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CN112272024B - Refreshing method, circuit and storage medium for configuration data of FPGA device - Google Patents

Refreshing method, circuit and storage medium for configuration data of FPGA device Download PDF

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Publication number
CN112272024B
CN112272024B CN202011181814.1A CN202011181814A CN112272024B CN 112272024 B CN112272024 B CN 112272024B CN 202011181814 A CN202011181814 A CN 202011181814A CN 112272024 B CN112272024 B CN 112272024B
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configuration data
fpga
fpga device
refreshing
controlled
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CN112272024A (en
Inventor
朱志新
王佳承
何允灵
朱亚军
李铁明
刘鑫
李�昊
朱一骄
丁雪玲
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State Nuclear Power Automation System Engineering Co Ltd
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State Nuclear Power Automation System Engineering Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G06F11/1469—Backup restoration techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)

Abstract

The invention discloses a refreshing method of configuration data of an FPGA device, which comprises the following steps: s11, storing configuration data backup of an FPGA device; s12, detecting whether configuration data of the FPGA device is wrong, if so, executing a step S13; s13, refreshing the configuration data of the FPGA device by using the configuration data backup. According to the invention, by detecting the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data backup of the FPGA device is obtained from the configuration data storage chip, and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is improved, the working reliability of the FPGA device is improved, and the safety is improved.

Description

Refreshing method, circuit and storage medium for configuration data of FPGA device
Technical Field
The invention relates to the technical field of industrial control, in particular to a refreshing method, a circuit and a storage medium of configuration data of an FPGA device.
Background
Reconfigurable FPGA (Field Programmable Gate Array ) devices based on Static Random-Access Memory (SRAM) structures can enter a working state after configuration data are read into an on-chip SRAM when power is supplied. After the FPGA device is powered down, configuration data in the on-chip SRAM is lost, and the internal logic relationship of the FPGA device disappears. When the FPGA device works in a radiation environment (such as nuclear power), the on-chip SRAM is easily affected by single event upset (namely bit upset), so that bits in a storage unit are overturned, thereby causing storage data errors and losing functions.
Configuration data in an on-chip SRAM of the FPGA device is easy to generate errors (including losses), once errors occur, the errors can be found only after a long time, the configuration data loaded in the FPGA device needs to be manually refreshed, the efficiency of detecting the configuration data and correcting errors is low, the working reliability of the FPGA device is reduced, and the safety is lowered.
Disclosure of Invention
The invention aims to overcome the defects that configuration data in an on-chip SRAM of an FPGA device is easy to generate errors (including losses) in the prior art, and once the errors occur, the configuration data loaded in the FPGA device needs to be manually refreshed after long time, so that the working reliability of the FPGA device is reduced, the efficiency of detecting the configuration data and correcting errors is low, and the safety is reduced.
The invention solves the technical problems by the following technical scheme:
the invention provides a refreshing method of configuration data of an FPGA device, which comprises the following steps:
s11, storing configuration data backup of an FPGA device;
s12, detecting whether configuration data of the FPGA device is wrong, if so, executing a step S13;
s13, refreshing the configuration data of the FPGA device by using the configuration data backup.
Preferably, the step S12 includes the steps of:
and comparing whether the configuration data of the FPGA device is the same as the corresponding configuration data backup of the FPGA device.
Preferably, the FPGA device comprises a master control FPGA and a controlled FPGA;
the step S11 specifically includes:
storing the configuration data backup of the master control FPGA in a first storage chip, and storing the configuration data backup of the controlled FPGA in a second storage chip;
the step S12 specifically includes:
detecting whether the configuration data of the master control FPGA is wrong, if so, executing a step S13;
and the master control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if so, step S13 is executed.
Preferably, a plurality of controlled FPGAs are sequentially connected to form a cascade controlled FPGA;
step S12 further includes:
and the master control FPGA detects whether the configuration data of any controlled FPGA in the cascade controlled FPGAs is wrong, and if so, the step S13 is executed.
Preferably, after step S13, the method for refreshing configuration data further includes the following steps:
s14, after the corresponding configuration data of the FPGA device is refreshed, the FPGA device generates a refresh operation completion indication signal.
The invention also provides a refreshing system of the configuration data of the FPGA device, which comprises at least one FPGA device, a refreshing module and a first memory chip;
the refreshing module is respectively and electrically connected with the FPGA device and the first storage chip;
the first memory chip is used for storing configuration data backup of the FPGA device;
and the refreshing module is used for detecting whether the configuration data of the FPGA device is wrong or not, and if so, refreshing the configuration data of the FPGA device by using the configuration data backup.
Preferably, the refreshing module is configured to compare whether the configuration data of the FPGA device is the same as the corresponding configuration data backup of the FPGA device, and if not, refresh the configuration data of the FPGA device using the configuration data backup.
Preferably, the FPGA device comprises a master control FPGA and a controlled FPGA;
the refresh system further includes a second memory chip;
the main control FPGA is electrically connected with the refreshing module, the second storage chip and the controlled FPGA respectively;
the first memory chip is used for storing the configuration data backup of the master control FPGA, and the second memory chip is used for storing the configuration data backup of the controlled FPGA;
the refreshing module comprises a first detecting unit and a first refreshing unit, wherein the first detecting unit is used for detecting whether the configuration data of the main control FPGA is wrong, and if yes, the first refreshing unit is called to use the configuration data backup to refresh the configuration data of the main control FPGA;
the main control FPGA comprises a second detection unit and a second refreshing unit, wherein the second detection unit is used for detecting whether the configuration data of the controlled FPGA is wrong, and if yes, the second refreshing unit is called to use the configuration data backup to refresh the configuration data of the controlled FPGA.
Preferably, a plurality of controlled FPGAs are sequentially connected to form a cascade controlled FPGA;
the second detection unit is further configured to detect whether configuration data of any controlled FPGA in the cascade controlled FPGAs is wrong, and if yes, call the second refreshing unit to use the configuration data backup to refresh the configuration data of the controlled FPGAs.
Preferably, the FPGA device further comprises a signal generating unit;
after the configuration data of the corresponding FPGA device is refreshed, the generating signal unit generates a refresh operation completion indicating signal.
The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the aforementioned method of refreshing configuration data of an FPGA device.
The invention has the positive progress effects that: by detecting the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data backup of the FPGA device is obtained from the configuration data storage chip, and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Drawings
Fig. 1 is a flow chart of a method for refreshing configuration data of an FPGA device in embodiment 1.
Fig. 2 is a flow chart of another implementation of the method for refreshing configuration data of the FPGA device of embodiment 1.
Fig. 3 is a flow chart of a method for refreshing configuration data of the FPGA device in embodiment 2.
Fig. 4 is a flowchart of a method for refreshing configuration data of the FPGA device in embodiment 3.
Fig. 5 is a schematic block diagram of a refresh system for configuration data of the FPGA device of embodiment 4.
Fig. 6 is a schematic block diagram of a refresh system for configuration data of the FPGA device of embodiment 5.
Fig. 7 is a schematic block diagram of a refresh system for configuration data of the FPGA device of embodiment 6.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a refreshing method of configuration data of an FPGA device. Referring to fig. 1, the refresh method includes the steps of:
s11, storing configuration data backup of an FPGA device.
S12, detecting whether configuration data of the FPGA device is wrong, and if so, executing the step S13.
S13, refreshing the configuration data of the FPGA device by using the configuration data backup.
S14, after the configuration data of the corresponding FPGA device is refreshed, the FPGA device generates a refresh operation completion indication signal.
In step S14, the FPGA device may indicate that the refresh of the configuration data is completed by the refresh operation completion indication signal.
According to the method for refreshing the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data backup of the FPGA device is obtained from the configuration data storage chip and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Referring to fig. 2, step S12 specifically includes the steps of:
s121, comparing whether the configuration data of the FPGA device is the same as the configuration data backup of the corresponding FPGA device.
If not, the configuration data of the FPGA device is wrong, and step S13 is executed.
According to the method for refreshing the configuration data of the FPGA device, the configuration data of the FPGA device is detected, when the configuration data of the FPGA device is different from the configuration data backup, the configuration data backup of the FPGA device is obtained from the configuration data storage chip, and the configuration data of the FPGA device is refreshed, so that configuration data errors of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 2
The method for refreshing configuration data of the FPGA device of the present embodiment is a further improvement of embodiment 1, specifically:
the FPGA device comprises a master control FPGA and a controlled FPGA.
Referring to fig. 3, step S11 specifically includes:
s111, storing configuration data backup of the master control FPGA in a first storage chip, and storing configuration data backup of the controlled FPGA in a second storage chip.
The step S12 specifically includes:
s122, detecting whether the configuration data of the master control FPGA is wrong, and if so, executing the step S13.
S123, the master control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if yes, step S13 is executed.
If the configuration data of the master control FPGA is wrong, the configuration data of the master control FPGA is refreshed in step S13; and if the configuration data of the controlled FPGA is wrong, refreshing the configuration data of the controlled FPGA in step S13.
According to the method for refreshing the configuration data of the FPGA device, under the condition that the configuration data errors of the master control FPGA are monitored and corrected, the configuration data errors of the controlled FPGA are monitored and corrected by the master control FPGA, so that the configuration data errors of the master control FPGA and the controlled FPGA can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is further improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 3
The method for refreshing configuration data of the FPGA device of the present embodiment is a further improvement of embodiment 2, specifically:
the controlled FPGAs are sequentially connected to form a cascade controlled FPGA.
Referring to fig. 4, step S12 further includes:
s124, the master control FPGA detects whether the configuration data of any controlled FPGA in the cascade controlled FPGAs is wrong, and if so, the step S13 is executed.
The method for refreshing the configuration data of the FPGA device further enriches the connection modes of the controlled FPGAs, and can monitor and correct configuration data errors of any controlled FPGA in the cascade controlled FPGAs.
Example 4
The embodiment provides a refreshing system for configuration data of an FPGA device. Referring to fig. 5, the refresh system includes at least one FPGA device 1, a refresh module 2, and a first memory chip 3.
The refresh module 2 is electrically connected to the FPGA device 1 and the first memory chip 3, respectively.
The first memory chip 3 is used for storing configuration data backups of the FPGA device 1.
The refreshing module 2 is configured to detect whether an error occurs in the configuration data of the FPGA device 1, and if so, use the configuration data backup to refresh the configuration data of the FPGA device 1.
In specific implementation, the refresh module 2 is configured to compare whether the configuration data of the FPGA device 1 is the same as the configuration data backup of the corresponding FPGA device 1, and if not, refresh the configuration data of the FPGA device 1 using the configuration data backup. If the configuration data of the FPGA device 1 is different from the corresponding configuration data backup of the FPGA device 1, it indicates that an error occurs in the configuration data of the FPGA device 1.
According to the refreshing system for the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data backup of the FPGA device is obtained from the configuration data storage chip and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 5
The system for refreshing configuration data of the FPGA device of the present embodiment is a further improvement of embodiment 4, specifically:
referring to fig. 6, the FPGA device 1 includes a master FPGA11 and a controlled FPGA12, the refresh system further includes a second memory chip 4, the refresh module 2 includes a first detection unit 21 and a first refresh unit 22, and the master FPGA11 includes a second detection unit 23 and a second refresh unit 24.
The main control FPGA11 is electrically connected with the refreshing module 2, the second memory chip 4 and the controlled FPGA12 respectively.
The first memory chip 3 is used for storing the configuration data backup of the master control FPGA11, and the second memory chip 4 is used for storing the configuration data backup of the controlled FPGA 12.
The first detecting unit 21 is configured to detect whether the configuration data of the main control FPGA11 is wrong, and if yes, call the first refreshing unit 22 to refresh the configuration data of the main control FPGA11 using the configuration data backup.
The second detecting unit 23 is configured to detect whether an error occurs in the configuration data of the controlled FPGA12, and if so, call the second refreshing unit 24 to refresh the configuration data of the controlled FPGA12 using the configuration data backup.
In the system for refreshing the configuration data of the FPGA device of the embodiment, under the condition of monitoring and correcting the configuration data errors of the master FPGA, the master FPGA monitors and corrects the configuration data errors of the controlled FPGA, so that the configuration data errors of the master FPGA and the controlled FPGA can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting errors is further improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 6
The system for refreshing configuration data of the FPGA device of the present embodiment is a further improvement of embodiment 5, specifically:
referring to fig. 7, a plurality of controlled FPGAs 12 are sequentially connected to form a cascade of controlled FPGAs 13.
The second detecting unit 23 is further configured to detect whether the configuration data of any controlled FPGA12 in the cascade controlled FPGAs 13 is wrong, and if yes, call the second refreshing unit 24 to refresh the configuration data of the controlled FPGAs 12 using the configuration data backup.
The refreshing system for the configuration data of the FPGA device further enriches the connection modes of the controlled FPGAs, and can monitor and correct configuration data errors of any controlled FPGA in the cascade controlled FPGAs.
In one embodiment, the FPGA device 1 further includes a generating signal unit that generates a refresh operation completion instruction signal after the configuration data of the corresponding FPGA device 1 is completely refreshed.
In specific implementation, when the refresh module 2 detects an error of configuration data of the FPGA device 1, the FPGA device 1 sends a refresh operation completion instruction signal to the refresh module 2 after finishing refreshing the configuration data. In the case where the master FPGA11 detects a configuration data error of the controlled FPGA12, the controlled FPGA12 transmits a refresh operation completion instruction signal to the master FPGA11 after finishing refreshing the configuration data.
In the system for refreshing the configuration data of the FPGA device of this embodiment, the FPGA device may complete the refresh of the configuration data by using a refresh operation completion indication signal.
Example 7
The present embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of refreshing configuration data of an FPGA device in any one of embodiments 1, 2 or 3.
More specifically, among others, readable storage media may be employed including, but not limited to: portable disk, hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible implementation manner, the present invention may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps of implementing the method for refreshing configuration data of an FPGA device in any of embodiments 1, 2 or 3, when said program product is run on the terminal device.
Wherein the program code for carrying out the invention may be written in any combination of one or more programming languages, which program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on the remote device or entirely on the remote device.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims (9)

1. The method for refreshing the configuration data of the FPGA device is characterized by comprising the following steps of:
s11, storing configuration data backup of an FPGA device;
s12, detecting whether configuration data of the FPGA device is wrong, if so, executing a step S13;
s13, refreshing the configuration data of the FPGA device by using the configuration data backup;
the FPGA device comprises a master control FPGA and a controlled FPGA;
the step S11 specifically includes:
storing the configuration data backup of the master control FPGA in a first storage chip, and storing the configuration data backup of the controlled FPGA in a second storage chip;
the step S12 specifically includes:
detecting whether the configuration data of the master control FPGA is wrong, if so, executing a step S13;
and the master control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if so, step S13 is executed.
2. The method for refreshing configuration data of an FPGA device according to claim 1, wherein step S12 includes the steps of:
and comparing whether the configuration data of the FPGA device is the same as the corresponding configuration data backup of the FPGA device.
3. The method for refreshing configuration data of an FPGA device of claim 1, wherein a plurality of controlled FPGAs are sequentially connected to form a cascade controlled FPGA;
step S12 further includes:
and the master control FPGA detects whether the configuration data of any controlled FPGA in the cascade controlled FPGAs is wrong, and if so, the step S13 is executed.
4. The method for refreshing configuration data of an FPGA device according to claim 1, wherein after step S13, the method for refreshing configuration data further comprises the steps of:
s14, after the corresponding configuration data of the FPGA device is refreshed, the FPGA device generates a refresh operation completion indication signal.
5. The refreshing system of the configuration data of the FPGA device is characterized by comprising at least one FPGA device, a refreshing module and a first memory chip;
the refreshing module is respectively and electrically connected with the FPGA device and the first storage chip;
the first memory chip is used for storing configuration data backup of the FPGA device;
the refreshing module is used for detecting whether the configuration data of the FPGA device is wrong or not, and if yes, the configuration data of the FPGA device is refreshed by using the configuration data backup;
the FPGA device comprises a master control FPGA and a controlled FPGA;
the refresh system further includes a second memory chip;
the main control FPGA is electrically connected with the refreshing module, the second storage chip and the controlled FPGA respectively;
the first memory chip is used for storing the configuration data backup of the master control FPGA, and the second memory chip is used for storing the configuration data backup of the controlled FPGA;
the refreshing module comprises a first detecting unit and a first refreshing unit, wherein the first detecting unit is used for detecting whether the configuration data of the main control FPGA is wrong, and if yes, the first refreshing unit is called to use the configuration data backup to refresh the configuration data of the main control FPGA;
the main control FPGA comprises a second detection unit and a second refreshing unit, wherein the second detection unit is used for detecting whether the configuration data of the controlled FPGA is wrong, and if yes, the second refreshing unit is called to use the configuration data backup to refresh the configuration data of the controlled FPGA.
6. The system of claim 5, wherein the refresh module is configured to compare whether the configuration data of the FPGA device is the same as the corresponding configuration data backup of the FPGA device, and if not, refresh the configuration data of the FPGA device using the configuration data backup.
7. The system for refreshing configuration data of an FPGA device of claim 5 wherein a plurality of said controlled FPGAs are sequentially connected to form a cascade of controlled FPGAs;
the second detection unit is further configured to detect whether configuration data of any controlled FPGA in the cascade controlled FPGAs is wrong, and if yes, call the second refreshing unit to use the configuration data backup to refresh the configuration data of the controlled FPGAs.
8. The system for refreshing configuration data of an FPGA device of claim 5, wherein said FPGA device further comprises a generate signal unit;
after the configuration data of the corresponding FPGA device is refreshed, the generating signal unit generates a refresh operation completion indicating signal.
9. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of refreshing configuration data of an FPGA device of any of claims 1-4.
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