CN112202530A

CN112202530A - Channel blind detection method and device, communication device and storage medium

Info

Publication number: CN112202530A
Application number: CN202011062223.2A
Authority: CN
Inventors: 任江涛; 邓敬贤; 胡剑锋; 张国松
Original assignee: Beijing Sigbean Information Technology Co ltd
Current assignee: Core Semiconductor Technology Beijing Co ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2021-01-08
Anticipated expiration: 2040-09-30
Also published as: CN112202530B

Abstract

Disclosed are a channel blind detection method and apparatus, a communication apparatus and a storage medium. The method comprises the steps of obtaining a first bit sequence of a subframe signal under the number of candidate antenna ports and the frame head index of a candidate sub-period by receiving the subframe signal sent by a narrow-band physical broadcast channel NPBCH in a sub-period, determining the initial position of the first bit sequence according to the frame head index of the candidate sub-period, performing rate de-matching on the first bit sequence according to the initial position to obtain a second bit sequence, decoding and checking the second bit sequence to obtain a checking result, and determining the number of the candidate antenna ports and the frame head index of the candidate sub-period corresponding to a third bit sequence with correct checking result as the number of the antenna ports and the frame head index of the sub-period corresponding to the subframe signal. Therefore, the cache and calculation amount of the de-rate matching can be reduced, and the blind detection efficiency is improved.

Description

Channel blind detection method and device, communication device and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a channel blind detection method and apparatus, a communication apparatus, and a storage medium.

Background

The NB-IoT (Narrow Band Internet of Things) system has the characteristics of low speed, low power consumption, low cost, high capacity, wide coverage, multiple connections, and the like. The NB-IoT NPBCH (Narrow Band physical broadcast channel) is used for MIB-NB (master information block-Narrow Band) carrying system broadcast information. The MIB-NB Information includes scheduling Information and operation mode type of SIB1(System Information Block), and the like.

After a sending end of the downlink control information determines related data to be sent, processes such as Cyclic Redundancy Check (CRC), channel coding, rate matching, winding, modulation, mapping preprocessing, resource mapping and the like are sequentially performed on the MIB-NB information, and the processed information is sent. If the receiving end needs to receive the MIB-NB information, blind detection needs to be carried out on the MIB-NB information, namely, the position of the MIB-NB information is searched on the search space obtained through calculation, the MIB-NB information at the position is decoded, the decoded MIB-NB information is sequentially subjected to resource de-mapping, rate de-matching, descrambling, channel de-coding, CRC (cyclic redundancy check) and other processing, and if the check result is correct after CRC (cyclic redundancy check) check, the blind detection is successful.

However, the blind detection method in the prior art needs to occupy a large cache, and the calculation amount is large.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method and an apparatus for blind channel detection, a communication apparatus, and a storage medium, which can reduce buffering and calculation amount of de-rate matching and improve blind detection efficiency.

In a first aspect, an embodiment of the present invention provides a channel blind detection method, where the method includes:

receiving at least one subframe signal sent by a narrowband physical broadcast channel NPBCH in a sub-period;

acquiring a first bit sequence corresponding to the sub-frame signal under the number of candidate antenna ports and the frame header index of the candidate sub-period;

determining the initial position of the first bit sequence according to the candidate sub-period frame header index;

performing rate de-matching on the first bit sequence according to the initial position to obtain a second bit sequence;

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

and determining the number of the candidate antenna ports and the candidate sub-period frame header index corresponding to the third bit sequence with correct verification result as the number of the antenna ports and the sub-period frame header index corresponding to the sub-frame signal, wherein the sub-period frame header index is used for representing the position of the sub-period of the sub-frame signal in the NPBCH period.

Preferably, the number of candidate antenna ports includes 1 and 2, and the candidate sub-period frame header indexes include 1, 2, 3, 4, 5, 6, 7, and 8.

Preferably, determining the start position of the first bit sequence according to the candidate sub-period frame header index includes:

responding to the candidate sub-period frame header index being 1, 4 or 7, wherein the starting position is 1;

responding to the candidate sub-period frame header index being 2, 5 or 8, wherein the starting position is 65; and

in response to the candidate sub-period frame header index being 3 or 6, the start position is 129.

Preferably, rate de-matching the first bit sequence according to the start position to obtain a second bit sequence comprises:

sequentially adding data in the second bit sequence to a plurality of data bits in a virtual circular buffer according to the starting position;

shunting data in the virtual circular buffer; and

and performing sub-block de-interleaving on the split data to acquire the second bit sequence.

Preferably, in response to receiving a plurality of subframe signals transmitted by the NPBCH within one subframe period, the method further includes:

and combining the received multiple subframe signals.

In a second aspect, an embodiment of the present invention provides a channel blind detection apparatus, where the apparatus includes:

a receiving unit, configured to receive at least one subframe signal sent by a narrowband physical broadcast channel NPBCH in a sub-period;

a first bit sequence obtaining unit, configured to obtain a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the frame header index of the candidate subframe;

an initial position determining unit, configured to determine an initial position of the first bit sequence according to the candidate sub-cycle frame header index;

a de-rate matching unit, configured to perform de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence;

a decoding unit, configured to perform decoding processing on the second bit sequence to obtain a corresponding third bit sequence;

the checking unit is used for checking the third bit sequence to obtain a checking result; and

and the determining unit is used for determining the number of the candidate antenna ports and the candidate sub-period frame header index corresponding to the third bit sequence with correct checking results as the number of the antenna ports and the sub-period frame header index corresponding to the sub-frame signal, wherein the sub-period frame header index is used for representing the position of the sub-period of the sub-frame signal in the NPBCH period.

In a third aspect, an embodiment of the present invention provides a communication apparatus, including a memory and a processor, where the processor executes program instructions in the memory, so as to implement the method in the first aspect.

In a fourth aspect, an embodiment of the present invention provides a storage medium, where the storage medium is used to store a computer program, and the computer program is used to implement the method in the first aspect.

The embodiment of the invention obtains a first bit sequence corresponding to the sub-frame signals under the number of candidate antenna ports and the frame head index of a candidate sub-period by receiving the sub-frame signals sent by a narrow-band physical broadcast channel NPBCH in a sub-period, determines the initial position of the first bit sequence according to the frame head index of the candidate sub-period, performs rate de-matching on the first bit sequence according to the initial position to obtain a second bit sequence, decodes and checks the second bit sequence to obtain a check result, and determines the number of the candidate antenna ports and the frame head index of the candidate sub-period corresponding to a third bit sequence with correct check result as the number of the antenna ports and the frame head index of the sub-period corresponding to the sub-frame signals. Therefore, the cache and calculation amount of the de-rate matching can be reduced, and the blind detection efficiency is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a communication system of an embodiment of the present invention;

FIG. 2 is a flowchart of data processing of an NPBCH of a transmitting apparatus according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating the number of antenna ports and the corresponding scrambling code sequence according to an embodiment of the present invention;

FIG. 4 is a block diagram of a virtual circular buffer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an inter-column permutation rule of an embodiment of the present invention;

FIG. 6 is a structural diagram of a channel time-frequency domain of NPBCH over one cycle according to an embodiment of the present invention;

FIG. 7 is a flowchart of a NPBCH blind detection method in the prior art;

FIG. 8 is a schematic diagram of a candidate sequence of the prior art;

fig. 9 is a flow chart of a blind channel detection method according to an embodiment of the present invention;

FIG. 10 is a flow chart of an embodiment of the present invention for obtaining a first bit sequence;

FIG. 11 is a diagram illustrating a relationship between candidate sub-period frame header indexes and start positions according to an embodiment of the present invention;

FIG. 12 is a flow chart of an embodiment of the present invention for obtaining a second bit sequence;

fig. 13 is a schematic structural diagram of a blind channel detection apparatus according to an embodiment of the present invention;

fig. 14 is a schematic hardware configuration diagram of a communication apparatus according to an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 1 is a schematic diagram of a communication system of an embodiment of the present invention. As shown in fig. 1, the communication system of the embodiment of the present invention includes a transmitting apparatus 11 and a receiving apparatus 12.

In this embodiment, the transmitting device 11 is a network device, and the receiving device 12 is a terminal device.

Further, the transmitting device 11 includes an encoder so that the transmitting device 11 can perform encoding and output an encoded sequence. The encoded sequence is scrambled, modulated, layer mapped and precoded, RE mapped and generates a baseband signal, which is transmitted to the receiving device 12. The receiving device 12 includes a decoder, and the receiving device 12 can receive the signal transmitted by the transmitting device 101 and decode the received signal.

It should be understood that fig. 1 is merely an architectural diagram illustrating a communication system by way of example and is not intended to limit the architecture of the communication system.

In the communication process, the sending end encodes the information to obtain a bit sequence to be sent and sends the bit sequence to be sent. The receiving end demodulates the received signal to obtain a set of log-Likelihood ratios (LLRs), and the number of LLRs included in the set of LLRs is the same as the number of bits included in the bit sequence to be transmitted. And the receiving end decodes according to the received group of LLRs. Regardless of whether the sending end sends bit 1 or bit 0, the receiving end may misjudge. For the signal r, the ratio of the probability p (r | b ═ 0) of correctly determining 0 to the probability p (r | b ═ 1) of correctly determining 1 at the receiving end is the likelihood ratio. For the convenience of calculation processing, the likelihood ratio is taken as a natural logarithm, and a log likelihood ratio, that is, LLR ═ ln [ p (r | b ═ 0)/p (r | b ═ 1) ].

Further, the receiving device 12 includes, but is not limited to, a Mobile Station (MS), a Mobile Terminal (MT), a Mobile phone (MT), a handset (handset), and a portable device (portable equipment), and the Terminal device may communicate with one or more core networks through a Radio Access Network (RAN). For example, the terminal equipment may be a mobile phone, a computer with wireless communication capability, etc., and the terminal equipment may also be a portable, pocket, hand-held, computer-included, or vehicle-mounted mobile device or apparatus.

Further, the transmitting device 11 may be an NB-IoT base station, or a base station of a network including other multi-technology convergence of NB-IoT, and the like.

Further, the embodiment of the invention decodes the data of the NB-IoT network downlink channel.

Further, the embodiment of the invention decodes the downlink data of the NPBCH of the NB-IoT network.

Alternatively, the data processing flow of NPBCH of the transmitting device 11 can refer to fig. 2, and includes the following steps:

and step S110, channel coding.

In this embodiment, the channel coding process of NPBCH includes the following steps:

step S111, CRC (Cyclic Redundancy Check) Check.

In this embodiment, CRC is a channel coding technique that generates a short fixed bit check code from a network packet, and is mainly used to detect or check errors that may occur after data transmission or storage.

Further, the MIB-NB information is 34-bit data, and a CRC sequence length of 16 bits is added during verification, so that the output after verification is 50-bit data.

Further, after the check bits are added, the CRC sequence is wrapped by using a specific antenna port number scrambling sequence according to the number of antenna ports configured by the base station, and the number of antenna ports and the corresponding scrambling sequence are as shown in fig. 3 below. Wherein,<x_ant,0，x_ant,1，x_ant,2，…，x_ant,15>is an added CRC-Mask sequence. The number of the antenna ports of the transmitting end can only be 1 or 2, when the number of the antenna ports of the transmitting end is 1, the data in the CRC-Mask sequence are all 0, and when the number of the antenna ports of the transmitting end is 2, the data in the CRC-Mask sequence are all 1.

Step S112, TBCC encoding.

In this embodiment, the coding principle of TBCC (Tail Biting CC) coding is as follows: when the encoder starts to work, special initialization is carried out, the last m bits of the input information bits are sequentially input into a register of the encoder, and when the encoding is finished, the finishing state of the encoder is the same as the initial state. Since this coding method does not have tail bits, it is called tail-biting coding. The TBCC codes carry out channel coding on the control information and the broadcast channel, thereby enhancing the robustness, reducing the coding cost of tail bits, overcoming the problem of code rate loss and being suitable for iterative decoding.

Further, after the information bits are input into the TBCC encoding module and are TBCC encoded, the bit number of the output information is 3 times of the bit number of the input information. Representing the input bit as A₁，A₂，A₃，……，A_kWhere k is the number of bits of the input information and the output information is d₁₁，d₁₂，d₁₃，……d_1kAnd, d₂₁，d₂₂，d₂₃，……d_2kAnd, d₃₁，d₃₂，d₃₃，……d_3k。

Further, k is 50.

In the present embodiment, the encoding rate of tail-biting convolutional encoding is 1/3. That is, the TBCC encoder has 50 bits of input information and 3 × 50 bits of output information.

And step S113, rate matching.

In the present embodiment, the output information of the TBCC encoding module is converted into data of a predetermined length through rate matching.

Further, the output data of 3 x 50 bits of the TBCC encoding module is converted into data of 1600 bits by rate matching. Specifically, the rate matching is implemented by a virtual circular buffer, the structure of which can be referred to fig. 4, including three

sub-block interleavers

41, 42, and 43, a bit collection unit 44, and a bit selection unit 45.

In this embodiment, the data d obtained by encoding in step S112 is₁₁，d₁₂，d₁₃，……，d_1kInput to a sub-block interleaver 41₂₁，d₂₂，d₂₃，……d_2kInput to a sub-block interleaver 42, and d is₃₁，d₃₂，d₃₃，……d_3kInput to the sub-block interleaver 43. Wherein k is 50.

In the present embodiment, the work flow of the sub-block interleaver 41 includes the following steps:

step S1131, determine the number of matrix columns.

In this embodiment, the number C of matrix columns is determined to be 32, and the sequence numbers of the columns are denoted as

sequence numbers

1, 2, 3, … …, and 32 from left to right.

And step S1132, determining the number of matrix rows.

In this embodiment, the sub-block interleaver obtains the number of matrix rows according to the determined number of matrix columns. Specifically, it can be obtained according to the following formula:

D≤(R*C)

wherein D is the bit number of the input information of the sub-block interleaver, R is the matrix row number, and C is the matrix column number.

Further, R is the smallest integer satisfying the above formula.

Further, D ═ k ═ 50 and C ═ 32 can be determined, and from this, R ═ 2 can be calculated.

Further, each row of the matrix is denoted by the

numbers

1, 2 from top left to bottom.

From this, a 2 x 32 matrix can be obtained.

Step S1133, add the input information to the matrix.

In the present embodiment, the matrix of 2 × 32 has 64 data bits in total, and the number of input bits is 50, so that 14 dummy bits need to be added to the header, and then the number of bits of input information needs to be added to other positions of the matrix.

Specifically, the data is added row by row starting from the 0 th row and the 0 th column of the matrix, 14 dummy bits are added first, and then 50-bit data of the input information is sequentially added to the matrix.

Step S1134, inter-column permutation.

In this embodiment, the matrix obtained as described above is subjected to inter-column permutation according to a predetermined rule. Specifically, the permutation rule is as shown in fig. 5. Recording each column of the matrix after replacement as P from left to right₁，P₂，P₃，……，P₃₂It can be known that P₁，P₂，P₃，……，P₃₂The

column numbers

2, 18, 10, 26, 6, 22, 14, 30, 4, 20, 12, 28, 8, 24, 16, 32, 1 before the replacement, respectively7，9，25，5，21，13，29，3，19，11，27，7，23，15，31。

The sub-block interleaver 41 thus obtains a first permutation matrix of 2 x 32.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 2 × 32 according to the same procedure as described above.

In the present embodiment, the bit collection unit 44 performs data collection according to the first permutation matrix, the second permutation matrix, and the third permutation matrix described above.

In particular, the bit sequence is read out from the first permutation matrix column by column in left to right order, denoted v₁₁，v₁₂，v₁₃，……，v_1mWherein m is 64. Reading out a bit sequence, denoted v, from the second permutation matrix₂₁，v₂₂，v₂₃，……，v_2mWherein m is 64. Reading out a bit sequence, denoted v, from a third permutation matrix₃₁，v₃₂，v₃₃，……，v_3mWherein m is 64. Let the ith (i ═ 1, 2, 3, … …, 191, 192) data of the virtual circular buffer be denoted as w_iAnd then:

that is, the m bit sequences read out from the first permutation matrix are added in sequence to the 1 st to the m th positions of the virtual circular buffer, the m bit sequences read out from the second permutation matrix are added in sequence to the m +1 st to the 2m th positions of the virtual circular buffer, and the m bit sequences read out from the third permutation matrix are added in sequence to the 2m +1 th to the 3m th positions of the virtual circular buffer.

Further, since m is 64, the virtual circular buffer has 3 × m 192bit of data in common.

In this embodiment, the bit selection unit 45 is configured to generate a bit sequence e of a predetermined length n.

Further, the bit selection unit 45 is configured to generate a sequence of n 1600 bits.

Further, the length of the transmission period of the NPBCH is 640ms, the NPBCH is divided into 8 80ms sub-periods, and the NPBCH is transmitted in the form of a repeated empty signal in the sub-periods, so that the NPBCH information bit carried in each sub-period is 100 information amount carried by the REs under the QPSK modulation condition, that is, 200 bits, and the 8 sub-periods total 1600 bits. Thus requiring a rate-matched output sequence length of 1600 bits.

Specifically, the bit selection unit 45 selects one data from the virtual circular buffer in a predetermined order, determines whether the data is a dummy bit, adds the data to 1600 bits if the data is not a dummy bit, and skips the data to select the next data to continue processing until 1600 bits are filled.

Further, according to the above principle, it can be known that the virtual circular buffer shares 3 × 64 bits of data, and each 64bit of data includes 50 bits of valid data, so that every 200 bits (4 × 50 bits) are filled, and it is necessary to read 4 × 64 bits of data in the virtual circular buffer. From this, in 192 bits of data in the virtual circular buffer:

the first 200bit, the starting position k0 is 1;

the second 200bit, start position k0 is 65;

the third 200bit, starting position k0 is 129;

the fourth 200bit, the start position k0 is 1;

the fifth 200bit, start position k0 is 65;

the sixth 200bit, starting position k0 is 129;

seventh 200bit, start position k0 is 1;

the eighth 200bit, start position k0 is 65.

That is, the start position of the 1 st, 4 th, and 7 th 200-bit data is 1, the start position of the 2 nd, 5 th, and 8 th 200-bit data is 65, and the start position of the 3 rd and 6 th 200-bit data is 129.

Thus, 1600bit data e can be generated by rate matching₁，e₂，e₃，……，e_n，n＝1600。

And step S120, scrambling.

In this embodiment, scrambling is performed by multiplying spreading codes by a random code sequence to encrypt signals, and downlink scrambling may be used to distinguish between cells and channels.

Further, the scrambling formula is as follows:

wherein,

is the h data after scrambling, e (h) is the h data after rate matching, c (h) is the h data in the random sequence, and h is more than or equal to 1 and less than or equal to 1600.

In particular, since e (h) and c (h) are 0 or 1, the scrambling is actually determined from c (h) in the random sequence

When c (h) is 0, the ratio,

when c (h) is 1, the ratio,

0/1 transformation is performed. Namely:

when e (h) is 0, c (h) is 0,

when e (h) is 0, c (h) is 1,

when e (h) is 1, c (h) is 0,

when e (h) ═When 1, c (h) is 1,

step S130, QPSK modulation.

In this embodiment, NPDSCH employs a QPSK (Quadrature Phase Shift Keying) modulation scheme. QPSK uses four different phase differences of the carrier to represent the input digital information, and is quaternary phase shift keying. QPSK is a phase modulation technique when M is 4, which specifies four carrier phases, 45 °, 135 °, 225 °, 315 °, and the data input to the modulator is a sequence of binary digits, and the binary data needs to be converted into quad data in order to match the quaternary carrier phases.

Specifically, 1600-bit data obtained by scrambling as described above is divided into 8 200 bits. For each 200bit, every two bits in the binary digit sequence are grouped into four combinations, namely 00, 01, 10, 11, where each group is referred to as a bi-bit symbol. Each dibit symbol is composed of two binary information bits, which respectively represent one symbol (symbol) of four quaternary symbols. In QPSK, 2 information bits can be transmitted per modulation, which are conveyed by four phases of the carrier. The demodulator judges the information bits sent by the sending end according to the phase of the received carrier signal.

Step S140, layer mapping and pre-coding.

In this embodiment, since the number of codewords is different from the number of transmit antenna ports, the codewords need to be mapped to different antenna ports. The number of layers is indicated by RI (Rank Indication), and Rank is a Rank in an antenna matrix in a MIMO (multiple input multiple output) scheme, that is, a data stream capable of independent parallel transmission. RANK tells the network side the number of layers that can be effectively supported by the terminal. If the receiving end supports at most two antenna ports, the maximum value of the rank can only be 2. The NPBCH jointly completes the function of MIMO by layer mapping and precoding. The process is that firstly, the code word complex value modulation symbol to be transmitted is mapped to one or more layers through layer mapping, the serial-parallel conversion is completed, the multiplexing rate of the space multiplexing is controlled, and then the data after the layer mapping is precoded, namely, the MIMO coding is realized. The precoding is used for matching layer data to an antenna port, and simultaneously reduces or controls interference between spatial multiplexing data streams, reduces complexity of implementation of a receiver, and reduces system overhead, thereby improving performance of the MIMO technology.

And step S150, RE mapping.

In this embodiment, Resource Element (RE) mapping processes output of precoding, which is subjected to random phase offset, and then maps the output to an allocated RB (Resource Block) Resource, and the mapping process follows the principle of first Frequency domain and then time domain, that is, first all REs of an OFDM (Orthogonal Frequency Division Multiplexing) symbol are filled, and then the next OFDM symbol is filled.

Step S160, baseband signal generation.

In this embodiment, the baseband signal is an original electrical signal transmitted from a source (transmitting end). Specifically, the method for generating the baseband signal may adopt various existing technologies, and is not described herein again. Thus, a transmission signal can be generated.

Specifically, a structure diagram of a channel time-frequency domain over one period of NPBCH can be referred to fig. 6. As shown in FIG. 6, one period of NPBCH is 640ms, and is divided into 8 sub-periods, each of which is 80 ms. Each sub-period transmits a segment of 200-bit data, so that 1600-bit data is transmitted exactly over 8 periods. Meanwhile, each sub-period is divided into 8 10ms, and the MIB-NB signal is transmitted in the 1 st ms of each 10ms, so that each 200-bit segment of data is repeatedly transmitted 8 times in each sub-period.

It should be understood that the signal processing of the NPBCH is only one implementation manner of the embodiment of the present invention, and the embodiment of the present invention is not limited thereto, and may be implemented in various existing manners.

Further, in order to obtain the MIB-NB information, the receiving device 12 needs to perform blind detection on the MIB-NB information, that is, search the calculated search space for the location where the MIB-NB information is located, and decode the MIB-NB information at the location.

FIG. 7 is a flowchart of a NPBCH blind detection method in the prior art. As shown in fig. 7, the NPBCH blind detection method of the prior art includes the following steps:

step S210, obtaining soft bit LLR.

In this embodiment, the receiving device may obtain the frame header of the received signal in 80ms in the time domain through cell search, that is, a certain 80ms starting position in a 640ms period. Soft bit LLRs for the received subframe signal are obtained.

Specifically, sampling is carried out at a preset rate, a cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB-NB data and related pilot frequency data in a time domain are obtained; performing Fourier transform to generate frequency domain data of the subframe; blind detection is carried out on the number of the antenna ports, if the number of the antenna ports is 1, the corresponding port number p is 2000, if the number of the antenna ports is 2, the corresponding port number p is 2000, and if p is 2001; calculating an NRS mapping position corresponding to an antenna port number, extracting a NRS (Narrow-band reference signal), and performing channel estimation by using a locally generated NRS sequence and an NRS signal in received data to recover a signal at a transmitting end; performing resource de-mapping, eliminating resource grids occupied by a Reference Signal LTE-CRS (Cell-Specific Reference Signal) and an NRS (non-Reference Signal), and sequentially taking out complex value symbols from the positions of the resource grids; performing de-layer mapping and pre-coding according to the number of the antenna ports; demodulating each complex-valued symbol into two bit data by de-QPSK modulation; therefore, the soft bit LLR of 200 bits corresponding to the sub-frame signals when the number of the antenna ports is 1 and 2 respectively can be obtained.

Further, if a plurality of subframe signals in the same sub-period are received, the soft bit LLR of 200 bits corresponding to each subframe signal is obtained, and the soft bit LLRs of 200 bits corresponding to each subframe signal are combined. The soft bit LLR combining method may adopt various existing combining methods, which is not limited in this embodiment of the present invention. For example, the combining method may be equal ratio combining, saturation adding, etc.

And S220, descrambling.

In this embodiment, a random sequence of each sub-period when the sending device scrambles is obtained, and the obtained 200-bit data is descrambled according to the random sequence.

Further, according to the step S120, it can be known that, when the sending device performs scrambling, each bit of data sent by the sending device corresponds to one data in the random sequence, so that each 200-bit sent data corresponds to one 200-bit random sequence, and the received data is descrambled according to the random sequence during scrambling to recover the data of the sending device before scrambling.

Further, according to the step S210, 200-bit soft bit LLRs corresponding to the subframe signals when the number of antenna ports is 1 and 2, respectively, can be obtained. And acquiring random sequences of each sub-period when the sending equipment scrambles, and descrambling the obtained soft bit LLR (bit likelihood ratio) of 200 bits according to the random sequences of each sub-period so as to acquire descrambling sequences respectively corresponding to 8 sub-periods when the number of antenna ports is 1 and descrambling sequences respectively corresponding to 8 sub-periods when the number of antenna ports is 2. That is, 16 200-bit data are obtained by descrambling according to the number of antenna ports and the different sub-periods.

And step S230, rate de-matching.

In this embodiment, the rate de-matching is the inverse process of the step S113, and specifically includes the following steps:

and step S231, determining candidate sequences.

In the present embodiment, at the time of rate de-matching, a candidate sequence that needs to be rate de-matched is determined.

Specifically, 16 200-bit data are obtained through descrambling, and a corresponding candidate sequence is determined according to the number of antenna ports and a sub-period corresponding to each 200-bit data. The 200-bit data obtained above is put into the sub-period, and the data in other sub-periods are filled with 0, so that 1600-bit data can be obtained, and therefore, when the number of the antenna ports is 1, 8 conditions are obtained, and 8 1600-bit data are correspondingly obtained. Similarly, when the number of the antenna ports is 2, there are 8 cases, and 8 1600-bit data are correspondingly obtained.

Fig. 8 shows a candidate sequence of the number of antenna ports, where X is a header index of a sub-period frame. Specifically, when X is equal to i (i is equal to 1, 2, 3, 4, 5, 6, 7, 8), the data in the ith sub-period of the 200-bit data obtained above is filled with 0 in the other sub-periods.

It should be understood that fig. 8 only shows one candidate sequence for the number of antenna ports, and since there may be two cases for the number of antenna ports, there are 16 candidate sequences, each of which is 1600 bits.

And step S232, rate de-matching.

In this embodiment, the receiving device obtains, through the control information, the length D of the original sequence sent by the sending device, where the original sequence is a sequence obtained through CRC check, that is, D is 50 bits. Further, the virtual circular buffer is constructed according to the original sequence length, specifically referring to fig. 4 and 5, and includes the following steps:

step S2321, determining the number of matrix columns.

sequence numbers

1, 2, 3, … …, and 32 from left to right.

And S2322, determining the number of matrix rows.

D≤(R*C)

Further, R is the smallest integer satisfying the above formula.

Further, D may be determined to be 50, C may be determined to be 32, and from this, R may be calculated to be 2.

Further, each row of the matrix is denoted by the

numbers

1, 2 from top left to bottom.

From this, a 2 x 32 matrix can be obtained.

And S2323, adding the information into the matrix.

In the present embodiment, the 2 × 32 matrix has 64 data bits, and the number of bits of the original sequence is 50, so that 14 dummy bits need to be added to the header, and then valid information needs to be added to other positions of the matrix.

Specifically, the data is added row by row starting from the 0 th row and the 0 th column of the matrix, 14 dummy bits are added first, and then 50 bits of data are sequentially added to the matrix.

And S2324, performing inter-column replacement.

column numbers

2, 18, 10, 26, 6, 22, 14, 30, 4, 20, 12, 28, 8, 24, 16, 32, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31 before the substitution, respectively.

The sub-block interleaver 41 thus obtains a first permutation matrix of 32 x 2.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 32 × 2 according to the same procedure.

In particular, the bit sequence is read out from the first permutation matrix column by column in left to right order, denoted v₁₁，v₁₂，v₁₃，……，v_1mWherein m is 64. Reading out a bit sequence, denoted v, from the second permutation matrix₂₁，v₂₂，v₂₃，……，v_2mWherein m is 64. Reading out a bit sequence, denoted v, from a third permutation matrix₃₁，v₃₂，v₃₃，……，v_3mWherein m is 64. Recording the ith data of the virtual circular buffer as w_iAnd then:

Thus, a virtual circular buffer is obtained.

Step S2325, add the candidate sequence to the virtual circular buffer.

In this embodiment, the candidate sequence obtained as described above is added to the virtual circular buffer.

Further, for each candidate sequence, 1600 bits of data are added to 192 data bits in the virtual circular buffer.

Specifically, 150 valid bits and 42 dummy bit positions out of 192 data bits can be known from the above-described step of constructing the virtual circular buffer. First, selecting the first bit in the candidate sequence, selecting the first data bit in the virtual circular buffer, judging whether the data bit is a valid bit, if the data bit is a valid bit, filling the selected bit into the data bit, if the data bit is not a valid bit, selecting the next data bit in the virtual circular buffer, and continuing the judgment. If the currently processed data bit is the last data bit of the 192 bits, the first data bit is returned at the next processing. The above steps are repeated until 1600 bits of data are all added to 192 data bits.

Further, for each data bit, multiple bits of data are received, and the multiple bits of data are combined. Thus, 192bit data can be obtained.

Step S2326, bit shunting.

In this embodiment, the obtained 192-bit data is bit-shunted to obtain 3 × 64-bit data.

Specifically, 1-64 bits of data of 192 bits are taken out to generate a 64-bit sequence, which is denoted as v₁₁，v₁₂，v₁₃，……，v_1mWherein m is 64. Taking out 65-128 bits of data to generate a 64-bit sequence, which is marked as v₂₁，v₂₂，v₂₃，……，v_2mWherein m is 64. The 129-bit 192-bit data is taken out to generate a 64-bit sequence which is marked as v₃₁，v₃₂，v₃₃，……，v_3mWherein m is 64. Thus, 3 x 64bit data can be obtained.

Step S2327, sub-block de-interleaving.

In this embodiment, each 64-bit data obtained as described above is added to a 2 × 32 matrix. The data of 3 × 50 bits can be obtained through the process of step S2324 and the reverse process of step S2323.

Further, 3 x 50bit data of 16 candidate sequences can be obtained by the same method.

And step S240, decoding.

In this embodiment, the 16 kinds of data of 3 × 50 bits obtained above are respectively subjected to TBCC decoding to obtain 16 data of 50 bits.

Further, the TBCC decoding may adopt various existing methods, which are not limited herein.

And step S250, CRC is decoded.

In this embodiment, 16 check results are obtained by performing CRC decoding on the 16 data with 50 bits, respectively.

Further, the number of antenna ports and the frame header index of the sub-period corresponding to the condition that the checking result is correct are obtained as the decoding result.

However, in the prior art, the buffer and the calculation amount are large during rate de-matching, and as described above, the buffer that needs to be occupied before rate de-matching is 16 × 1600 bits, and the calculation amount is 16 × 1600 bits.

Further, according to the sum rate matching process of the sending device, it is known that: the start position k0 of the 1 st, 4 th and 7 th 200bit data is set to 1, the start position k0 of the 2 nd, 5 th and 8 th 200bit data is 65, and the start position k0 of the 3 rd and 6 th 200bit data is 129. Therefore, the embodiment of the invention provides a channel blind detection method, so as to reduce the cache and calculation amount of de-rate matching and improve the blind detection efficiency. As shown in fig. 9, the method includes the following steps:

step S310, at least one subframe signal sent by a narrow-band physical broadcast channel NPBCH in a sub-period is received.

In this embodiment, the receiving device may obtain the frame header of the received signal in 80ms in the time domain through cell search, that is, a certain 80ms starting position in a 640ms period. And receiving at least one subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one sub-period.

Further, if a plurality of sub-frame signals in the same sub-period are received, each sub-frame signal is combined. The merging method may adopt various existing merging methods, and the embodiment of the present invention is not limited thereto. For example, the combining method may be equal ratio combining, saturation adding, etc.

Step S320, obtaining a first bit sequence corresponding to the sub-frame signal under the number of candidate antenna ports and the frame header index of the candidate sub-period.

In this embodiment, acquiring soft bit LLRs of a received subframe signal, as specifically shown in fig. 10, includes the following steps:

and S321, extracting the sampled NPBCH baseband data, and performing Fourier transform to obtain frequency domain data.

In this embodiment, sampling is performed at a predetermined frequency, a cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB-NB data and related pilot data in a time domain are obtained. And performing Fourier transform to generate frequency domain data of the subframe.

Step S322, performs channel estimation through NRS, and recovers the transmitting-end signal.

In this embodiment, the number of antenna ports is subjected to blind detection, where the number of antenna ports is 1, the corresponding port number p is 2000, the number of antenna ports is 2, the corresponding port numbers p is 2000 and p is 2001, a NRS (Narrow-band reference signal) mapping position corresponding to the antenna port number is calculated, an NRS signal is extracted, and a locally generated NRS sequence and an NRS signal in received data are used for channel estimation; and performing minimum mean square error estimation, and recovering the signal of the transmitting end by using the obtained estimation matrix.

And step S323, resource demapping is carried out.

In this embodiment, the resource lattices occupied by the Reference signals LTE-CRS Cell-Specific Reference Signal) and NRS are removed, and the first three OFDM (Orthogonal Frequency Division Multiplexing) symbols and the resource lattices occupied by the Reference signals are removed, where when the position of the Reference Signal is calculated, assuming that the antenna port p of CRS is present at all of 0-3, and assuming that the antenna port p of NB-IoT is present at all of 2000 and 2001, complex-valued symbols are sequentially extracted from the 4 th symbol in a predetermined order.

Further, the MIB-NB information is transmitted on NPBCH channel with a transmission period of 8 sub-periods, which is 64 frames. Therefore, it is necessary to perform blind detection on which sub-period of the frame is located in the NPBCH period, so that the value of the frame header index X of the sub-period is 1 to 8 in sequence, and then the value is divided by the coefficient θ f (i) corresponding to the 8 frame header indexes of 10ms in the assumed sub-period, thereby obtaining 100 complex-valued symbols.

Where θ f (i) is a random phase offset added by the transmitting device before RE mapping. Specifically, before performing RE mapping, the sending device performs random phase offset processing on all 100 symbols participating in RE mapping in subframe 0 corresponding to 8 frame header indexes of 10ms in each sub-period, and more specifically, multiplies the symbols by a random phase offset θ f (i).

Wherein, the calculation formula of θ f (i) is as follows:

where cf (2i) and cf (2i +1) are random sequences, and θ f (i) is a random phase offset.

That is, when cf (2i) is 0 and cf (2i +1) is 0, θ f (i) is 1;

θ f (i) is-1 when cf (2i) is 0 and cf (2i +1) is 1;

when cf (2i) is 1 and cf (2i +1) is 0, θ f (i) is j;

when cf (2i) is 1 and cf (2i +1) is 1, θ f (i) is — j.

Step S324, de-layer mapping and pre-coding.

In the present embodiment, NPBCH uses 2 antenna ports at the maximum. When 1 antenna port is adopted, the antenna port number p is 2000, which can be regarded as direct signal transmission. When 2 antenna ports are used, the transmission diversity scheme is used using antenna port numbers p 2000 and p 2001.

Step S325, QPSK modulation is released.

In the present embodiment, every two complex-valued symbols are adjusted to a pair of bit data. Thus, 200bit data can be obtained.

Therefore, 200bit data of the sub-frame signal under the candidate antenna port number and the candidate sub-period frame header index can be obtained through the steps S321-S325.

Further, there are two candidate antenna ports, and 8 candidate sub-period frame header indexes, so that 16 200-bit data are obtained.

And step S326, descrambling.

In this embodiment, for each 200-bit data obtained as described above, the receiving device generates a 1600-bit (8 × 200-bit) random sequence, and selects the 200 th bit from the subframe signal assumed in step S323 to be located in the second sub-period of the NPBCH period for descrambling.

In this embodiment, when performing scrambling, the sending device may use a random sequence, where each bit of data sent corresponds to one data in the random sequence, and each sub-period corresponds to one scrambling sequence, so that the sending device may descramble the received data according to the random sequence when performing scrambling to recover the data before scrambling.

Further, for the mapping of the candidate sub-period frame header index X ═ i (i ═ 1, 2, 3, 4, 5, 6, 7, 8), descrambling is performed according to the random sequence of the ith sub-period to obtain the corresponding first bit sequence.

Specifically, the descrambling formula is as follows:

y＝LLR*(1-2c)

wherein, LLR is a bit sequence obtained by demodulation, c is a random sequence, and y is a descrambled sequence.

As can be seen from the above formula, when c is 0, y is LLR; when c is 1, y is-LLR.

That is, if the random sequence is 0, the bit sequence obtained by demodulation is not changed; if the scrambling code sequence is 1, the demodulated bit sequence is transformed 0/1.

Therefore, the corresponding first bit sequence under the candidate antenna port number and the candidate sub-period frame header index can be obtained.

Step S330, determining a start position (hereinafter referred to as start position k0) of the first bit sequence in the virtual circular buffer according to the candidate sub-period frame header index.

In this embodiment, according to the rate matching process of the transmitting device, the starting position k0 of the 1 st, 4 th and 7 th 200bit data in the virtual circular buffer is 1, the starting position k0 of the 2 nd, 5 th and 8 th 200bit data in the virtual circular buffer is 65, and the starting position k0 of the 3 rd and 6 th 200bit data in the virtual circular buffer is 129. Thus, the start position of the first bit sequence in the virtual circular buffer can be determined according to the candidate sub-period frame header index X.

Further, the relation between the candidate sub-period frame header index X and the start position k0 of the first bit sequence in the virtual circular buffer is shown in fig. 11. Determining the starting position of the first bit sequence in the virtual circular buffer according to the candidate sub-period frame header index comprises:

and responding to the candidate sub-period frame header index being 1 or 4 or 7, wherein the starting position is 1.

In response to the candidate sub-period frame header index being 2, 5 or 8, the start position is 65.

And step S340, performing rate de-matching on the first bit sequence according to the starting position to obtain a second bit sequence.

In this embodiment, for each 200 bits, rate de-matching is performed according to the determined start position to obtain the second bit sequence. As shown in fig. 12, the method includes the following steps:

step S341, sequentially adding the data in the second bit sequence to a plurality of data bits in the virtual circular buffer according to the starting position.

In this embodiment, the sending device obtains a virtual circular buffer, and sequentially adds the data in the second bit sequence to a plurality of data bits in the virtual circular buffer. Specifically, the step of obtaining the virtual buffer can refer to the step S232, and is not described herein again.

Further, the determined start position is k0, and the obtained second bit sequence (200 bits) is filled from the k0 th data bit of 192 data bits in the virtual circular buffer.

Specifically, the first bit in the second bit sequence is selected, the k0 th (k0 ═ 1, 65, 129) data bit in the virtual circular buffer is selected, whether the data bit is a valid bit is determined, if the data bit is a valid bit, the selected bit is padded to the data bit, if the data bit is not a valid bit, the next data bit in the virtual circular buffer is selected, and the determination is continued. If the currently processed data bit is the last data bit in 192, the first data bit is returned on the next processing. The above steps are repeated until 200 bits of data are added to 192 data bits in total.

Further, for each data bit, if multiple bits of data are received, the multiple bits of data are combined. Thus, 192bit data can be obtained.

And step S342, shunting the data in the virtual circular buffer.

Specifically, taking out 1-64 bits of data of 192 bits generates a 64-bit sequence, which is denoted as v11, v12, v13, … …, and v1m, where m is 64. Taking out 65-128 bits of data generates a 64-bit sequence, which is denoted as v21, v22, v23, … … and v2m, wherein m is 64. The 129-192 bit data is taken out to generate a 64-bit sequence which is marked as v31, v32, v33, … … and v3m, wherein m is 64. Thus, 3 x 64bit data can be obtained.

Step S343, performing sub-block deinterleaving on the shunted data to obtain the second bit sequence.

In this embodiment, a corresponding second bit sequence is obtained according to the obtained 3 × 64bit data by sub-block deinterleaving.

Further, for each 64-bit data obtained as described above, the data is added to the 2 × 32 matrix column by column in order from left to right. The original matrix is obtained by performing the inter-column inverse transformation through the inverse process of the step S1134, the data in the original matrix is read out row by row from the 0 th row and the 0 th column of the matrix, and the first 14 dummy bits are removed, so that 50-bit data can be generated. Thus, for 3 × 64bit data, the second bit sequence obtained by sub-block deinterleaving is 3 × 50 bit.

Further, 16 kinds of 200 bits obtained after descrambling in step S330 are subjected to rate de-matching to obtain 16 3 × 50 bits.

According to the embodiment of the invention, the descrambled data is directly subjected to rate de-matching, the cache for rate de-matching is 16 x 3 x 50bit, and compared with the 16 x 1600bit data cached before rate de-matching in the prior art, the occupied cache is 9/32 in the prior art.

And step S350, decoding the second bit sequence to obtain a corresponding third bit sequence.

In this embodiment, the 16 obtained 3 × 50 bits are respectively decoded to obtain a corresponding third bit sequence.

Furthermore, for each 3 × 50bit data, a decoding algorithm is performed to obtain 50bit data before tail-biting convolutional coding with constraint length of 7 and code rate 1/3, that is, a third bit sequence. The idea of decoding is to find a maximum likelihood decoding based on the received sequence. Initializing a state register, a state transition register and a path register, circulating for each state after the initial state, calculating the Hamming distance between the state and the previous two possible states, comparing and selecting a path with smaller Hamming distance until finding out a path with the maximum probability value, and finally backtracking the path transition to generate decoding data.

And step S360, checking the third bit sequence to obtain a checking result.

In this embodiment, the 16 third bit sequences obtained above are respectively checked to obtain check results.

Further, the 50-bit data of the third bit sequence contains 34-bit MIB-NB data and 16-bit CRC check data, and the 16-bit check bits are scrambled by different scrambling sequences. Firstly, according to the number of the antenna ports assumed before, different scrambling codes are selected, and the CRC check bit is subjected to descrambling operation. Specifically, for 8 cases where the number of assumed antenna ports is 1, scrambling sequences of all 0 s in fig. 3 are selected for descrambling; for 8 cases with the number of assumed antenna ports being 2, the scrambling sequences of all 1 in fig. 3 are selected for descrambling. And then using the descrambled 16-bit CRC data to judge whether the data is decoded correctly.

Step S370, determining the number of antenna ports and the frame header index of the sub-period corresponding to the sub-frame signal according to the checking result.

In this embodiment, the number of candidate antenna ports and the candidate sub-period frame header index corresponding to the third bit sequence with correct verification result are determined as the number of antenna ports and the sub-period frame header index corresponding to the sub-frame signal, where the sub-period frame header index is used to represent the position of the sub-period of the sub-frame signal in the NPBCH period.

Thus, it can be determined that the received subframe signal is the frame header of the 80ms th subframe.

Further, the MIB-NB information (34bits) transmitted by the transmitting device is obtained by checking the correct third bit sequence CRC.

Furthermore, as can be seen from the above steps, in the embodiment of the present invention, rate de-matching is directly performed on the received 200-bit data, and only 16 × 3 × 150-bit data output by rate de-matching needs to be buffered, and the calculated amount is 16 × 200 bits. Compared with the 16 × 1600bit cache required by the prior art, the calculated amount is 16 × 1600bit, the cache required by the embodiment of the invention is 9/32 in the prior art, and the calculated amount is 1/8 in the prior art.

Fig. 13 is a schematic structural diagram of a blind channel detection apparatus according to an embodiment of the present invention. As shown in fig. 13, the blind channel detection apparatus according to the embodiment of the present invention includes: receiving unit 131, first bit sequence acquiring unit 132, start position determining unit 133, de-rate matching unit 134, decoding unit 135, verifying unit 136, and determining unit 137. The receiving unit 131 is configured to receive at least one subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one sub-period. The first bit sequence obtaining unit 132 is configured to obtain a first bit sequence corresponding to the subframe signal under the candidate antenna port number and the candidate subframe header index. The start position determining unit 133 is configured to determine a start position of the first bit sequence according to the candidate sub-period frame header index. The de-rate matching unit 134 is configured to perform de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence. The decoding unit 135 is configured to perform a decoding process on the second bit sequence to obtain a corresponding third bit sequence. The checking unit 136 is configured to check the third bit sequence to obtain a check result. The determining unit 137 is configured to determine, as the number of antenna ports and a sub-cycle frame header index corresponding to the sub-frame signal, the number of candidate antenna ports and the candidate sub-cycle frame header index corresponding to the third bit sequence with the correct checking result, where the sub-cycle frame header index is used to represent a position of a sub-cycle of the sub-frame signal in an NPBCH cycle.

Further, the number of candidate antenna ports includes 1 and 2, and the candidate sub-period frame header indexes include 1, 2, 3, 4, 5, 6, 7, and 8.

Further, the start position determination unit 133 includes:

a first position determining subunit, configured to respond to that the candidate sub-period frame header index is 1, 4, or 7, and the start position is 1;

a second position determining subunit, configured to respond to that the candidate sub-period frame header index is 2, 5, or 8, and the start position is 65; and

and the third position determining subunit is used for responding to the frame header index of the candidate sub-period being 3 or 6, and the starting position is 129.

Further, the de-rate matching unit 134 includes:

a data adding subunit, configured to add data in the second bit sequence to a plurality of data bits in a virtual circular buffer in sequence according to the starting position;

the shunting subunit is used for shunting the data in the virtual circular buffer; and

and the deinterleaving subunit is configured to perform sub-block deinterleaving on the split data to obtain the second bit sequence.

Further, in response to receiving a plurality of subframe signals transmitted by the NPBCH in one subframe period, the apparatus further includes:

and the merging unit is used for merging the received multiple subframe signals.

The method comprises the steps of obtaining a first bit sequence of a subframe signal under the number of candidate antenna ports and the frame head index of a candidate sub-period by receiving the subframe signal sent by a narrow-band physical broadcast channel NPBCH in a sub-period, determining the initial position of the first bit sequence according to the frame head index of the candidate sub-period, performing rate de-matching on the first bit sequence according to the initial position to obtain a second bit sequence, decoding and checking the second bit sequence to obtain a checking result, and determining the number of the candidate antenna ports and the frame head index of the candidate sub-period corresponding to a third bit sequence with correct checking result as the number of the antenna ports and the frame head index of the sub-period corresponding to the subframe signal. Therefore, the cache and calculation amount of the de-rate matching can be reduced, and the blind detection efficiency is improved.

Fig. 14 is a schematic hardware configuration diagram of a communication device according to an embodiment of the present invention. As shown in fig. 14, the communication apparatus includes: memory 141 and processor 142, wherein memory 141 and processor 142 are in communication; illustratively, the memory 141 and the processor 142 communicate via a communication bus 143, the memory 141 being used for storing computer programs, the processor 142 executing the computer programs to implement the methods shown in the above embodiments.

Optionally, the communication device may further comprise a transmitter and/or a receiver.

Alternatively, the Processor may be a Central Processing Unit (CPU), or may be implemented by other general-purpose processors, a PLC (Programmable Logic Controller), an FPGA (Field-Programmable Gate Array), a DSP (Digital Signal Processor), or an ASIC (Application Specific Integrated Circuit). A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.

An embodiment of the present invention provides a storage medium, where the storage medium is used to store a computer program, and the computer program is used to implement the channel blind detection method according to any of the above-mentioned method embodiments.

The embodiment of the present invention provides a chip, where the chip is used to support a receiving device (e.g., a terminal device, a network device, etc.) to implement the functions shown in the embodiment of the present invention, and the chip is specifically used in a chip system, where the chip system may be formed by a chip, and may also include a chip and other discrete devices. When the chip in the receiving device implementing the method includes a processing unit, the chip may further include a communication unit, and the processing unit may be, for example, a processor, and when the chip includes the communication unit, the communication unit may be, for example, an input/output interface, a pin, a circuit, or the like. The processing unit executes all or part of the actions executed by the processing modules in the embodiment of the invention, and the communication unit executes corresponding receiving or sending actions. In another specific embodiment, the processing module of the receiving device in the embodiment of the present invention may be a processing unit of a chip, and the receiving module or the transmitting module of the control device is a communication unit of the chip.

All or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The aforementioned program may be stored in a readable memory. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid state disk, magnetic tape (magnetic tape), floppy disk (floppy disk), optical disk (optical disk), and any combination thereof.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for blind channel detection, the method comprising:

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

2. The method of claim 1, wherein the number of candidate antenna ports comprises 1 and 2, and wherein the candidate sub-period frame header indexes comprise 1, 2, 3, 4, 5, 6, 7, and 8.

3. The method of claim 2, wherein determining the starting position of the first bit sequence according to the candidate sub-period frame header index comprises:

4. The method of claim 1, wherein rate de-matching the first bit sequence to obtain a second bit sequence according to the starting position comprises:

shunting data in the virtual circular buffer; and

5. The method of claim 1, wherein in response to receiving a plurality of subframe signals transmitted by NPBCH in one sub-period, the method further comprises:

and combining the received multiple subframe signals.

6. An apparatus for blind channel detection, the apparatus comprising:

7. A communications apparatus comprising a memory and a processor, the processor executing program instructions in the memory for implementing the method of any one of claims 1-5.

8. A storage medium, characterized in that the storage medium is adapted to store a computer program for implementing the method of any one of claims 1-5.