CN112100023B - Board card information acquisition method and device for heterogeneous acceleration platform - Google Patents

Abstract

The invention provides a method and equipment for acquiring board card information of a heterogeneous acceleration platform, wherein the method comprises the following steps: acquiring information data of the board card, and sending the information data to the FPGA at intervals of threshold time; responding to the FPGA receiving the information data, and storing the information data into a corresponding RAM; periodically acquiring information data in the RAM through a PCIe Bar space, and verifying and analyzing the information data; and displaying the analyzed information data through a display device. By using the scheme of the invention, the limitation of the server BMC can be eliminated, and the board card state information can be monitored in real time, so that the board card state information can be acquired in real time in a system without a matched BMC, and the operation and maintenance work can be conveniently expanded.

Description

Method and device for obtaining board information of a heterogeneous acceleration platform

technical field

This field relates to the computer field, and more specifically relates to a method and a device for obtaining board information of a heterogeneous acceleration platform.

Background technique

With the rise of big data, cloud computing, and artificial intelligence technologies, people's requirements for data computing speed are getting higher and higher. Based on this consideration, we propose a CPU+FPGA+MCU (micro control unit) heterogeneous acceleration platform suitable for servers. The basic principle is to put part of the data in the FPGA and use a specific algorithm for fast processing, and then feed back the processing results to the CPU (Central Processing Unit), which reduces the pressure on the CPU, improves the server's work efficiency, and reduces the running time. As shown in Figure 1, the left part of Figure 1 is a traditional server that does not use FPGA acceleration, and it takes a long time to process data B. The right part of Figure 1 is accelerated by FPGA (field programmable gate array) After the platform, the data B is processed in the FPGA using a specific algorithm, and its processing speed is significantly faster than that of the CPU, so that the processing time of B is greatly reduced. It can be seen from this that in the future, FPGA-led heterogeneous acceleration platforms have broad application prospects in big data, cloud computing, and artificial intelligence.

Figure 2 shows the overall framework of the heterogeneous acceleration platform, which mainly includes the server and the FPGA heterogeneous acceleration card connected to it through PCIe. The heterogeneous accelerator card includes the main chip (FPGA chip), monitoring and management chip (MCU chip), DDR, FLASH, EEPROM, monitoring Sensor and some other peripheral circuits, where the EEPROM is used to store the basic information of the board, and the peripheral Sensor is used to The board status is monitored, including board temperature, power consumption and other information.

In order to monitor the status information of the board in real time, the current general practice is to use the FPGA accelerator card as a part of the monitoring and management of the server BMC. The server BMC can obtain the status information of the board through the ipmitool tool. Although this method can achieve the purpose of real-time monitoring of the status of the board, its fatal flaw lies in the need for a supporting BMC system. If the BMC in the user server is not a BMC provided by the board manufacturer, it is still impossible to obtain board information through this method.

Contents of the invention

In view of this, the purpose of the embodiment of the present invention is to propose a method and device for obtaining board information of a heterogeneous acceleration platform. By using the method of the present invention, it is possible to get rid of the limitation of the server BMC and monitor the status information of the board in real time. , so that the board status information can be obtained in real time even in a system without a supporting BMC, which facilitates the development of operation and maintenance work.

Based on the above purpose, an aspect of the embodiments of the present invention provides a method for obtaining board information of a heterogeneous acceleration platform, including the following steps:

Obtain the information data of the board, and send the information data to the FPGA every threshold time interval;

In response to the FPGA receiving the information data, storing the information data in the corresponding RAM;

Obtain the information data in RAM regularly through the PCIe Bar space, and check and analyze the information data;

The analyzed information data is displayed by a display device.

According to an embodiment of the present invention, obtaining the information data of the board, and sending the information data to the FPGA every interval threshold time also includes:

Use the MCU to read out the information data of the board stored in the storage device, and store the information data in the cache;

The MCU sends the information data in the cache to the FPGA via the SMbus bus on the PCIe interface every threshold time interval.

According to an embodiment of the present invention, also include:

Set the update status flag before sending the information data to the FPGA every threshold time interval;

Reset the update status flag after sending the message data to the FPGA.

According to an embodiment of the present invention, also include:

Before obtaining the information data in the RAM via the PCIe Bar space, judge the status of the update status flag;

In response to the update status flag being set, stop acquiring and prompt the user that the board information is being updated;

In response to the update state being identified as the reset state, continue to obtain information data in the RAM.

According to an embodiment of the present invention, the information data includes FRU (Field Replaceable Unit) information of the board and status information of the board.

According to an embodiment of the present invention, in response to the FPGA receiving the information data, storing the information data into the corresponding RAM includes:

In response to the FPGA receiving the information data, storing the information data into a corresponding on-chip RAM;

Mount the RAM to the PCIe Bar space via the FPGA so that the server can access the RAM by accessing the PCIe Bar space.

Another aspect of the embodiments of the present invention also provides a device for obtaining board information of a heterogeneous acceleration platform, and the device includes:

The acquiring module is configured to acquire the information data of the board, and send the information data to the FPGA every threshold time interval;

A storage module, the storage module is configured to store the information data in the corresponding RAM in response to the FPGA receiving the information data;

An analysis module, the analysis module is configured to regularly obtain the information data in the RAM via the PCIe Bar space, and check and analyze the information data;

A display module, the display module is configured to display the parsed information data through a display device.

According to an embodiment of the present invention, the acquisition module is also configured to:

Use the MCU to read out the information data of the board stored in the storage device, and store the information data in the cache;

The MCU sends the information data in the cache to the FPGA via the SMbus bus on the PCIe interface every threshold time interval.

Another aspect of the embodiments of the present invention also provides a computer device, including:

at least one processor; and

A memory, the memory stores a computer program that can run on the processor, and it is characterized in that, when the processor executes the program, any one of the methods above is executed.

Another aspect of the embodiments of the present invention further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any one of the above-mentioned methods is executed.

The present invention has the following beneficial technical effects: the method for board information acquisition provided by the embodiment of the present invention, by obtaining the information data of the board, and sending the information data to the FPGA every interval threshold time; in response to the FPGA receiving the information data, Store the information data in the corresponding RAM; regularly obtain the information data in the RAM through the PCIe Bar space, and verify and analyze the information data; the technical solution of displaying the analyzed information data through the display device can get rid of the server Due to the limitation of BMC, the real-time monitoring of the status information of the board makes it possible to obtain the status information of the board in real time even in a system without a supporting BMC, which facilitates the development of operation and maintenance work.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and those skilled in the art can obtain other embodiments according to these drawings without any creative effort.

Fig. 1 is the heterogeneous platform acceleration model of prior art;

Fig. 2 is the heterogeneous acceleration platform of prior art;

Fig. 3 is a schematic flowchart of a method for obtaining board information according to an embodiment of the present invention;

Fig. 4 is a schematic diagram of a device for obtaining board information according to an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Based on the above purpose, the first aspect of the embodiments of the present invention proposes an embodiment of a method for improving the signal-to-noise ratio. Fig. 3 shows a schematic flowchart of the method.

As shown in Figure 3, the method may include the following steps:

S1 obtains the information data of the board, and sends the information data to the FPGA every threshold time, and initializes the hardware after booting, including the hardware information of the board will be stored in the EEPROM, and can use CPU+FPGA+MCU heterogeneous acceleration The MCU in the platform reads the board information stored in the EEPROM. The board information includes FRU information, and the FRU information includes serial number information and product number information. The MCU also polls the status information of the board regularly. The status information includes Information such as temperature, power consumption, current, etc. After the MCU obtains the above information, it first stores the information in the cache, and then the MCU regularly collects the board information data (including FRU information and board status information) through the SMbus bus on the PCIe interface. send to FPGA;

S2 stores the information data in the corresponding RAM in response to the FPGA receiving the information data. After receiving the information data, the FPGA stores the data in the corresponding on-chip RAM according to the address, and the FPGA mounts the RAM to the PCIe Bar space for Make the host (host) side of the server accessible by accessing the PCIe Bar space;

S3 regularly obtains the information data in RAM through the PCIe Bar space, and checks and analyzes the information data. The Host terminal interacts with the FPGA through reading and writing in the PCIe Bar space, and obtains the data in the corresponding address in the RAM through the PCIe Bar space. After the terminal obtains the data, it first verifies the data, verifies whether the obtained information is correct, and then parses the data through the protocol after the verification is passed;

S4 displays the analyzed information data through a display device, and displays the analyzed board information data through a human-computer interaction interface (such as a display, etc.).

The technical solution of the present invention is mainly applied in the CPU+FPGA+MCU heterogeneous acceleration platform, which can effectively avoid the shackles of the BMC, and only the host program of the server can obtain the board information, and the host program is only responsible for obtaining the board The information will not affect other functions of the server, and the user can execute the Host program at any time to obtain the status information of the board in real time.

Through the technical solution of the present invention, it is possible to get rid of the limitation of the server BMC and monitor the status information of the board card in real time, so that the status information of the board card can also be obtained in real time in a system without a supporting BMC, which facilitates the development of operation and maintenance work.

In a preferred embodiment of the present invention, obtaining the information data of the board, and sending the information data to the FPGA every interval threshold time also includes:

Use the MCU to read out the information data of the board stored in the storage device, and store the information data in the cache;

The MCU sends the information data in the cache to the FPGA via the SMbus bus on the PCIe interface every threshold time interval. When the system is powered on, the MCU obtains the FRU information of the board and regularly obtains the status information of the board, and stores the two parts of information in two buffers for the convenience of program writing and data copying on the MCU side. A cache can increase the response speed of data information when writing and reading. The board status information in the cache is regularly updated, and the MCU regularly sends the board information data to the FPGA through the SMbus bus on the PCIe interface.

In a preferred embodiment of the present invention, also include:

Set the update status flag before sending the information data to the FPGA every threshold time interval;

After the information data is sent to the FPGA, the update status flag will be reset. The status flag bit can theoretically be placed on any unused address in the BAR space. In order to facilitate later function expansion, the flag bit is placed at the end of the Bar2 space in this case. on one byte. In order to avoid data conflicts, set the update status flag. When the flag is in the set state, it means that the information data in the RAM is being updated. At this time, the server cannot read the information data stored in the RAM and prompt the user. The flag bit When the state is reset, the server side can read the information data stored in the RAM.

In a preferred embodiment of the present invention, also include:

Before obtaining the information data in the RAM via the PCIe Bar space, judge the status of the update status flag;

In response to the update status flag being set, stop acquiring and prompt the user that the board information is being updated;

In response to the update state being identified as the reset state, continue to obtain information data in the RAM.

In a preferred embodiment of the present invention, in response to the FPGA receiving the information data, storing the information data in the corresponding RAM includes:

In response to the FPGA receiving the information data, the information data is stored in the corresponding on-chip RAM. After the FPGA receives the information data, the data is first verified. If the verification is passed, the data in the previous RAM will be overwritten. If the verification is not passed The data that has not passed the verification will be deleted directly;

Mount the RAM to the PCIe Bar space via the FPGA so that the server can access the RAM by accessing the PCIe Bar space.

Through the technical solution of the present invention, it is possible to get rid of the limitation of the server BMC and monitor the status information of the board card in real time, so that the status information of the board card can also be obtained in real time in a system without a supporting BMC, which facilitates the development of operation and maintenance work.

It should be noted that those skilled in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented through computer programs to instruct relevant hardware to complete, and the above programs can be stored in computer-readable storage media. When the program is executed, it may include the processes of the embodiments of the above-mentioned methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random Access Memory, RAM). The foregoing computer program embodiments can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

In addition, the method disclosed according to the embodiment of the present invention can also be implemented as a computer program executed by a CPU, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the CPU, the above functions defined in the methods disclosed in the embodiments of the present invention are executed.

Based on the above purpose, the second aspect of the embodiment of the present invention proposes a device for obtaining board information of a heterogeneous acceleration platform. As shown in FIG. 4 , the device 200 includes:

Acquisition module 201, the acquisition module 201 is configured to obtain the information data of the board, and send the information data to the FPGA every interval threshold time;

A storage module 202, the storage module 202 is configured to store the information data into a corresponding RAM in response to the FPGA receiving the information data;

An analysis module 203, the analysis module 203 is configured to regularly obtain the information data in the RAM via the PCIe Bar space, and check and analyze the information data;

A display module 204, the display module 204 is configured to display the analyzed information data through a display device.

In a preferred embodiment of the present invention, the acquisition module is also configured as:

Use the MCU to read out the information data of the board stored in the storage device, and store the information data in the cache;

The MCU sends the information data in the cache to the FPGA via the SMbus bus on the PCIe interface every threshold time interval.

In a preferred embodiment of the present invention, it also includes an identification module, and the identification module is configured as:

Set the update status flag before sending the information data to the FPGA every threshold time interval;

Reset the update status flag after sending the message data to the FPGA.

In a preferred embodiment of the present invention, a judging module is also included, and the judging module is configured as:

Before obtaining the information data in the RAM via the PCIe Bar space, judge the status of the update status flag;

In response to the update status flag being set, stop acquiring and prompt the user that the board information is being updated;

In response to the update state being identified as the reset state, continue to obtain information data in the RAM.

Based on the above purpose, a third aspect of the embodiments of the present invention proposes a computer device, including:

at least one processor; and

A memory, the memory stores a computer program that can run on the processor, and it is characterized in that, when the processor executes the program, any one of the methods above is executed.

Based on the above purpose, the fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, any one of the above-mentioned methods is performed.

It should be pointed out that the embodiments of the above-mentioned system use the embodiments of the above-mentioned method to specifically illustrate the working process of each module, and those skilled in the art can easily think of applying these modules to other embodiments of the above-mentioned method.

Those of skill would also appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality. Whether such functionality is implemented as software or as hardware depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope disclosed in the embodiments of the present invention.

The above-described embodiments, particularly any "preferred" embodiments, are possible examples of implementations, and were merely presented for a clear understanding of the principles of the invention. Many changes and modifications can be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All modifications are intended to be included within the scope of this disclosure and protected by the appended claims.

Claims (7)

1. A method for acquiring board card information of a heterogeneous acceleration platform is characterized by comprising the following steps:

reading out information data of a board card stored in a storage device by using an MCU (microprogrammed control unit), and storing the information data into a cache;

sending the information data in the cache to an FPGA (field programmable gate array) through an SMbus on a PCIe (peripheral component interconnect express) interface by using the MCU at intervals of threshold time;

responding to the FPGA receiving the information data, storing the information data into a RAM on a corresponding chip, and mounting the RAM onto a PCIe Bar space through the FPGA so that a server side accesses the RAM by accessing the PCIe Bar space;

the information data in the RAM is regularly acquired through a PCIe Bar space, and the information data is checked and analyzed;

and displaying the analyzed information data through a display device.

2. The method of claim 1, further comprising:

setting the update state identifier before sending the information data to the FPGA at each threshold interval time;

resetting the update status flag after sending the information data to the FPGA.

3. The method of claim 2, further comprising:

judging the state of the update state identifier before acquiring the information data in the RAM through a PCIe Bar space;

in response to the update state identification being in a set state, stopping acquiring and prompting that the user board card information is being updated;

and responding to the updating state mark as a reset state, and continuously acquiring the information data in the RAM.

4. The method of claim 1, wherein the information data includes FRU information for the board and status information for the board.

5. The utility model provides an equipment that heterogeneous integrated circuit board information of accelerating platform obtained which characterized in that, equipment includes:

the acquisition module is configured to read out information data of the board card stored in the storage device by using the MCU and store the information data into a cache;

the obtaining module is further configured to send the information data in the cache to the FPGA via an SMbus on a PCIe interface at every threshold interval time by using the MCU;

the storage module is configured to respond to the information data received by the FPGA, store the information data into the RAM on the corresponding chip, and mount the RAM onto a PCIe Bar space through the FPGA so that a server side can access the RAM by accessing the PCIe Bar space;

the analysis module is configured to periodically acquire the information data in the RAM via a PCIe Bar space and check and analyze the information data;

and the display module is configured to display the analyzed information data through a display device.

6. A computer device, comprising:

at least one processor; and

memory storing a computer program operable on the processor, wherein the processor, when executing the program, performs the method of any of claims 1-4.

7. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 1 to 4.

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