CN112073354B - High Speed Mobile Wireless Communication System Based on FPGA - Google Patents

Abstract

The invention discloses a high-speed mobile wireless communication system based on FPGA, a base station is arranged at intervals of preset distance along an optical fiber, a 2.5G synchronous ring network is formed between the base stations, and the base stations are connected with a monitoring center, and broadband communication is carried out between a mobile terminal and the base stations; the timing and carrier synchronization is realized between the mobile terminal and the base station, the uplink rate and the downlink rate adopt an asymmetric mode with configurable uplink-downlink rate ratio, and the communication rate is automatically configured according to the number of the mobile terminals which are simultaneously accessed into the base station; the base station coordinates with the adjacent base station to determine the communication modes of the downlink channel and the uplink channel, so that the mobile terminal can be smoothly switched between different base stations; both the base station and the mobile terminal include modems. By the technical scheme of the invention, the asymmetric rates of the upper and lower channels are realized, and the base station can automatically adjust the communication rate of each terminal according to the number of the terminals which can be accessed, so that the problem of seamless switching of the mobile terminal in the high-speed mobile communication process is solved.

Description

High-speed mobile wireless communication system based on FPGA

Technical Field

The present invention relates to the technical field of communication systems, and in particular to a high-speed mobile wireless communication system based on FPGA.

Background Art

In recent years, with the rapid development of science and technology and economy, my country's transportation construction has developed rapidly. Therefore, more and more people choose high-speed rail or car as a means of travel, resulting in an increasing frequency of mobile terminals in high-speed moving scenarios. Since the mobile terminal will cause Doppler frequency shift when it is in a high-speed moving state, it will increase the difficulty of synchronous reception of the OFDM (Orthogonal Frequency Division Multiplexing) system, and the quality of the communication link cannot be guaranteed.

At present, some scholars focus on using the redundant information of the cyclic prefix to achieve synchronization. Considering the defects of the cyclic prefix, a new timing measurement function and detection function are proposed by sampling in the interval without inter-symbol interference. In order to improve the anti-interference ability under low signal-to-noise ratio, a blind estimation algorithm of time offset based on distance measurement is proposed in combination with the truncated CP technology. However, this type of algorithm is relatively complex and is not suitable for mobile terminals with real-time requirements. Therefore, some scholars combine pilot or preamble symbols to achieve synchronization of OFDM systems, and propose a preamble symbol composed of ZC (Zadoff-Chu) sequence. By constructing a training sequence with a conjugate repetitive relationship structure, the synchronization result is guaranteed to be unaffected by frequency. In order to avoid problems such as timing ambiguity, a weighted (Constant Amplitude Zero Auto-Correlation, CAZAC) training sequence is proposed, and on this basis, a synchronization algorithm for joint estimation of symbol timing and carrier frequency offset is proposed. Through fewer auxiliary sequences, an autocorrelation estimation Auto Correlation Estimation, ACE) time-frequency synchronization algorithm is proposed, and the frequency offset estimation is completed by combining the idea of autocorrelation function and weighted average. To determine the symbol synchronization point, the Schmidl&Cox algorithm is used to determine the symbol synchronization range, and then the Park algorithm is used to determine the symbol synchronization point. Although the synchronization algorithm combined with the pilot or preamble symbol can achieve the synchronization of the OFDM system, it is mainly verified by the simulation system, and has not been actually tested with specific hardware equipment.

Summary of the invention

In view of the above problems, the present invention provides a high-speed mobile wireless communication system based on FPGA. By using FPGA and OFDM technology, on the basis of PN synchronization, a downlink channel, an uplink channel and a modem system are designed for the communication process between a mobile terminal and a base station, so as to realize asymmetric rates of the uplink and downlink channels, and the base station can automatically adjust the communication rate of each terminal according to the number of terminals that can be accessed. In both cases of moving toward the base station and moving away from the base station, a high-gain omnidirectional antenna has more advantages than a low-gain omnidirectional antenna, and a single-tone signal can more accurately reflect the fading depth than a broadband signal.

To achieve the above-mentioned purpose, the present invention provides a high-speed mobile wireless communication system based on FPGA, comprising: a base station, a mobile terminal, a monitoring center and an optical fiber ring network; a base station is arranged at a preset distance along the optical fiber, and the base stations form a 2.5G synchronous ring network through the optical fiber and are connected to the monitoring center, and broadband communication is performed between the mobile terminal and the base station; timing synchronization and carrier synchronization are achieved between the mobile terminal and the base station, and the uplink rate and downlink rate between the mobile terminal and the base station adopt an asymmetric mode with a configurable uplink and downlink rate ratio, and the communication rate of each mobile terminal is automatically configured according to the number of mobile terminals simultaneously accessing the base station; the base station coordinates with adjacent base stations to determine the communication mode of the downlink channel and the uplink channel between the base station and the mobile terminal, so as to achieve smooth switching of the mobile terminal between different base stations; the base station and the mobile terminal both include a modem, the modem of the base station is connected to an external device through an IP switch, and the modem of the mobile terminal is connected to an external device through a WiFi module.

In the above technical scheme, preferably, the base stations are sorted from near to far according to the distance between the base stations and the monitoring center, and the base stations with odd serial numbers are defined as odd base stations and the base stations with even serial numbers are defined as even base stations; the data format of the downlink channel includes a synchronization header, a control bit 0, a control bit 1, a class 1 channel and a class 2 channel, and the timing synchronization and carrier synchronization between the mobile terminal and the base station are achieved through the synchronization header. The even base station uses the control bit 0 time slot to send control information and the control bit 1 time slot is idle, and the odd base station uses the control bit 1 time slot to send control information and the control bit 0 time slot is idle; all time slots of the class 1 channel can be used by the base station, the even base station can only use the even-numbered time slots of the class 2 channel, and the odd-numbered time slots are vacant, and the odd base station can only use the odd-numbered time slots of the class 2 channel, and the even-numbered time slots are vacant.

In the above technical solution, preferably, the monitoring center sends a reset command to all base stations, the monitoring center and the base stations both start counting with a standard clock, the monitoring center sends a message to the base station when counting to a preset time, and when the base station receives the message, it records the count of its own counter at this time as an uplink count, and the base station sends a message to the monitoring center when counting to a preset time, and when the monitoring center receives the message, it records the count of its own counter at this time as a downlink count, and sends the downlink count to the corresponding base station, and the base station adjusts the base of its own counter according to the difference between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, thereby realizing time calibration of the current base station.

In the above technical scheme, preferably, the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through the synchronization head of the downlink channel. After the synchronization is completed, the mobile terminal controls the instructions of the uplink channel through the clock counter synchronized with the base station to perform corresponding actions at the corresponding time; according to the different distances between the mobile terminal and the base station, when the mobile terminal is in a Class 1 area, it sends data to the base station through a Class 1 channel in the uplink channel that does not need to avoid the time slots of mobile terminals connected to adjacent base stations; when the mobile terminal is in a Class 2 area, it sends data to the base station through a Class 2 channel in the uplink channel that needs to avoid the time slots of mobile terminals connected to adjacent base stations; the uplink channel starts with a network access application channel. When a base station and its adjacent base stations no longer accept new network access applications from mobile terminals, the time slots occupied by the network access application channel can be removed from the uplink channel.

In the above technical solution, preferably, the modem includes an ARM CPU, an address attribute controller, a transmission time slot controller, a reception time slot controller, a control register, a memory, a digital modulator, a digital demodulator and a radio frequency module; the ARM CPU, the transmission time slot controller, the reception time slot controller and the control register are connected to the memory through a data bus, the address attribute controller controls the ownership of the memory, the ARM CPU stores the received data in the memory, the transmission time slot controller reads the data from the memory at a specific time and sends the data to the digital modulator, the digital modulator performs OFDM modulation on the received data and sends the modulated data to the radio frequency module; the reception time slot controller sends the data received by the radio frequency module to the digital demodulator, performs OFDM demodulation through the digital demodulator, and stores the demodulated data in the memory, the ARM CPU reads the data from the memory and sends the data to the IP switch.

In the above technical solution, preferably, the digital modulator includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, a FIR HB Filter module, a Farrow Filter module, a DUC module and a Gain module;

When the transmit time slot controller executes the TxPN instruction, the PN Generator module generates synchronization header information, otherwise it is idle at other times, the Mapper module loads the Tx_Data data onto the modulated signal according to the requirements of Tx_Mod, the Carrier Control module determines whether to insert the pilot subcarrier according to whether the SUB_CAR value in the transmit instruction is the same as the setting of the valid subcarrier number register, the Differential Encoder module is a differential encoder for the differential OFDM system, the iFFT module is used for inverse fast Fourier transform, and is responsible for converting the frequency domain signal to the time domain to form an OFDM symbol, the CP module is responsible for adding the cyclic prefix of the OFDM symbol, when the instruction is the TxPN instruction, the MUX module selects the data of the synchronization header circuit to be transmitted to the subsequent module, and when the instruction is the OFDM or PILOT instruction, the data of the OFDM circuit is selected, the FIR HB Filter module is used to increase the data sampling rate from 76MHz to 152MHz, the Farrow The Filter module is used to interpolate and upsample the 152MHz clock sampling signal to a 156.25MHz sampling rate. The DUC module is used to up-convert the baseband signal to an intermediate frequency signal. Finally, the Gain module adjusts the gain of the transmission signal.

In the above technical solution, preferably, the digital demodulator includes an AGC module, a DCC module, a FarrowFilter module, a FIR HB Filter module, a DeMUX1 module, a PN Correlate module, a PLL module, a Correlator module, an FFT module, a DeMUX2 module, a Differential Decoder module, a Channel & Carrier Estimation module, an Equalizer module, a PHASOR module, a DeMapper module, a Post Proc module and a Pilot Drop module;

The AGC module is a pulse width modulation generation circuit, which is used to provide automatic gain control for the RF receiving amplifier and adjust the received signal to a preset amplitude. The DCC module is used to move the received signal from the intermediate frequency to the baseband. The FarrowFilter module and the FIR HB Filter module are used to interpolate and downsample the 156.25MHz clock sampling signal to a 152MHz sampling rate and reduce the data sampling rate from 152MHz to 76MHz, respectively. The DeMUX1 module selects different processing circuits according to the received instructions. If the instructions are RxPN Start and RxPN Stop, the received data is passed to the PN processing circuit. When the instruction is OFDM or PILOT, the OFDM processing circuit is selected. In the PN processing circuit, the PN Correlate module is mainly responsible for synchronization header search. When the receiving time slot controller executes RxPN Start or RxPN Stop instruction, the module starts or ends the synchronization header search; the PLL module provides the system with a close working clock, and in the later stage the PNCorrelate module synchronizes the working clock with the working clock of the base station, and the Correlator module in the OFDM circuit performs correlation operation on the first pilot symbol of the differential OFDM, thereby eliminating the ambiguity in the OFDM signal; the FFT module converts the OFDM signal in the time domain to the frequency domain, the DeMUX2 module and the DifferentialDecoder module respectively complete the difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes PILOT, the Channel&Carrier Estimation module is selected to complete the channel and carrier frequency estimation, but when the module executes the OFDM instruction, the Equalizer module is selected to complete the channel equalization; considering that there is a certain carrier frequency deviation in the signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete the phase rotation, judge the received data to the constellation point of the modulated signal and extract the frequency deviation information according to the phase difference of the data before and after the judgment, and finally the Pilot The Drop module determines the insertion position of the pilot subcarrier based on whether the SUB_CAR value in the received instruction is the same as the setting of the valid subcarrier number register.

In the above technical solution, preferably, the specific process of performing clock synchronization and carrier frequency synchronization through the synchronization head includes a search process and a tracking process; in the search process, the period of the frame length counter is set by software setting before the position of the synchronization head is locked, and when the amplitude of the correlation peak is greater than the preset threshold, the position of the maximum correlation peak and the amplitude of the corresponding correlation peak are recorded, and an interrupt request is issued to the ARM CPU. After receiving the interrupt request, the ARM CPU sets the clearing point of the frame length counter to the sum of the time intervals between the maximum correlation peak and the end point of the synchronization head and the end point of the frame; when the frame length counter reaches the clearing point, an interrupt request is issued to the ARM CPU. After receiving the interrupt request, the ARM CPU sets the period of the frame length counter so that the clearing point of the frame length counter is located at the end point of the frame;

The tracking process includes timing tracking and carrier frequency tracking. In the timing tracking process, the main correlation peak and the correlation peaks on both sides are obtained through the PN correlator, and the timing error of the system clock is calculated, and the timing error is corrected by adjusting the NCO; in the carrier frequency tracking process, the carrier frequency offset information is detected by the PN correlator, the offset is calculated based on the carrier frequency offset information, and the correction amount is set back to the hardware circuit to correct the carrier frequency deviation.

Compared with the prior art, the beneficial effects of the present invention are as follows: by utilizing FPGA and OFDM technology, on the basis of PN synchronization, a downlink channel, an uplink channel and a modem system are designed for the communication process between a mobile terminal and a base station, and asymmetric rates of the uplink and downlink channels are realized, and the base station can automatically adjust the communication rate of each terminal according to the number of terminals that can be accessed. In both the case of moving toward the base station and moving away from the base station, a high-gain omnidirectional antenna has more advantages than a low-gain omnidirectional antenna, and a single-tone signal can more accurately reflect the fading depth than a broadband signal, thereby solving the problem of seamless switching of mobile terminals during high-speed mobile communications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the overall structure of a high-speed mobile wireless communication system based on FPGA disclosed in an embodiment of the present invention;

FIG2 is a schematic diagram of a data format of a downlink channel disclosed in an embodiment of the present invention;

FIG3 is a schematic diagram of a data format of an uplink channel disclosed in an embodiment of the present invention;

FIG4 is a schematic diagram of a frame format of an uplink channel disclosed in an embodiment of the present invention;

FIG5 is a schematic diagram of a system design of a modem disclosed in an embodiment of the present invention;

FIG6 is a schematic diagram of the basic structure of a digital modulator disclosed in an embodiment of the present invention;

FIG7 is a schematic diagram of the basic structure of a digital demodulator disclosed in an embodiment of the present invention;

FIG8 is a schematic diagram of a synchronization head disclosed in an embodiment of the present invention;

FIG9 is a schematic diagram of a system correlation peak disclosed in an embodiment of the present invention;

FIG10 is a schematic diagram of the locations of an outfield base station and a mobile terminal test point disclosed in an embodiment of the present invention;

FIG11 is a schematic diagram of RSSI values on the mobile terminal side moving toward a base station disclosed in an embodiment of the present invention;

FIG12 is a schematic diagram of RSSI values at a mobile terminal side moving away from a base station according to an embodiment of the present invention;

FIG13 is a schematic diagram of RSSI values at a base station side moving toward a base station disclosed in an embodiment of the present invention;

FIG. 14 is a schematic diagram of RSSI values at a base station side moving away from the base station according to an embodiment of the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

The present invention is further described in detail below in conjunction with the accompanying drawings:

As shown in FIG1 , a high-speed mobile wireless communication system based on FPGA provided by the present invention includes: a base station, a mobile terminal, a monitoring center and an optical fiber ring network; a base station is set at a preset distance along the optical fiber, and the base stations form a 2.5G synchronous ring network through the optical fiber and are connected to the monitoring center, and broadband communication is performed between the mobile terminal and the base station; timing synchronization and carrier synchronization are achieved between the mobile terminal and the base station, and the uplink rate and downlink rate between the mobile terminal and the base station adopt an asymmetric mode with a configurable uplink and downlink rate ratio, and the communication rate of each mobile terminal is automatically configured according to the number of mobile terminals simultaneously accessing the base station; the base station coordinates with the adjacent base stations to determine the communication mode of the downlink channel and the uplink channel between the base station and the mobile terminal, so as to achieve smooth switching of the mobile terminal between different base stations; the base station and the mobile terminal both include a modem, the modem of the base station is connected to the external device through an IP switch, and the modem of the mobile terminal is connected to the external device through a WiFi module.

In this embodiment, a high-speed mobile wireless communication system based on FPGA is designed by using FPGA and OFDM technology, taking the highway as a typical case. Based on PN synchronization, the system specially designs the downlink channel, uplink channel and modem system for the communication process between the mobile terminal and the base station, realizes the asymmetric rate of the uplink and downlink channels, and the base station can automatically adjust the communication rate of each terminal according to the number of terminals that can be accessed.

Preferably, a wireless access device, i.e., a base station, is set up every 2 kilometers along the deployment scenario. The base station forms a 2.5G synchronous ring network through optical fiber and is connected to the section monitoring center, and each base station can simultaneously communicate with multiple mobile terminals through broadband. The mobile terminal can seamlessly switch between the coverage areas of the base station equipment during high-speed movement. The 5.8G frequency band is used for communication between the mobile terminal and the base station. The uplink (from the terminal to the base station) rate and the downlink (from the base station to the terminal) rate adopt an asymmetric mode, with low uplink and high downlink, and the uplink and downlink rate ratio can be configured. The maximum number of terminals that can be accessed simultaneously by each base station is N, where N can be configured to 32, 64, 128, etc., and the communication rate with each terminal can be automatically adjusted according to the number of terminals accessed simultaneously.

In the above embodiment, preferably, according to the distance between the base station and the monitoring center, the base station with an odd number is defined as an odd base station, and the base station with an even number is defined as an even base station. As shown in Figure 2, the data format of the downlink channel includes a synchronization header, a control bit 0, a control bit 1, a class 1 channel, and a class 2 channel. First, the timing synchronization and carrier synchronization between the mobile terminal and the base station are realized through the synchronization header. The control bit 0 and the control bit 1 not only indicate where the corresponding mobile terminal should extract data from the downlink channel, but also where the corresponding mobile terminal should send data from the uplink channel. Specifically, the even base station uses the control bit 0 time slot to send control information and the control bit 1 time slot is idle, and the odd base station uses the control bit 1 time slot to send control information and the control bit 0 time slot is idle. If the mobile terminal is connected to the even base station, it is not only necessary to extract the control information of the control bit 0 time slot, but also monitor the control bit 1 time slot to determine whether it has entered the range of the next base station. The mobile terminal connected to the odd base station is similar to the mobile terminal connected to the even base station mentioned above. All time slots of Class 1 channels can be used by base stations, even-numbered base stations can only use even-numbered time slots of Class 2 channels, leaving odd-numbered time slots vacant, and odd-numbered base stations can only use odd-numbered time slots of Class 2 channels, leaving even-numbered time slots vacant. Therefore, each base station must coordinate with its two neighboring base stations on the left and right to determine the allocation of its Class 1 and Class 2 channels.

In the above embodiment, preferably, in order to realize the smooth switching of the mobile terminal between different base stations, the base stations need to maintain good time synchronization, and the time calibration process is as follows: the monitoring center sends a reset command to all base stations, the monitoring center and the base stations start counting with the standard clock, the monitoring center sends a message to the base station when the count reaches 20 milliseconds, and when the base station receives the message, it records the count of its own counter at this time as the uplink count, and the base station sends a message to the monitoring center when the count reaches 20 milliseconds, and when the monitoring center receives the message, it records the count of its own counter at this time as the downlink count, and sends the downlink count to the corresponding base station, and the base station adjusts the base of its own counter according to the difference between the uplink count and the downlink count until the downlink count reaches the same value as the uplink count, thereby realizing the time calibration of the current base station. Only the base station that has completed the time calibration can send data through the downlink channel.

In the above embodiment, preferably, before sending data through the uplink channel, the mobile terminal must perform clock synchronization and carrier frequency synchronization with the base station through the synchronization header of the downlink channel. After the synchronization is completed, the mobile terminal controls the instructions of the uplink channel through the clock counter synchronized with the base station frame period to perform the corresponding action at the corresponding time; according to the different distances between the mobile terminal and the base station, the delay of receiving the base station information is different, so the base station must reserve an interval of 6.7us when formulating the uplink channel time slots for different mobile terminals. Similar to the Class 1 channel and Class 2 channel of the downlink channel, the uplink channel can also be divided into two categories: when the mobile terminal is in a Class 1 area, it can use the Class 1 channel to transmit data to the base station, and the so-called Class 1 channel means that its time slot does not need to avoid the time slot of the mobile terminal connected to the adjacent base station. When the mobile terminal is in a Class 2 area, it must use the Class 2 channel to transmit data to the base station, and the so-called Class 2 channel means that its time slot needs to avoid the time slot of the mobile terminal connected to the adjacent base station.

The data format of the uplink channel is shown in Figure 3. Since the time when the data sent by each mobile terminal arrives at the base station may be different, the uplink channel of each mobile terminal needs to be started with a synchronization header. The base station can lock the position of the data segment by the synchronization header. The frame format of the uplink channel is shown in Figure 4. The uplink channel starts with the network access application channel. When a base station and its adjacent base stations no longer accept new mobile terminal network access applications, the time slot occupied by the network access application channel can be removed from the uplink channel. The information carried by a frame of the uplink channel is completely determined by the control information of the downlink channel, and it contains uplink data of up to 64 mobile terminals.

As shown in FIG5 , in the above embodiment, preferably, the modem includes an ARM CPU, an address attribute controller, a transmission time slot controller, a receiving time slot controller, a control register, a memory, a digital modulator, a digital demodulator and a radio frequency module; the ARM CPU, the transmission time slot controller, the receiving time slot controller and the control register are connected to the memory through a data bus, the address attribute controller controls the ownership of the memory, the ARM CPU stores the data received through the 2.5G network in a certain position in the memory, the transmission time slot controller reads the data from the memory at a specific time and sends the data to the digital modulator, the digital modulator performs OFDM modulation on the received data, and sends the modulated data to the radio frequency module, which is transmitted through the antenna; the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, performs OFDM demodulation through the digital demodulator, and stores the demodulated data in the memory, the ARM CPU reads the data from the memory and sends the data to the IP switch. The action instructions followed by the transmission time slot controller and the receiving time slot controller are first placed in a specific position in the memory by the ARM CPU. Then the transmission and reception time slot controllers read the instructions from the memory in sequence and execute them. The transmit time slot controller sends data to the digital modulator, which is then sent to the antenna via the RF module, while the receive time slot controller receives the data demodulated by the digital demodulator, which is then sent to the IP switching module via the ARM CPU.

The difference between the modem of the base station and the modem of the mobile terminal is that the modem of the base station is connected to the IP switch, while the modem of the mobile terminal is connected to the WIFI device. At the same time, the standard clock of the base station is provided by the 2.5G network, while the working clock of the mobile terminal is generated by the modem itself, and adjusted according to the synchronization header of the received downlink channel, and finally synchronized to the standard clock of the base station. The IP switching module (the mobile terminal is the WIFI module) and the modem are connected together via the bus through the ARM CPU.

As shown in FIG6 , in the above embodiment, preferably, the digital modulator includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, a FIR HB Filter module, a Farrow Filter module, a DUC module and a Gain module;

When the transmit timeslot controller executes the TxPN instruction, the PN Generator module generates synchronization header information, otherwise it is idle at other times. The Mapper module loads the Tx_Data data onto the modulated signal according to the requirements of Tx_Mod. The Carrier Control module determines whether to insert the pilot subcarrier based on whether the SUB_CAR value in the transmit instruction is the same as the setting of the valid subcarrier number register. The Differential Encoder module is the differential encoder of the differential OFDM system. The iFFT module is used for inverse fast Fourier transform and is responsible for converting the frequency domain signal to the time domain to form an OFDM symbol. The CP module is responsible for adding the cyclic prefix of the OFDM symbol. When the instruction is the TxPN instruction, the MUX module selects the data of the synchronization header circuit to be transmitted to the subsequent module. When the instruction is the OFDM or PILOT instruction, the data of the OFDM circuit is selected. The FIR HB Filter module is used to increase the data sampling rate from 76MHz to 152MHz. The Filter module is used to interpolate and upsample the 152MHz clock sampling signal to a sampling rate of 156.25MHz. The DUC module is used to up-convert the baseband signal to an intermediate frequency signal. Finally, the Gain module adjusts the gain of the transmitted signal.

As shown in FIG7 , in the above embodiment, preferably, the digital demodulator includes an AGC module, a DCC module, a FarrowFilter module, a FIR HB Filter module, a DeMUX1 module, a PN Correlate module, a PLL module, a Correlator module, a FFT module, a DeMUX2 module, a Differential Decoder module, a Channel & Carrier Estimation module, an Equalizer module, a PHASOR module, a DeMapper module, a Post Proc module and a Pilot Drop module;

The AGC module is a pulse width modulation generation circuit, which is used to provide automatic gain control for the RF receiving amplifier and adjust the received signal to the preset amplitude. The DCC module is used to move the received signal from the intermediate frequency to the baseband. The Farrow Filter module and the FIR HB Filter module are used to interpolate and downsample the 156.25MHz clock sampling signal to a sampling rate of 152MHz and reduce the data sampling rate from 152MHz to 76MHz respectively. The DeMUX1 module selects different processing circuits according to the received instructions. If the instructions are RxPN Start and RxPN Stop, the received data will be passed to the PN processing circuit. When the instruction is OFDM or PILOT, the OFDM processing circuit is selected. In the PN processing circuit, the PN Correlate module is mainly responsible for the synchronization header search. When the receiving time slot controller executes the RxPN Start or RxPN Stop instruction, the module starts or ends the synchronization header search. The PLL and other modules provide the system with a close working clock, and in the later PN The Correlate module synchronizes the working clock with the working clock of the base station. The Correlator module in the OFDM circuit performs correlation operation on the first pilot symbol of the differential OFDM, thereby eliminating the ambiguity in the OFDM signal. The FFT module converts the OFDM signal in the time domain to the frequency domain. The DeMUX2 module and the Differential Decoder module respectively complete the difference and decoding of the OFDM signal. The DeMUX3 module is a data separation controller. When the module executes PILOT, the Channel&Carrier Estimation module is selected to complete the channel and carrier frequency estimation, but when the module executes the OFDM instruction, the Equalizer module is selected to complete the channel equalization. Considering that there is a certain carrier frequency deviation in the signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete the phase rotation, judge the received data to the constellation point of the modulated signal and extract the frequency deviation information according to the phase difference of the data before and after the judgment. Finally, the Pilot Drop module determines the insertion position of the pilot subcarrier according to whether the SUB_CAR value in the receiving instruction is the same as the setting of the effective subcarrier number register.

In the above embodiment, preferably, the specific process of performing clock synchronization and carrier frequency synchronization through the synchronization header includes a search process and a tracking process.

As shown in Figure 8, it is a schematic diagram of a frame structure with a length of 20ms (1520000 clock width) based on a 76MHz clock. The data frame uses a PN synchronization header as the start mark. The frame period is a counter with a 76MHz clock that counts from 0 to 1519999.

As shown in FIG8 , the time interval between the end point of the PN synchronization header and the end point of a frame is d=1519999-3079. In order to ensure that the hardware will encounter a PN synchronization header within a cycle, before the position of the PN synchronization header is locked, the frame length counter period is set to 30ms by software setting. When the hardware determines that the amplitude of the correlation peak is greater than the preset threshold, the hardware records the position x of the maximum correlation peak and the amplitude of the corresponding correlation peak, and sends an interrupt request to the ARM CPU. After receiving the interrupt request, the ARM CPU sets the clearing point of the frame length counter to the sum of the maximum correlation peak and the time interval between the end point of the synchronization header and the end point of the frame, that is, x+d. When the frame length counter reaches the clearing point, an interrupt request is sent to the ARM CPU. After receiving the interrupt request, the ARM CPU sets the period of the frame length counter to 20ms, that is, the clearing point of the frame length counter is set at the position of 1519999 of the frame end point, so that the PN synchronization header has the structure shown in FIG8 .

The tracking process includes timing tracking and carrier frequency tracking. The purpose of timing tracking is to synchronize the working clock of the mobile terminal with the working clock of the base station; the purpose of carrier frequency tracking is to synchronize the carrier frequency of the mobile terminal with the working carrier frequency of the base station.

During the timing tracking process, the schematic diagram of the system correlation peak is shown in Figure 9. There are two non-zero points on both sides of the main correlation peak, where the main correlation peak is point P (puncture); the correlation peak earlier than point P is point E (early); and the correlation peak later than point P is point L (late). First, the correlation peaks of points P, E, and L are obtained through the PN correlator and recorded in the corresponding registers. The timing error of the system clock is calculated. If the correlation peaks of the three points are represented as Punc_Corr, Early_Corr, and Late_Corr, respectively, the timing error Terr of the system clock can be expressed as:

The timing error of the system clock can be converted to Hertz Terr_hz as follows:

Terr_hz＝Terr×(1/TF)×(RS/FS) (2)

Where TF is the frame period, RS is the PN sequence symbol rate, and FS is the system clock frequency. When a timing error is detected, the software can correct the system deviation by adjusting the NCO.

In the carrier frequency tracking process, the carrier frequency offset information is first detected by the PN correlator, and then the software calculates the offset amount based on the carrier frequency offset information, and sets the correction amount back to the hardware circuit to correct the carrier frequency deviation. The software calculation process is as follows:

和

则Assumptions

and

but

Therefore, the phase difference α is

For small angles, the phase difference calculation can be approximated as

由于Lpn为PN序列的总长度，而α为

个PN符号累计的相位差，因此载频偏差可计算如下：Assume that Δf is the carrier frequency offset, Rs is the PN symbol rate, and Δp is the phase of each PN symbol, then

Since Lpn is the total length of the PN sequence, and α is

The carrier frequency deviation can be calculated as follows:

因此Considering that in order to estimate the carrier frequency deviation with a certain accuracy, α needs to be no more than

therefore

In order to verify the reliability of the FPGA-based high-speed mobile wireless communication system proposed in the above embodiment, the base station is set up on the roof of the building, and the antenna is aligned with the terminal test point pre-selected at 500m. The position of the terminal test point is shown in Figure 10. The mobile cabinet terminal equipment, antenna, monitoring computer, and battery are placed on a bicycle to form a mobile test platform. First, the antenna static alignment debugging is performed at the predetermined test point, so that the maximum gain direction of the base station antenna is aligned with the predetermined terminal test point, and then a dynamic test is performed, that is, the tester rides a bicycle along the road and circles back and forth. At the same time, during the circle process, the base station and the terminal respectively continuously print RSSI values (RSSI values are taken at intervals of no more than 0.1ms). In the above test environment, RSSI analysis is performed on the gain antenna and signal of the terminal.

The antenna is set to a high-gain omnidirectional antenna, and the fading depth test is performed under broadband signal excitation. Analysis is performed in two situations: moving toward the base station and moving away from the base station.

As shown in Figures 11 and 12, the data on the mobile terminal side are analyzed. The linear trend of the RSSI value is gradually increasing when moving toward the base station, while the trend is gradually decreasing when moving away from the base station. At the same time, in terms of standard deviation and maximum swing, the backward movement is larger than the forward movement, while in terms of average value, the backward movement is smaller than the forward movement.

As shown in Figures 13 and 14, the data on the base station side is analyzed, and its data trend is basically consistent with the data trend on the mobile terminal side in Figures 11 and 12. However, since Figure 14 contains RSSI data during the running steering process, this type of data will have a relatively large average value depression.

In order to analyze the impact of the gain antenna of the terminal, a high-gain omnidirectional antenna and a low-gain omnidirectional antenna are selected for comparison under the condition of ensuring bandwidth signal excitation. The results are shown in Table 1 below. In terms of average value, the signal strength in the direction of movement away from the base station is greater than that in the direction of movement toward the base station, and the difference is obvious. The main reason is the difference in the angle between the maximum gain direction of the antenna and the direction of the incoming wave. In terms of standard deviation and swing, the value in the direction of movement away from the base station is greater than that in the direction of movement toward the base station. The main reason is that when moving toward the base station, the angle between the maximum gain direction of the omnidirectional antenna and the direction of the line-of-sight incoming wave is small, the line-of-sight incoming wave signal obtains high gain, and the multipath scattered waves in other directions are suppressed. The energy of the line-of-sight incoming wave is much stronger than that of the multipath scattered wave, so the strong fluctuation of the signal caused by fast fading is relatively small. When moving away from the base station, the angle between the maximum gain direction of the omnidirectional antenna and the incoming wave direction is relatively large, deviating from the maximum gain direction, the gain is reduced, and some heat dissipation paths are in the maximum gain direction, resulting in an increase in the total signal strength of the heat dissipation path. Compared with the movement toward the base station, the main signal strength of the line-of-sight wave is reduced, while the signal of the heat dissipation path is enhanced, and the strong difference between the main signal and the signal of the scattering path is reduced, resulting in greater fluctuations in the strength of the fast fading signal. In the comparison of the two types of antennas, when moving toward the base station, the standard deviation of the high-gain antenna on the base station side is slightly larger than that of the low-gain antenna, but the standard deviation of the low-gain antenna on the terminal side is significantly larger than that of the high-gain antenna. When moving away from the base station, the standard deviation of the two types of antennas on the base station side is not much different, but the standard deviation of the low-gain antenna on the terminal side is significantly larger than that of the high-gain antenna. Therefore, on the whole, the high-gain antenna has a slight advantage over the low-gain antenna. The main reason is that the swing of the antenna during movement causes a dramatic angle change, and the gain change caused by the angle change is added, which causes the received energy change.

Table 1 Comparison of dynamic RSSI of antennas with different gains

In order to analyze the impact of the signal selection of the terminal, the broadband signal and the bass signal are selected for comparison under the condition of ensuring low gain antenna. The results are shown in Table 2 below. In terms of standard deviation and swing, the value in the direction of movement away from the base station is larger than that in the direction of movement toward the base station. For specific reasons, please refer to the gain antenna analysis for mobile terminals above. The maximum swing and standard deviation of the single-tone signal are both larger than those of the broadband signal, so the single-tone signal can better measure the actual fading depth. The main reason is that for the broadband signal, at a certain moment, the fading of different frequencies is different. RSSI is a statistical energy in the band (the density product of all frequency components in the band), so it masks the actual frequency selection fading depth. However, the energy of the single-tone signal is more concentrated than that of the broadband signal, so once a deep fading occurs at this frequency point, RSSI can accurately reflect it.

Table 2 Comparison of RSSI of single-tone bandwidth signal

According to the FPGA-based high-speed mobile wireless communication system proposed in the above embodiment, it can be known from the above test that it can not only realize the simultaneous access of multiple terminals, but also automatically adjust the communication rate of the terminal according to the number of terminals connected. In the system testing stage, the maximum swing, standard deviation and average value of the terminal moving toward the base station and moving away from the base station are analyzed, and the single-tone bandwidth signal RSSI is compared, which solves the problem of seamless switching of mobile terminals in the process of high-speed mobile communication.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (7)

1. A high-speed mobile wireless communication system based on FPGA is characterized in that, comprising: base station, mobile terminal, monitoring center and optical fiber ring network; A base station is set at every preset distance along the optical fiber, and a 2.5G synchronous ring network is formed between the base stations through the optical fiber, and is connected to the monitoring center, and broadband communication is performed between the mobile terminal and the base station ; Timing synchronization and carrier synchronization are implemented between the mobile terminal and the base station, and the uplink rate and downlink rate between the mobile terminal and the base station adopt an asymmetric mode with a configurable uplink and downlink rate ratio, and each of the The communication rate of the mobile terminal is automatically configured according to the number of mobile terminals simultaneously accessing the base station; Coordinating between the base station and adjacent base stations to determine the communication mode of the downlink channel and uplink channel between the base station and the mobile terminal, so as to realize the smooth handover of the mobile terminal between different base stations; Both the base station and the mobile terminal include a modem, the modem of the base station is connected to external equipment through an IP switch, and the modem of the mobile terminal is connected to external equipment through a WiFi module; Sorting according to the distance between the base station and the monitoring center from near to far, defining a base station with an odd number as an odd base station, and a base station with an even number as an even base station; The data format of the downlink channel includes a synchronization header, a control 0 bit, a control 1 bit, a type 1 channel and a type 2 channel, and the timing synchronization and carrier synchronization between the mobile terminal and the base station are realized through the synchronization header, The even base station uses the control 0-bit time slot to send control information and control the 1-bit time slot to be idle, and the odd base station uses the control 1-bit time slot to send control information and control the 0-bit time slot to be idle; All the time slots of the 1-type channel can be used by the base station, the even base station can only use the even-numbered time slots of the 2-type channel, and the odd-numbered time slots are vacant, and the odd base station can only use the odd-numbered time slots and even-numbered time slots of the 2 types of channels. Ordinal slots are vacant. 2. FPGA-based high-speed mobile wireless communication system according to claim 1, is characterized in that, described monitoring center sends reset order to all base stations, and described monitoring center and described base station all begin to count with standard clock, described When the monitoring center counts to the preset time, it sends a message to the base station. When the base station receives the message, it records the count of its own counter as an uplink count, and when the base station counts to the preset time, it sends a message to the monitoring center. When the monitoring center receives the message, it records the count of its own counter as the downlink count at this time, and sends the downlink count to the corresponding base station, and the base station according to the difference between the uplink count and the downlink count The value adjusts the base number of its own counter until the downlink count and the uplink count reach the same value, so as to realize the time calibration of the current base station. 3. the FPGA-based high-speed mobile wireless communication system according to claim 2 is characterized in that, the mobile terminal carries out clock synchronization and carrier frequency synchronization with the base station through the synchronization head of the downlink channel, and the synchronization is completed after the synchronization is completed. The mobile terminal controls the instructions of the uplink channel through a clock counter synchronized with the base station to perform corresponding actions at corresponding times; According to the difference between the distance between the mobile terminal and the base station, when the mobile terminal is in a type 1 area, it sends a message to the base station through a type 1 channel in the uplink channel that does not need to avoid the time slot of the mobile terminal connected to the adjacent base station Sending data, when in the type 2 area, sending data to the base station through the type 2 channel in the uplink channel that needs to avoid the time slot of the mobile terminal connected to the adjacent base station; The uplink channel starts with a network access application channel, and the time slot occupied by the network access application channel can be removed from the uplink channel only when a base station and its adjacent base stations no longer accept network access applications from new mobile terminals. 4. the high-speed mobile wireless communication system based on FPGA according to claim 1, is characterized in that, described modem comprises ARM CPU, address attribute controller, transmitting time slot controller, receiving time slot controller, control register, memory , digital modulator, digital demodulator and radio frequency module; The ARM CPU, the transmit time slot controller, the receive time slot controller, and the control register are connected to the memory through a data bus, the address attribute controller controls the ownership of the memory, and the The ARM CPU stores the received data in the memory, and the transmission time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, and the digital modulator will receive performing OFDM modulation on the data, and sending the modulated data to the radio frequency module; The receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, performs OFDM demodulation through the digital demodulator, and stores the demodulated data in the memory, The ARM CPU reads data from the memory and sends the data to the IP switch. 5. FPGA-based high-speed mobile wireless communication system according to claim 4, is characterized in that, described digital modulator comprises PN Generator module, Mapper module, Carrier Control module, Differential Encoder module, iFFT module, CP module module , MUX module, FIR HB Filter module, Farrow Filter module, DUC module and Gain module; When the transmission time slot controller is executing the TxPN command, the PN Generator module generates synchronous header information, otherwise it is idle at other times, and the Mapper module loads the Tx_Data data on the modulation signal according to the requirements of Tx_Mod, so The Carrier Control module determines whether to insert pilot subcarriers according to whether the SUB_CAR value in the transmission command is the same as the setting of the effective subcarrier number register, the Differential Encoder module is a differential encoder for a differential OFDM system, and the iFFT module is used for fast The inverse Fourier transform is responsible for converting the frequency domain signal to the time domain to form OFDM symbols; The CP module module is responsible for adding the cyclic prefix of the OFDM symbol. When the instruction is a TxPN instruction, the MUX module selects the data of the synchronous head circuit to be transmitted to the back module, and selects the data of the OFDM circuit when the instruction is an OFDM or PILOT instruction; The FIR HB Filter module is used to increase the data sampling rate from 76MHz to 152MHz, the FarrowFilter module is used to interpolate and upsample the 152MHz clock sampling signal to a sampling rate of 156.25MHz, and the DUC module is used to upconvert the baseband signal to intermediate frequency signal, and finally the Gain module adjusts the gain of the transmitted signal. 6. the high-speed mobile wireless communication system based on FPGA according to claim 4, is characterized in that, described digital demodulator comprises AGC module, DCC module, Farrow Filter module, FIR HB Filter module, DeMUX1 module, PNCorrelate module, PLL module, Correlator module, FFT module, DeMUX2 module, Differential Decoder module, Channel&Carrier Estimation module, Equalizer module, PHASOR module, DeMapper module, Post Proc module and Pilot Drop module; The AGC module is a pulse width modulation generating circuit, which is used to provide automatic gain control for the radio frequency receiving amplifier and adjust the received signal to a preset amplitude. The DCC module is used to move the received signal from the intermediate frequency to the base frequency. The FarrowFilter The module and the FIR HB Filter module are respectively used to interpolate and downsample the 156.25MHz clock sampling signal to a 152MHz sampling rate and reduce the data sampling rate from 152MHz to 76MHz. The DeMUX1 module selects different processing circuits according to the received instructions, If the instruction is RxPN Start and RxPN Stop, the received data is transferred to the PN processing circuit, and when the instruction is OFDM or PILOT, the OFDM processing circuit is selected. In the PN processing circuit, the PN Correlate module is mainly responsible for synchronous head search. When the When the receiving slot controller executes the RxPN Start or RxPN Stop command, the module starts or ends the sync header search; The PLL module provides the system with a close working clock, and in the later stage, the PN Correlate module synchronizes the working clock with the working clock of the base station, and the Correlator module in the OFDM circuit is aimed at the first pilot symbol of the differential OFDM Perform correlation operations to eliminate ambiguity in OFDM signals; The FFT module converts the OFDM signal in the time domain to the frequency domain, the DeMUX2 module and the DifferentialDecoder module respectively complete the difference and decoding of the OFDM signal, and the DeMUX3 module is a data separation controller. When the module executes PILOT , then select the Channel&Carrier Estimation module to complete channel and carrier frequency estimation, but when the module executes the OFDM instruction, then select the Equalizer module to complete channel equalization; Considering that there is a certain carrier frequency deviation in the signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete the phase rotation, and judge the received data to the constellation point of the modulated signal and according to the phase difference of the data before and after the judgment The task of extracting frequency offset information, and finally the Pilot Drop module determines the insertion position of the pilot subcarrier according to whether the SUB_CAR value in the received command is the same as the setting of the effective subcarrier number register. 7. according to the described high-speed mobile wireless communication system based on FPGA of claim 1 or 3, it is characterized in that, the concrete process that carries out clock synchronization and carrier frequency synchronization by synchronization head comprises search process and tracking process; In the search process, before the position of the synchronization head is locked, the period of the frame length counter is set by software setting. When the amplitude of the correlation peak is greater than the preset threshold, the position of the largest correlation peak and the amplitude of the corresponding correlation peak are recorded. And send interrupt request to ARM CPU, after ARM CPU receives the interrupt request, the clearing point of the frame length counter is set to the sum value position of the time interval between the maximum correlation peak and the end point of the synchronization head and the end point of the frame; After the frame length counter reaches the clearing point, an interrupt request is sent to the ARM CPU, and the period of the frame length counter is set after the ARM CPU receives the interrupt request, so that the clearing point of the frame length counter is positioned at the frame end point position; The tracking process includes timing tracking and carrier frequency tracking. In the timing tracking process, the main correlation peak and the correlation peaks on both sides are obtained through the PN correlator, and the timing error of the system clock is calculated, and the timing error is corrected by adjusting the NCO; During the carrier frequency tracking process, the carrier frequency offset information is detected by the PN correlator, the offset amount is calculated according to the carrier frequency offset information, and the correction amount is set back to the hardware circuit to correct the carrier frequency offset.

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