CN112038233A - Method for reducing load effect of different products in furnace tube - Google Patents
Method for reducing load effect of different products in furnace tube Download PDFInfo
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- CN112038233A CN112038233A CN202010878027.6A CN202010878027A CN112038233A CN 112038233 A CN112038233 A CN 112038233A CN 202010878027 A CN202010878027 A CN 202010878027A CN 112038233 A CN112038233 A CN 112038233A
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- 230000000694 effects Effects 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000012360 testing method Methods 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 13
- 238000004364 calculation method Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 39
- 235000012431 wafers Nutrition 0.000 description 28
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 poly spacer nitride Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract
The invention discloses a method for reducing the load effect of different products in a furnace tube, which comprises the following steps: step 1, after a new product is subjected to photoetching, calculating a load effect numerical value by adopting a formula P ═ C multiplied by Y + frame)/S, wherein P represents the graph perimeter of a unit area in a single shot, C represents the graph perimeter of a single chip, and X represents the line number of the chips in the shot; y is the number of columns of the chips in the shot, and S is Field shot size; step 2, defining the perimeter of the graph in unit area in a single shot as a load effect value, and classifying according to the load effect value; step 3, selecting a corresponding number effect value according to the classification of the load effect value of the new product, adjusting the temperature of the five ends of the furnace tube, and performing film forming off-line test operation by using the polished section until the film thickness of the polished section in the furnace tube reaches the test target film thickness; and 4, directly operating according to the category of the new product. The invention can quickly and accurately estimate the load effect of different products, reduce the number of silicon chips for new product trial operation and save the trial operation time.
Description
Technical Field
The invention relates to a semiconductor integrated circuit manufacturing technology, in particular to a method for reducing the load effect of different products in a furnace tube.
Background
With the development of integrated circuit processes and the continuous reduction of critical dimensions, thin film fabrication techniques are receiving more and more attention in semiconductor fabrication. In semiconductor integrated circuit process, since a long operation time is required for growing a thin film by using a furnace, a plurality of silicon wafer groups (lot, i.e. a set of silicon wafers having the same process flow) are generally placed in a batch (lot, i.e. a set of lots having the same operation condition at a lot operation equipment site and capable of operating together at the same time) and operated at the same time, and the batches all use the same process condition (recipe).
However, since the furnace tube itself has a gas flow depletion effect, the thickness of the films grown on the silicon wafer through which the gas passes first and the silicon wafer through which the gas passes later in the same batch is different, as shown in fig. 1, and thus the film growth in the technical node with a small critical dimension is difficult to satisfy. In this case, a method commonly used in the industry is to adjust a temperature controller within process conditions to adjust a temperature and a filling light sheet (NPW wafer, i.e., a non-productive silicon wafer) to a vacant position (slot), thereby solving the problem of uneven film thickness caused by a depletion effect.
However, the area required for film formation is different for each product, and when the surface area of different products is greatly different, the film thickness problem caused by depletion effect needs to be solved by adjusting the temperature of the recipe. Therefore, in order to meet the film forming requirements of different products, independent film forming temperature compensation conditions are used so as to meet the film thickness requirement of the process.
For example, when a gate spacer (poly spacer nitride) is grown, the difference between products is large, and the difference between load effects caused by different chip designs is also large. In semiconductor chip manufacturing, there are a large number of new products (NTO) that are off-line, and typically require a small number of silicon lots to be run in a pilot run. In order to ensure the accurate film thickness, when the gate sidewall layer deposition process is performed on the furnace tube, the load effect difference can be known only by filling the furnace tube batch with a new product and then testing the thickness difference, so as to adjust the temperature of the process conditions to improve the load effect. However, the method has a problem that the silicon wafers are used in a large amount when all batches of furnace tubes are filled with new products for trial run, and the method is extremely disadvantageous to both the productivity and the progress of the trial run of the new products.
In the conventional method, the difference between these products is determined in advance by the Data Rate (i.e., the pattern density, which is the ratio of the front area of the polysilicon to the whole chip area) of the reticle, but it is found that this method cannot be determined accurately in practical use.
For example, in a method for reducing the load effect of thin film growth in a furnace tube disclosed in patent CN102347208A, the perimeter and height of the step before film formation in the chip, the area of the chip, the film formation rate of the front surface in the chip, and the film formation rate of the side surface of the step in the chip are used to calculate the load effect value of each chip with the same program, and then the chips with the calculated load effect value less than or equal to 170% are arranged to perform simultaneous operation, for the chips with the load effect value greater than 170%, the difference between the load effect values of any two chips is compared, and when the difference is less than 30%, the simultaneous operation is arranged to perform, and the chips belonging to other cases are uniformly and separately operated. The method cannot accurately define the difference of film forming thickness on the silicon wafer, and the process with the technical node below 40nm has extremely strict requirements on the thickness of the side wall of the grid electrode.
This method has several disadvantages:
1. the perimeter of the step before film formation in the chip is not provided with a frame area (the photomask projects to the shot area of the silicon wafer, and the rest area is removed from the die area), so that the influence on the actual thickness is large;
2. the height of the step needs to confirm the slicing result, and the trial operation time is long;
3. when the difference between the values of the loading effects between the two chips is less than 30%, the simultaneous operation is scheduled, and the difference of 30% is 1/6 of the loading effect, so that the thickness cannot be accurately controlled.
Disclosure of Invention
The invention aims to provide a method for reducing the load effect of different products in a furnace tube.
In order to solve the above problems, the present invention provides a method for reducing the loading effect of different products in a furnace tube, comprising the following steps:
P＝(C×X×Y+frame)/S
wherein, P represents the graph perimeter of unit area in a single shot, C represents the graph perimeter of a single chip, and X represents the line number of the chip in the shot; y is the number of columns of the chips in the shot, frame is the graph perimeter of the residual area except the chips in the single shot, and S is the plane area of the photomask projected on the silicon wafer;
and step 4, directly performing operation according to the category of the new product silicon chip and the process condition verified in the step S3.
In step 1, the parameter C, the parameter frame, and the parameter S are extracted by OPC software.
In step 1, the parameters X and Y are extracted through the mask.
Wherein, the number-of-chips effect value is the difference between the TOP end film thickness, the C-TOP end film thickness, the CTR end film thickness and the C-BTM end film thickness of the furnace tube and the BTM end film thickness respectively.
Wherein, the testing target film thickness is determined by the classification of the load effect value of the new product silicon wafer.
Compared with the prior art, the invention has the following beneficial effects:
firstly, the invention can better characterize and distinguish the load condition of the growth of different product silicon wafer films in the furnace tube, and the deposited film thickness can reach a set target value;
secondly, for the trial operation of new products, the method can reduce the number of wafers for trial operation of the new products in the furnace tube, and the method can quickly acquire data in advance without waiting for collecting the data, thereby saving the trial operation time.
Drawings
FIG. 1 is a schematic view of a furnace tube for performing a HCD silicon nitride deposition process;
FIG. 2 is a flow chart of a method of the present invention;
FIG. 3 is a schematic diagram of the placing positions of the furnace tubes for performing the HCD light sheet off-line test operation.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
Other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The method for reducing the load effect of different products in the furnace tube of the embodiment of the invention, as shown in fig. 2, comprises the following steps:
P＝(C×X×Y+frame)/S
wherein, P represents the graph perimeter of unit area in a single shot, C represents the graph perimeter of a single chip, and X represents the line number of the chip in the shot; y is the number of columns of the chips in the shot, frame is the graph perimeter of the residual area except the chips in the single shot, and S is the plane area of the photomask projected on the silicon wafer;
and step 4, directly performing operation according to the category of the new product silicon chip and the process condition verified in the step S3.
In step 1, the parameters C, frame and S are extracted by OPC software.
In step 1, the parameters X and Y are extracted through the mask.
The number effect value is the difference between the TOP end film thickness, the C-TOP end film thickness, the CTR end film thickness and the C-BTM end film thickness of the furnace tube and the BTM end film thickness respectively. The corresponding relationship between the classification of the load effect value and the sheet effect value can be set by a person skilled in the art.
The thickness of the tested target film is determined by classifying the load effect value of the new product silicon wafer.
Taking an HCD silicon nitride deposition process in a furnace tube as an example, a trial operation is required when a new product (NTO) is offline, parameters are extracted by OPC software after the new product finishes a photoetching (poly photo) process, and a load effect value of the new product is calculated by using a formula in the step 1, wherein the perimeter of a unit area pattern of a new product silicon wafer 1 is 0-3, the load effect type is a first type, the perimeter of a unit area pattern of a new product silicon wafer 2 is 3-6, the load effect type is a second type, the perimeter of a unit area pattern of a new product silicon wafer 3 is 6-9, and the load effect type is a third type.
Before a new product enters a furnace tube for gate sidewall deposition, a corresponding sheet number effect value (loading effect) is selected according to the load effect category of the new product, the five-end temperature in the process condition of the furnace tube is adjusted, and a sheet offline test run (NPW monitor off test run) is performed to verify the film thickness until the corresponding test target film thickness is reached, as shown in table 1. Wherein, the placing position of the light sheet in the furnace tube is shown in fig. 3.
TABLE 1 distribution of target film thickness and number of effect values for testing light sheets corresponding to different load effect categories
The invention can quickly, simply and accurately estimate the influence of the load effect of different products, can better represent and distinguish the load condition of the growth of the silicon wafer films of different products in the furnace tube, and the deposited film thickness can reach the set target value. For the trial operation of a new product, the invention can reduce the number of silicon wafers for trial operation of the new product in the furnace tube, and the method can quickly obtain data in advance without waiting for collecting the data, thereby saving the trial operation time.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.
Claims (5)
1. A method for reducing the loading effect of different products in a furnace tube is characterized by comprising the following steps:
step 1, after completing photoetching of a new product silicon wafer, calculating a load effect value by adopting the following formula;
P＝(C×X×Y+frame)/S
wherein, P represents the graph perimeter of unit area in a single shot, C represents the graph perimeter of a single chip, and X represents the line number of the chip in the shot; y is the number of columns of the chips in the shot, frame is the graph perimeter of the residual area except the chips in the single shot, and S is the plane area of the photomask projected on the silicon wafer;
step 2, defining the perimeter of the graph of the unit area in the single shot obtained by calculation as a load effect value, and classifying according to the load effect value, wherein a new product with the load effect value of 0-3 is in a first category, a new product with the load effect value of 3-6 is in a second category, a new product with the load effect value of 6-9 is in a third category, and a new product with the load effect value greater than 9 is in a fourth category;
step 3, selecting a corresponding wafer number effect value according to the classification of the load effect value of the new product silicon wafer, adjusting the temperature of the five ends of the furnace tube, and performing film forming off-line test operation by using a polished section until the film thickness of the polished section in the furnace tube reaches the test target film thickness;
and step 4, directly performing operation according to the category of the new product silicon chip and the process condition verified in the step S3.
2. The method for reducing the loading effect of different products in the furnace tube according to claim 1, wherein in step 1, the parameter C, the parameter frame and the parameter S are extracted by OPC software.
3. The method of claim 1, wherein in step 1, the parameters X and Y are extracted through a mask.
4. The method as claimed in claim 1, wherein the sheet count effect value is a difference between a TOP end film thickness, a C-TOP end film thickness, a CTR end film thickness, a C-BTM end film thickness and a BTM end film thickness of the furnace tube.
5. The method as claimed in claim 1, wherein the target film thickness is determined by classifying the loading effect value of the new product wafer.
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| CN202010878027.6A CN112038233B (en) | 2020-08-27 | 2020-08-27 | Method for reducing load effect of different products in furnace tube |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114262880A (en) * | 2021-12-16 | 2022-04-01 | 上海华虹宏力半导体制造有限公司 | Method for automatically regulating and controlling thickness of deposited film of LPCVD furnace tube |
| CN119685809A (en) * | 2025-02-25 | 2025-03-25 | 合肥晶合集成电路股份有限公司 | Control system and control method for chemical vapor deposition film thickness of semiconductor device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001101258A (en) * | 1999-10-04 | 2001-04-13 | Hitachi Ltd | Method of calculating effective load capacitance in wiring section and method of calculating delay time of electronic circuit |
| US6667070B1 (en) * | 2001-02-02 | 2003-12-23 | Advanced Micro Devices, Inc. | Method of in situ monitoring of thickness and composition of deposited films using raman spectroscopy |
| CN102347208A (en) * | 2010-08-05 | 2012-02-08 | 上海华虹Nec电子有限公司 | Method for reducing loading effect of thin film growth in furnace tube |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN102768955A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for forming low-loading-effect thin film |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN104701212A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Method for detecting etching load effects |
| CN109629006A (en) * | 2019-01-31 | 2019-04-16 | 长江存储科技有限责任公司 | Boiler tube board and toilet |
-
2020
- 2020-08-27 CN CN202010878027.6A patent/CN112038233B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001101258A (en) * | 1999-10-04 | 2001-04-13 | Hitachi Ltd | Method of calculating effective load capacitance in wiring section and method of calculating delay time of electronic circuit |
| US6667070B1 (en) * | 2001-02-02 | 2003-12-23 | Advanced Micro Devices, Inc. | Method of in situ monitoring of thickness and composition of deposited films using raman spectroscopy |
| CN102347208A (en) * | 2010-08-05 | 2012-02-08 | 上海华虹Nec电子有限公司 | Method for reducing loading effect of thin film growth in furnace tube |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN102768955A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for forming low-loading-effect thin film |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN104701212A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Method for detecting etching load effects |
| CN109629006A (en) * | 2019-01-31 | 2019-04-16 | 长江存储科技有限责任公司 | Boiler tube board and toilet |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114262880A (en) * | 2021-12-16 | 2022-04-01 | 上海华虹宏力半导体制造有限公司 | Method for automatically regulating and controlling thickness of deposited film of LPCVD furnace tube |
| CN114262880B (en) * | 2021-12-16 | 2023-11-17 | 上海华虹宏力半导体制造有限公司 | Method for automatically regulating and controlling deposition film thickness of LPCVD furnace tube |
| CN119685809A (en) * | 2025-02-25 | 2025-03-25 | 合肥晶合集成电路股份有限公司 | Control system and control method for chemical vapor deposition film thickness of semiconductor device |
| CN119685809B (en) * | 2025-02-25 | 2025-04-22 | 合肥晶合集成电路股份有限公司 | Control system and control method for chemical vapor deposition film thickness of semiconductor device |
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