CN112034754B

CN112034754B - A servo drive that supports multiple encoder protocols

Info

Publication number: CN112034754B
Application number: CN202010846912.6A
Authority: CN
Inventors: 赵茵茵; 刘波; 汤小平
Original assignee: Wuhu Qingneng Dechuang Electronic Technology Co ltd; Tsino Dynatron Electrical Technology Beijing Co ltd
Current assignee: Wuhu Qingneng Dechuang Electronic Technology Co ltd; Tsino Dynatron Electrical Technology Beijing Co ltd
Priority date: 2020-08-21
Filing date: 2020-08-21
Publication date: 2025-03-28
Anticipated expiration: 2040-08-21
Also published as: CN112034754A

Abstract

The present invention relates to a servo drive supporting multiple encoder protocols. The servo driver supporting multiple encoder protocols is based on a servo driver control architecture of DSP+FPGA, uses a low-cost solid-state memory, can realize the support of the multiple encoder communication protocols without adding additional hardware and interfaces, and has the characteristics of simple structure, low cost and the like.

Description

Servo driver supporting multiple encoder protocols

Technical Field

The present invention relates to the field of encoded drives, and more particularly, to a servo drive supporting multiple encoder protocols.

Background

In the servo control system, an encoder is often employed as a position detecting element. Different application systems will choose different encoders, which often support different communication protocols, depending on design requirements. When the servo drive is used in a multi-encoder system, it is necessary to replace the external encoder, and to replace the drive or to re-download Field-Programmable gate array (GATE ARRAY, FPGA) firmware.

In the prior art, patent CN206563893U mentions a data transmission system using a plurality of encoder interface circuits, which can support a plurality of encoders at the same time. The encoder modules may extend more encoder channels in a cascaded manner. The patent supports a plurality of encoders and simultaneously needs to be externally connected with a plurality of encoder interfaces, so that the hardware structure is complex, and the system cost is increased.

The servo controller in CN206848742U needs to re-download FPGA firmware when supporting multiple communication protocol encoders, without replacing the servo control circuit board. This patent requires that different encoders be supported by re-downloading FPGA firmware supporting different communication protocols. Downloading programs in some customer application sites is cumbersome, and when the number of drivers is large, the debugging efficiency is affected.

Patent CN202710997U mentions that when the servo controller supports multiple communication protocol encoders, the servo control circuit board does not need to be replaced, but the FPGA firmware needs to be downloaded again. For a complex customer site where the servo driver is installed, when encoders with different communication protocols need to be replaced, the FPGA firmware needs to be downloaded again by disassembling equipment, so that the maintenance workload of products is greatly increased, and the generation efficiency is reduced.

Disclosure of Invention

The invention aims to provide a servo driver supporting multiple encoder protocols, which has the characteristics of simple structure, low cost and the like on the basis of supporting the use functions of multiple encoders.

In order to achieve the above object, the present invention provides the following solutions:

A servo driver supporting multiple encoder protocols comprises an encoder interface, an FPGA, a DSP (digital signal processor, english holly: DIGITAL SIGNAL Process) and a solid state memory (Flash);

the FPGA is respectively connected with the DSP and the solid-state memory, and the DSP is connected with the solid-state memory;

The solid-state memory is used for storing FPGA program data of various encoder communication protocols, the encoder communication protocols corresponding to the program data stored in the solid-state memory are different, the encoder interface is used for connecting an encoder to be driven, the DSP is used for generating a chip selection signal according to the servo parameters so as to open or close the solid-state memory, the FPGA is used for reading the program data stored in the solid-state memory, determining the connected encoder communication protocol according to the servo parameters of a driver, analyzing transmission data of the encoder to be driven through the encoder data analysis function module and uploading the transmission data to the DSP through the DSP data interaction function module, and the DSP is used for carrying out data interaction through the FPGA interaction function module and the FPGA and updating servo driving data in real time according to the position data uploaded by the FPGA so as to drive the motor to stably run.

Preferably, the encoder interface is connected with an encoder data analysis module of the FPGA, the FPGA is connected with the DSP through an SPI interface, a nCFG interface and an Init interface, the SEL interface of the DSP is connected with the/CE signal of the solid-state memory through a switch selection device, and the nCSC interface of the FPGA is connected with the/CE signal of the solid-state memory through a switch selection device.

Preferably, the solid-state memory comprises a first solid-state memory and a second solid-state memory;

The data output interface of the first solid-state memory and the data output interface of the second solid-state memory are connected with the nCSC interface of the FPGA through switch selection devices.

Preferably, the first solid-state memory is turned on when the SEL interface output value is 0, and the second solid-state memory is turned on when the SEL interface output value is 1.

Preferably, the system also comprises an upper computer;

The upper computer is used for sending a command for updating the communication program data of the encoder stored in the solid-state memory to the DSP, so that the FPGA is updated on line.

Preferably, the number of the FPGAs is 1.

Preferably, the number of the encoder interfaces is 1.

According to the specific embodiment provided by the invention, the servo driver supporting multiple encoder protocols has the following technical effects that the servo driver control architecture based on the DSP+FPGA uses a low-cost solid-state memory, and the support of multiple encoder communication protocols can be realized without adding additional hardware and interfaces, so that the whole system has the characteristics of simple structure, low cost and the like.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a servo drive supporting multiple encoder protocols in accordance with the present invention;

FIG. 2 is a control block diagram of a servo drive supporting multiple encoder protocols provided by the present invention;

FIG. 3 is a control block diagram of a default support for a first solid-state memory in an embodiment of the invention;

FIG. 4 is a schematic diagram of a structure of a DSP after replacing a solid-state memory according to an embodiment of the present invention;

FIG. 5 is a functional block diagram of encoder data processing in an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

FIG. 1 is a schematic structural diagram of a servo driver supporting multiple encoder protocols, which is provided by the invention, and comprises an encoder interface, an FPGA, a DSP and a solid-state memory, wherein the number of the FPGA and the encoder interface is preferably 1.

The solid-state memory is used for storing a plurality of program data supporting the communication protocols of the encoders, the communication protocols of the encoders supported by the program data stored in the solid-state memory are different, the encoder interface is used for reading position data acquired by the encoder to be driven, the DSP is used for controlling input values of the Flash chip select signals according to the servo parameters so as to open or close the solid-state memory, the FPGA is used for reading the program data stored in the solid-state memory, the encoder data connected with the current servo driver are analyzed through the encoder data analysis module, the position data obtained after analysis are uploaded to the DSP through the DSP data interaction module, the DSP performs data interaction through the FPGA interaction function module and the FPGA, and servo drive data are updated in real time according to the position data uploaded by the FPGA so as to drive the motor to stably run.

In the above technical solution provided in the present invention, the driver may support, but is not limited to, encoders of synchronous and asynchronous protocols such as nikon, polymoton, biss, SSI, endat2.2, etc.

Preferably, the encoder interface is connected with an encoder data analysis module of the FPGA, the FPGA is connected with the DSP through an SPI interface, a nCFG interface and an Init interface, the SEL interface of the DSP is connected with the/CE interface of the solid-state memory through a switch selector, and the nCSC interface of the FPGA is connected with the/CE interface of the solid-state memory. The SPI communication between the DSP and the FPGA can use any other communication mode.

On a servo driver control architecture based on a DSP+FPGA, the solid-state memory can use two low-cost program memory chips Flash1 and Flash2 (a first solid-state memory and a second solid-state memory);

The data output interface of the first solid-state memory and the data output interface of the second solid-state memory are connected with the nCSC interface of the FPGA through the switch selection device.

In order to update the communication protocol of the encoder in the solid-state memory conveniently, the servo driver supporting various encoder protocols provided by the invention further comprises an upper computer;

The upper computer is used for updating the encoder communication protocol stored in the solid-state memory.

The invention not only supports the encoder of the asynchronous communication protocol, but also supports the encoder of the synchronous communication protocol, and expands the adaptability of the driver.

Meanwhile, the invention can also realize the online upgrade of the FPGA. Through switching of Flash, the reliability of FPGA online upgrade can be improved.

The advantages of the present invention will be further described based on the operating principle of the servo driver supporting various encoder protocols provided by the present invention.

As shown in fig. 2, based on the technical scheme provided by the invention, the DSP has the functions of servo driving, upper communication, fault detection, interaction with the FPGA, AD sampling and the like. After the FPGA analyzes the encoder data, the encoder data is uploaded to the DSP for servo control.

The internal functional modules of the FPGA are shown in fig. 5, and comprise an encoder data analysis module, a DSP data interaction module and other auxiliary functional modules.

Flash1 and Flash2 respectively store programs supporting different encoders, and it is assumed that the encoder types supported by Flash1 include A, B, C and D, and the encoder types supported by Flash2 include E, F and G. When sel=0 in the system default DSP, flash1 is selected as the default boot Flash for the FPGA, and the driver default supports encoder types A, B, C and D, as shown in fig. 3.

When the system is powered on, if the driver adopts default servo parameters, the DSP outputs SEL=0 according to the servo parameters of the driver, namely, the Flash1 chip selection signal/CE is valid at the moment. And simultaneously outputting nCFG low-level pulse signals, and reading program data from the Flash connected by the FPGA at the same time, and completing self-starting. After the FPGA has completed initialization, the Init signal goes high. After the DSP receives the Init high level, the FPGA is considered to enter a normal working mode, and the external encoder data can be analyzed. The types of encoders supported by the driver at this time are encoder a, encoder B, encoder C, and encoder D.

When the encoders of different communication protocols need to be replaced, the type of encoder of the servo parameters is modified only by the upper computer. And the DSP judges whether the FPGA is switched from the Flash1 to the program in the Flash2 according to the currently set servo parameters. Therefore, sel=0 is maintained if only one of A, B, C and D encoder types needs to be replaced, and the SEL signal in DSP is changed to sel=1 if the program in Flash2 needs to be replaced. After the FPGA has completed restarting, then the encoder types are encoder E, encoder F, and encoder G can be supported. The system functions when Flash2 is selected are seen in fig. 4.

When the Flash is determined to be started, the FPGA works normally, the data analysis module analyzes the data of the supported encoder, and the real-time position value is uploaded to the DSP through SPI communication.

When the FPGA program needs to be upgraded online, the DSP selects Flash chip select signals/CEs according to the encoder type set value.

Assuming that the current encoder type is set to a and the customer site needs to replace the encoder to type B, the DSP output keeps sel=0 to select Flash1 (① in fig. 1), and the FPGA receives the upgrade data via the SPI bus and writes to the corresponding Flash1. The DSP monitors the FPGA upgrade status and outputs nCFG control signals (② in fig. 1) to initiate reconfiguration of the FPGA. After the FPGA completes reconfiguration, the FPGA enters an initialization stage, and all interfaces are high-resistance. After the initialization of the FPGA is finished, an initialization completion signal init_done (③ in fig. 1) is output and is self-started, and the user mode can be entered to complete the design function.

In the upgrading process, only one piece of Flash data is operated, so that the other piece of Flash data is ensured to be unchanged. Therefore, the driver can be ensured to be capable of ensuring that the FPGA can be started correctly from Flash at any time. The method for upgrading the FPGA in the technical solution provided in the present invention is the prior art, and specifically refer to the patent document CN110737452a, which is not described herein.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

1. Multiple encoder protocols can be supported without increasing servo driver hardware and structural complexity.

2. The hardware design is simple, and synchronous communication protocol and asynchronous communication protocol encoders can be supported simultaneously by only adopting one FPGA and one encoder interface. Meanwhile, the online upgrading function can be completed, and the adaptability and the reliability of the driver are improved.

3. The FPGA firmware is simple to develop, and has the characteristics of low system cost and short development period.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The principles and embodiments of the present invention have been described herein with reference to specific examples, which are intended to facilitate an understanding of the principles and concepts of the invention and are to be varied in scope and detail by persons of ordinary skill in the art based on the teachings herein. In view of the foregoing, this description should not be construed as limiting the invention.

Claims

1. A servo driver supporting multiple encoder protocols, characterized by comprising: an encoder interface, an FPGA, a DSP, a solid-state memory and a host computer;

The encoder interface is connected to the FPGA; the FPGA is connected to the DSP and the solid-state memory respectively; the DSP is connected to the solid-state memory;

The solid-state memory is used to store FPGA program data of multiple encoder communication protocols, and the encoder communication protocols corresponding to the program data stored in the solid-state memory are all different; the encoder interface is used to connect the encoder to be driven; the DSP is used to generate a chip select signal according to the servo parameters to turn on or off the solid-state memory; the FPGA is used to read the program data stored in the solid-state memory, to determine the connected encoder communication protocol according to the servo parameters of the driver, to parse the transmission data of the encoder to be driven through the encoder data parsing function module, and to upload it to the DSP through the DSP data interaction function module; the DSP is used to perform data interaction with the FPGA through the FPGA interaction function module, and to update the servo drive data in real time according to the position data uploaded by the FPGA to drive the motor to run smoothly;

The host computer is used to send a command to the DSP to update the encoder communication program data stored in the solid-state memory, thereby realizing the online upgrade of the FPGA;

The FPGA is connected to the DSP via the SPI interface, the nCFG interface and the Init interface; the SEL interface of the DSP is connected to the /CE interface of the solid-state memory via a switch selector; the nCSC interface of the FPGA is connected to the /CE interface of the solid-state memory;

The solid-state memory comprises: a first solid-state memory and a second solid-state memory;

The /CE interface of the first solid-state memory and the /CE interface of the second solid-state memory are both connected to the SEL interface of the DSP through a switch selection device; the data output interface of the first solid-state memory and the data output interface of the second solid-state memory are both connected to the nCSC interface of the FPGA through a switch selection device;

When the system is powered on, if the driver uses the default servo parameters, the DSP outputs SEL=0 according to the driver's servo parameters, that is, the first solid-state memory chip select signal /CE is valid; at the same time, it outputs a low-level pulse signal of nCFG, and the FPGA reads the program data from the solid-state memory connected at this time and completes self-starting; when the FPGA completes initialization, the Init signal becomes a high level; after receiving the Init high level, the DSP considers that the FPGA has entered the normal working mode and parses the external encoder data; at this time, the encoder types supported by the driver are: encoder A, encoder B, encoder C and encoder D;

When replacing an encoder with a different communication protocol, the encoder type of the servo parameters is modified through the host computer; the DSP determines whether to switch the FPGA from the first solid-state memory to the program in the second solid-state memory based on the currently set servo parameters; if only one of the A, B, C and D encoder types is changed, SEL=0 is maintained; if it is replaced with the program of the second solid-state memory, the SEL signal in the DSP is changed to SEL=1; after the FPGA completes the restart, the supported encoder types are encoder E, encoder F and encoder G.

2. The servo driver supporting multiple encoder protocols according to claim 1, characterized in that the number of the FPGA is 1.

3 . The servo driver supporting multiple encoder protocols according to claim 1 , wherein the number of the encoder interface is 1.