CN111987894A

CN111987894A - Switching power converter, primary side controller and control method thereof

Info

Publication number: CN111987894A
Application number: CN202010400442.0A
Authority: CN
Inventors: J·赫罗姆恰克
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-05-22
Filing date: 2020-05-13
Publication date: 2020-11-24
Anticipated expiration: 2040-05-13
Also published as: CN111987894B

Abstract

The invention provides a switching power converter, a primary side controller and a control method thereof. The invention discloses a switching power converter, a primary side controller and a control method thereof. At least some example embodiments are methods of operating a switching power converter, comprising: operating, by the primary-side controller, the switching power converter at a first frequency set by a resistor coupled to a first pin of the primary-side controller; and sensing a synchronization signal applied to the first terminal of the primary side controller, the synchronization signal having a variable second frequency; and operating the switching power converter at the second frequency by the primary side controller.

Description

Switching power converter, primary side controller and control method thereof

Technical Field

The present application relates to the field of switching power converters, and more particularly to a switching power converter tracking an applied synchronization signal.

Background

The package of the integrated circuit encapsulates the integrated circuit and provides electrical connections to the encapsulated integrated circuit through pins or terminals that are electrically exposed outside the package. The number of terminals is limited for a particular package size, such as a low-profile integrated circuit (SOIC) having 16 terminals (i.e., SOIC-16). In some cases, terminals are omitted or not used for various reasons (e.g., physical separation between signals driven to or from the terminals to reduce crosstalk).

In the field of switching power converters, the controllers (e.g., primary side controller, secondary rectifier controller) used for switching power converters are in many cases packaged integrated circuits. However, for the setting and operation of the controller, many connections are made to the controller through the terminals. For example, the operating frequency of the switching power converter may be set by a resistor coupled to a terminal of the primary side controller. However, problems arise when additional information and/or signals need to be provided to the controller but no additional terminals are available.

Disclosure of Invention

At least one example embodiment is a method of operating a switching power converter, comprising: operating, by the primary-side controller, the switching power converter at a first frequency set by a resistor coupled to a first terminal of the primary-side controller; and sensing a synchronization signal applied to the first terminal of the primary side controller, the synchronization signal having a variable second frequency; and then operating the switching power converter at the second frequency by the primary side controller.

In this example method, operating the switching power converter at the second frequency may further include: the duty cycle of the main switching signal in each cycle of the synchronization signal is limited based on a parameter of the synchronization signal in a previous cycle of the synchronization signal. Limiting the duty cycle in each cycle of the synchronization signal may further include limiting the duty cycle of the main switching signal in each cycle of the synchronization signal based on an immediately previous cycle of the synchronization signal. Limiting the duty cycle in each cycle of the synchronization signal may further include limiting the duty cycle in each cycle of the main switching signal based on a period of the synchronization signal in an immediately preceding cycle.

In this example method, operating the switching power converter at the second frequency may further include: charging a first capacitor within the primary side controller during a first cycle of the synchronization signal; and setting a duty cycle limit of a drive signal driven to the drive terminal of the primary side controller in a second cycle of the synchronization signal, the setting transitioning beyond the voltage held on the first capacitor based on the second ramp signal. The example method may also include generating a second ramp signal in a second cycle by charging a third capacitor. The exemplary method may further comprise: during a first cycle of the synchronization signal, a duty cycle limit of the drive signal in the first cycle is set based on the first ramp signal transitioning beyond a voltage held on a second capacitor, the second capacitor being different from the first capacitor. The exemplary method may further comprise: charging a second capacitor within the primary side controller during a third cycle of the synchronization signal immediately prior to the first cycle; and in a first cycle of the synchronization signal, setting a duty cycle limit of the drive signal in the first cycle based on the first ramp signal transition exceeding the voltage held on the second capacitor. The example method may also include generating the first ramp signal in the first cycle by charging a third capacitor.

Another exemplary embodiment is a primary side controller for a switching power converter, the primary side controller comprising: a synchronization terminal and a drive terminal; a synchronization controller defining a synchronization input, a set output, and a reset output, the synchronization input coupled to the synchronization terminal; and drive logic defining a set input, a reset input and a drive output, the set input being coupled to the set output, the reset input being coupled to the reset output, and the drive output being coupled to the drive terminal, the drive logic being configured to drive a control input of the electrically controlled switch. The drive logic may be configured to assert the drive output in response to assertion of the set input, and the drive logic may be configured to de-assert the drive output in response to assertion of the reset input. The synchronization controller may be configured to: asserting a set input to the drive logic at a first frequency set by a direct current voltage (DC voltage) sensed by a synchronization controller on the synchronization terminal in the absence of a synchronization signal sensed on the synchronization terminal; sensing a synchronization signal applied to a synchronization terminal, the synchronization signal having a variable second frequency; asserting a set input to the drive logic at a second frequency in the presence of a synchronization signal on the synchronization terminal; and limiting the duty cycle in each cycle of the synchronization signal based on a parameter of the synchronization signal in a previous cycle.

In an exemplary primary side controller, the synchronization controller may further include: a current mirror defining a first mirrored output and a third mirrored output; a first sensing capacitor coupled to the first mirror output; a second sensing capacitor holding a voltage proportional to a period of a previous cycle of the synchronization signal; a ramp capacitor coupled to the third mirror output. During a first cycle of the synchronization signal, the synchronization controller may be configured to: charging a first sensing capacitor through the first mirrored output; charging a ramp capacitor through the third mirror output, the charging producing a ramp signal; the reset output is asserted when the magnitude of the first ramp signal passes through the magnitude of the voltage of the second sensing capacitor.

The synchronization controller may further include: a current mirror defining a second mirrored output; a first sensing capacitor holding a voltage proportional to a period of a first cycle of the synchronization signal; and a second sensing capacitor coupled to the second mirror output; a ramp capacitor coupled to the third mirror output. During a second cycle of the synchronization signal, the synchronization controller may be configured to: charging a second sensing capacitor through the second mirrored output; charging the ramp capacitor through the third mirror output, the charging generating a second ramp signal; the reset output is asserted when the magnitude of the second ramp signal passes through the magnitude of the voltage of the first sensing capacitor. The first cycle of the synchronization signal may be immediately before the second cycle of the synchronization signal.

In an exemplary primary side controller, the synchronization controller may further include: a current mirror defining a first mirrored output, a second mirrored output, and a third mirrored output; a first sensing capacitor coupled to the first mirror output through a first electrically controlled switch defining a control input; a second sensing capacitor coupled to the second mirror output through a second electrically controlled switch defining a control input; a ramp capacitor coupled to the third mirror output through a third electrically controlled switch defining a control input; a comparator defining a first comparison input, a second comparison input, and a comparison output, the first comparison input coupled to the ramp capacitor; a fourth electrically controlled switch defining a control input, the fourth electrically controlled switch coupled between the first sensing capacitor and the second comparison input; a fifth electrically controlled switch defining a control input, the fifth electrically controlled switch coupled between the second sensing capacitor and the second comparison input; and control logic defining a first control output coupled to the control input of the first electrically controlled switch, a second control output coupled to the control input of the second electrically controlled switch, a third control output coupled to the control input of the third electrically controlled switch, a fourth control output coupled to the control input of the fourth electrically controlled switch, a fifth control output coupled to the control input of the fifth electrically controlled switch, and control logic coupled to the synchronization input. The control logic may be configured to, in a first cycle of the synchronization signal: coupling a first sensing capacitor to the first mirror output through a first electrically controlled switch; the second sensing capacitor is coupled to the second comparison input through a fifth electrically controlled switch. And the control logic may be configured to, in a second cycle of the synchronization signal: coupling a second sensing capacitor to the second mirror output through a second electrically controlled switch; and coupling a second sensing capacitor to the second mirror output through a second electrically controlled switch.

In an example primary side controller, the drive logic may be configured to drive the gate and electrically control the switch in the form of a field effect transistor.

In an exemplary primary side controller, the synchronization signal may be at least one selected from the group consisting of: an AC signal; a pulse train; a pulse train having a non-zero average voltage.

Another exemplary embodiment is a switching power converter, comprising: a primary side; a secondary side; and a primary side controller. The primary side may include: a primary winding of a transformer; and a main electrically controlled switch defining a control input, the main electrically controlled switch configured to selectively couple the supply voltage to the primary winding of the transformer. The secondary side may include a secondary winding of a transformer and a rectifier coupled to the secondary winding. The primary side controller may include a synchronization terminal and a drive terminal coupled to a control input of the main power control switch. The primary-side controller may be configured to: asserting a drive terminal at a first frequency set by a direct current voltage (DC voltage) sensed on the synchronization terminal in the absence of the synchronization signal sensed on the synchronization terminal; sensing a synchronization signal applied to a synchronization terminal, the synchronization signal having a variable second frequency; driving a control input of the main electrical control switch at a second frequency in the presence of a synchronization signal on the synchronization terminal; and limiting the duty cycle in each cycle of the synchronization signal based on a parameter of the synchronization signal in a previous cycle.

In an exemplary switching power converter, the primary side controller may further include: a current mirror defining a first mirrored output and a third mirrored output; a first sensing capacitor coupled to the first mirror output; a second sensing capacitor holding a voltage proportional to a period of a previous cycle of the synchronization signal; and a ramp capacitor coupled to the third mirror output. During a first cycle of the synchronization signal, the primary side controller may be configured to: charging a first sensing capacitor through the first mirrored output; charging a ramp capacitor through the third mirror output, the charging generating a first ramp signal; the control input of the master electrical control switch is de-asserted when the magnitude of the first ramp signal crosses the magnitude of the voltage of the second sensing capacitor. The primary side controller may further include: a current mirror defining a second mirrored output; a first sensing capacitor holding a voltage proportional to a period of a first cycle of the synchronization signal; a second sensing capacitor coupled to the second mirror output; and a ramp capacitor coupled to the third mirror output. During a second cycle of the synchronization signal, the primary side controller may be configured to: charging a second sensing capacitor through the second mirrored output; charging the ramp capacitor through the third mirror output, the charging generating a second ramp signal; the control input of the master electrical control switch is de-asserted when the magnitude of the second ramp signal crosses the magnitude of the voltage of the first sensing capacitor. The first cycle of the synchronization signal may immediately precede the second cycle of the synchronization signal.

Drawings

For a detailed description of exemplary embodiments, reference will now be made to the accompanying drawings in which:

fig. 1 illustrates a circuit diagram of a switching power converter in accordance with at least some embodiments;

FIG. 2 illustrates a block diagram of the primary-side controller 126 in accordance with at least some embodiments;

FIG. 3 illustrates a block diagram of a synchronization controller in accordance with at least some embodiments;

FIG. 4 illustrates a partial block diagram, partial electrical schematic of a variable frequency controller in accordance with at least some embodiments; and is

FIG. 5 illustrates a method in accordance with at least some embodiments.

Definition of

Various terms are used to refer to particular system components. Different companies may refer to a component by different names-this document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus, these terms should be interpreted to mean "including, but not limited to …". Additionally, the term "coupled" or "couples" is intended to mean either an indirect connection or a direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

The terms "input" and "output" refer to electrical connections to electrical devices (whether stand-alone or as part of an integrated circuit) and should not be considered verbs requiring operation. For example, a differential amplifier (such as an operational amplifier) may have a first differential input and a second differential input, and these "inputs" are defined to the electrical connections of the operational amplifier and should not be understood as requiring signal inputs of the operational amplifier.

"assert" refers to changing the state of a Boolean signal. The boolean signal may be asserted as a high voltage or with a higher voltage, and the boolean signal may be asserted as a low voltage or with a lower voltage as appropriate by a circuit designer. Similarly, "deasserting" refers to changing the state of a boolean signal to a voltage level that is opposite the asserted state.

"period" with respect to a time associated with a periodic signal refers to a time duration between any two consistent characteristics of the periodic signal. For example, for a pulse signal comprising a series of pulses, the period may be the duration between two consecutive rising edges or two consecutive falling edges.

Detailed Description

The present application claims the benefit of U.S. provisional application No. 62/851,323 entitled "Adaptive Duty Cycle Limit" filed on 2019, 5, month 22. This provisional application is incorporated by reference as if reproduced in full below.

The following discussion is directed to various embodiments of the invention. While one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Example embodiments relate to methods and systems for controlling the switching frequency of a switching power converter. More particularly, exemplary embodiments relate to a primary side controller for a switching power converter, wherein the primary side controller senses a voltage and a signal applied to a terminal of the primary side controller, and controls a switching frequency of a main electric control switch based on the sensed voltage and signal. More specifically, the exemplary primary side controller may operate at a fixed frequency selected by a resistance of a terminal coupled to the primary side controller (e.g., by sensing a Direct Current (DC) voltage associated with a resistor), and may also operate at a synchronous frequency when a synchronization signal (e.g., an Alternating Current (AC) signal) is applied to the terminal. In other embodiments, the primary-side controller may limit the duty cycle in each cycle of the synchronization signal when operating at the synchronization frequency set by the synchronization signal. The present description now turns to an exemplary switching power converter.

Fig. 1 illustrates a circuit diagram of a switching power converter in accordance with at least some embodiments. In particular, switching power converter 100 includes a transformer 102 defining a primary winding 104 and a secondary winding 106. The transformer 102 conceptually forms a primary side 108 of the switching power converter 100 and a secondary side 110 of the switching power converter 100. The conceptual division between the primary side 108 and the secondary side 110 is an electrical concept, not necessarily a physical concept. In the exemplary switching power converter 100, the primary side 108 is electrically isolated from the secondary side 110 by the transformer 102, but need not be electrically isolated in all cases.

Turning to the primary side 108, the exemplary switching power converter 100 is arranged for forward operation and thus includes a high-side electrical control switch 112 and a low-side electrical control switch 114. In the exemplary system of fig. 1, the electrically controlled switches are shown as Field Effect Transistors (FETs), but any suitable electrically controlled switches (e.g., junction transistors, silicon controlled rectifiers) may be used. The electrical control switches are hereinafter referred to as a high-side FET 112 and a low-side FET 114.

The high-side FET 112 defines a drain 116, a source 118, and a gate 120. The drain 116 is coupled to the input voltage V_INThe positive electrode lead of (1). Source 118 is coupled to a first lead 122 of primary winding 104. The gate 120 is coupled to a high side drive terminal 124 of a primary side controller 126. The low-side FET 114 also defines a drain 128, a source 130, and a gate 132. The drain 128 is coupled to a second lead 134 of the primary winding 104. The source 130 is grounded on the primary side through a sense resistor 136.Gate 132 is coupled to low side drive terminal 138. The sense resistor 136 has a first lead coupled to the source 130 of the low side FET 114, and the first lead and the source 130 are coupled to a sense terminal 139 of the primary side controller 126. As the name implies, the sense resistor is used to sense the current flowing through the primary winding 104 when the low-side FET 114 is conducting.

The example primary side controller 126 also defines a synchronization terminal 140 and a feedback terminal 142. The exemplary feedback terminal 142 is coupled to the transistor side of the optocoupler 144, and the light emitting diode side of the optocoupler 144 is coupled to the output voltage V_OUT. The LED side of the optocoupler 144 to output voltage V_OUTThe proportional rate produces photons and the photons excite the base of the transistor side of the light coupler 144. Transistor-side conductivity and output voltage V of optocoupler_OUTAnd (4) in proportion. Thus, the primary side controller 126 receives the indicated output voltage V through the feedback terminal 142_OUTOf the signal of (1).

In the exemplary system, an external resistor 146 is coupled between the sync terminal 140 and ground on the primary side 108, and the value of the resistance sets the default operating frequency that the primary side controller 126 uses to control the switching of the high-side FET 112 and the low-side FET 114. To read the resistance of the external resistor 146, the primary side controller 126 may apply a current to the sync terminal 140 and read the DC voltage on the sync terminal 140 caused by the external resistor 146. The primary side controller 126 may thus set the operating frequency of the switching power converter 100 based on the sensed voltage. There will be additional terminals and connections to the primary side controller 126 (e.g., power supply, ground on the primary side), but such additional terminals and connections are not shown so as not to unduly complicate the drawing.

Turning now to the secondary side 110, in the exemplary system, a first lead 148 of the secondary winding 106 is coupled to an anode of a diode 150, and a second lead 152 of the secondary winding 106 is coupled to and defines a return or common on the secondary side 110. The cathode of the diode 150 is coupled to a first lead of an inductor 154, and a second lead of the inductor 154 defines an output voltage V_OUTIs connected to the positive electrode. Another diode 156 has a couplingAn anode of a second lead 152 to the secondary winding 106 and an anode coupled to a cathode of the diode 150. A capacitor 158 is coupled between the second lead of the inductor 154 and the second lead of the inductor 154. The capacitor 158 stores charge, smoothes the voltage and current provided by the secondary winding 106, and may also be used to provide energy during periods when no current is provided from the collapsed field of the secondary winding 106 or the inductor 154.

Still referring to fig. 1, the secondary side 110 also includes the LED side of the optocoupler 144. Specifically, the anode of the LED side of the optocoupler 144 is coupled to the output voltage V through a resistor 160_OUTThe positive electrode lead of (1). The cathode of the LED side of the optocoupler 144 is coupled to the common on the secondary side through a zener diode 162. Therefore, when the voltage V is output_OUTAbove a predetermined threshold set by zener diode 162, current flows through optocoupler 144 and thus provides voltage feedback to primary side controller 126.

In operation, the primary side controller 126 operates the switching power converter 100 at an initial frequency set by the external resistor 146. In particular, the primary side controller 126 drives the high side drive terminal 124 to render the high side FET 112 conductive and likewise drives the low side drive terminal 138 to render the low side FET 114 conductive. So that the current flows from the input voltage V_INThrough the high-side FET 112, through the primary winding 104, through the low-side FET 114, through the sense resistor 136, and then to ground on the primary side 108. The primary side controller 126 turns off the high side FET 112 and the low side FET 114 based on the current sensed through the sense terminal 139, or based on reaching a duty cycle limit. Additional circuitry (e.g., diodes, additional FETs), not specifically shown, may be used to account for the inductive effect of the primary winding 104. At a later time, the cycle is repeated based on the initial frequency. Thus, the FET and primary side controller 126 applies a time-varying voltage and a time-varying current to the primary winding 104, which generates a voltage and current on the secondary winding 106. The primary side 108 of fig. 1 shows two switch arrangements; however, the various exemplary methods and systems are not limited to two switching forward converters. The method and system may be applied to any arrangement for a forward converter on the primary side, such as a half bridge, a full bridge or an inductorInductor-capacitor (LLC) primary side devices. Furthermore, the example methods and systems are not limited to forward converters and may find application in any type of switching power converter, such as non-isolated converters and flyback power converters.

On the secondary side 110, the voltage generated by the secondary winding 106 (having the polarity shown by the dotted convention in fig. 1) generates a current that flows through the diode 150, charges the field associated with the inductor 154, and ultimately flows into the capacitor 158 and the output voltage V_OUT. Diode 156 is reverse biased when secondary winding 106 forward biases diode 150. When the voltage and current provided by the secondary winding 106 ceases in each switching cycle, the inductor 154 continues to provide current as the field around the inductor 154 collapses. Diode 156 (sometimes referred to as a freewheeling diode) provides a current path for the inductor current during field collapse of inductor 154. The secondary side 110 of fig. 1 shows a passive rectification and buck arrangement using an inductor 154; however, the various exemplary methods and systems are not limited to the precise secondary side 110 shown in FIG. 1. The methods and systems are applicable to any secondary side arrangement, including secondary sides using active rectification (e.g., FETs), and depending on the device and operation of the primary side 108, half-wave and full-wave rectification arrangements.

Still referring to fig. 1, while in some cases the switching power converter 100 may operate as a stand-alone converter, in other cases multiple switching power converters may be operated in parallel to meet the ampere requirements of the load. In this case, it may be beneficial to synchronize the operating frequencies of the various switching power converters. To achieve synchronization, the primary side controller 126 may receive a synchronization signal. If the package of the primary-side controller has a sufficient number of available terminals, the synchronization signal may be received on a dedicated terminal. However, difficulties arise if no additional terminal can be dedicated to receiving the synchronization signal. According to an exemplary embodiment, the primary side controller 126 is designed and configured to enable dual use of the terminals, and in particular, the sync terminals 140. That is, the exemplary primary-side controller 126 operates the switching power converter 100 at an initial frequency set by an external resistor 146 coupled to the synchronization terminal 140. However, the primary side controller 126 also monitors for the presence of a synchronization signal (e.g., an AC signal) applied to the synchronization terminal 140. When the primary side controller 126 senses or detects the synchronization signal, the primary side controller 126 operates the switching power converter 100 at the frequency and phase of the synchronization signal. In some cases, the synchronization signal has a variable frequency, and the primary side controller 126 tracks the frequency and phase of the synchronization signal when synchronized with the synchronization signal. In the exemplary switching power converter 100, the synchronization signal is applied to the synchronization terminal 140 through the capacitor 164. The capacitor 164 blocks the DC signal associated with the resistor 146 that sets the initial frequency.

Fig. 2 illustrates a block diagram of a primary-side controller 126 in accordance with at least some embodiments. In particular, fig. 2 shows the primary side controller 126 as a packaged semiconductor device or a packaged integrated circuit device having a plurality of externally accessible pins or terminals. Visible in fig. 2 are a high side drive terminal 124, a low side drive terminal 138, a sense terminal 139, a synchronization terminal 140 and a feedback terminal 142. Within the packaged device resides a semiconductor die 200 on which various circuits are monolithically fabricated. Although fig. 2 shows only a single semiconductor die 200, two or more semiconductor dies may be packaged together (i.e., a multi-chip module) to form the primary side controller 126.

The example primary side controller 126 defines a synchronization controller 202, drive logic 204, and current control logic 206. The synchronization controller 202 defines a synchronization input 208, a set output 210 and a reset output 212. The sync input 208 is coupled to the sync terminal 140. The drive logic 204 defines a set input 214, a reset input 216, a high drive output 218 and a low drive output 220. The setting input 214 is coupled to the setting output 210 of the synchronization controller 202. The reset input 216 is coupled to the reset output 212 of the synchronous controller 202 through a logical OR gate 222. High drive output 218 is coupled to high side drive terminal 124 and low drive output 220 is coupled to low side drive terminal 138. The drive logic 204 is configured to drive control signals to control inputs of the electrically controlled switches, and in particular, the drive logic 204 is configured to drive the

gates

120 and 132 of the high-side FET 112 and the low-side FET 114, respectively. Additionally, the drive logic 204 is configured to assert the high drive output 218 and assert the low drive output 220 in response to the assertion of the set input 214. In contrast, the drive logic 204 is configured to de-assert the high drive output 218 and de-assert the low drive output 220 in response to the assertion of the reset input 216.

The current control logic 206 defines a reset output 224, a sense input 226, and a feedback input 228. The sense input 226 is coupled to a sense terminal 139. Feedback input 228 is coupled to feedback terminal 142. The reset output 224 is coupled to the logic OR gate 222, and the logic output 230 of the logic OR gate 222 is coupled to the reset input 216 of the drive logic 204. In operation, during each cycle of the switching power converter 100 (fig. 1) (e.g., during the time period that the high-side FET 112 and the low-side FET 114 are conducting), the current control logic 206 monitors a signal indicative of the current in the primary winding through the sense terminal 139. When the signal indicative of current reaches or exceeds the predetermined threshold, the current control logic 206 asserts the reset output 224, which propagates to the reset input 216 of the drive logic 204. The predetermined threshold may be based on a signal indicative of the output voltage V sensed through the feedback terminal 142_OUTIs determined. I.e. when the output voltage V is_OUTWhen low, a predetermined threshold is increased. And conversely when the output voltage V is_OUTWhen high, the predetermined threshold is decreased. Thus, in normal operation, based on the output voltage V_OUTTo adjust the duty cycle of the signal applied to the gate of the FET on the primary side.

FIG. 3 illustrates a block diagram of a synchronization controller 202 in accordance with at least some embodiments. Specifically, the exemplary synchronization controller 202 includes a set multiplexer 300, a reset multiplexer 302, a variable frequency controller 304, and a fixed frequency controller 306. The multiplexers are each drawn as single pole, double throw switches for explanatory purposes; however, this should not be understood as requiring the presence of a physical switch. Functionality may be implemented in silicon using two electrically controlled switches (e.g., two complementary FETs). The exemplary set multiplexer 300 defines a common terminal 308, a first switch terminal 310, a second switch terminal 312, and a control input 314. The common terminal 308 is coupled to the setting output 210. The exemplary reset multiplexer 302 defines a common terminal 316, a first switch terminal 318, a second switch terminal 320, and a control terminal 322. The common terminal 316 is coupled to the reset output 212.

The fixed frequency controller 306 defines a sense input 324, a set output 326, and a reset output 328. The sense input 324 is coupled to the synchronization input 208. The set output 326 is coupled to the second switch terminal 312 of the set multiplexer 300 and the reset output 328 is coupled to the second switch terminal 320 of the reset multiplexer 302. In operation, the fixed frequency controller 306 senses the signal associated with the external resistor 146 (fig. 1) and drives the set signal to the drive logic 204 (fig. 2) at the frequency indicated by the external resistor 146. For example, the sense input 324 may be coupled to the pull-up resistor 331 to the internal supply voltage VD. Thus, pull-up resistor 331 and external resistor 146 form a voltage divider, and fixed frequency controller 306 senses the DC voltage generated by the voltage divider. Thus, the synchronous controller 202, and in particular the fixed frequency controller 306, is configured to assert a set input to the drive logic 204 at an initial frequency indicated by the sensed DC voltage. In non-fault operation, the drive logic 204 is reset by the current control logic 206 (fig. 2) based on a predetermined threshold current; however, the fixed frequency controller 306 may also provide a reset signal via a reset output 328 to ensure that a fault condition (e.g., a short circuit output voltage V) is present_OUT) The duty cycle limit is met. For example, if the switching power converter operates as a two-switch forward converter, the duty cycle of the drive signal applied to the FET on the primary side may be limited to 50%.

Still referring to fig. 3, the example variable frequency controller 304 defines a sense input 330, a set output 332, a control output 334, and a reset output 336. The sense input 330 is coupled to the sync input 208 through a DC blocking capacitor 338. The set output 332 is coupled to the first switch terminal 310 of the set multiplexer 300. The control output 334 is coupled to the control input 314 of the set multiplexer 300, and the control output 334 is also coupled to the control terminal 322 of the reset multiplexer 302. The reset output 336 is coupled to the first switch terminal 318 of the reset multiplexer 302. In operation, the fixed frequency controller 306 initially senses the DC voltage associated with the external resistor 146 (fig. 1) and asserts a set input to the drive logic 204 (fig. 2) at an initial frequency set by the DC voltage. At the same time, the variable frequency controller 304 monitors the AC signal of the synchronization input 208 as a synchronization signal, wherein the synchronization signal may have a variable frequency. When the variable frequency controller senses a synchronization signal applied to the synchronization terminal 140 (fig. 1), the variable frequency controller 304 takes over from the fixed frequency controller 306. In the exemplary system, when the variable frequency controller 304 senses the synchronization signal, the variable frequency controller 304 asserts the control output 334. Asserting the control output 334 changes the switch positions of the set and reset

multiplexers

300 and 302 so that the set and reset signals applied to the set and reset

outputs

210 and 212, respectively, are provided by the variable frequency controller 304 instead of the fixed frequency controller 306. Thus, the variable frequency controller 304 asserts the set input 214 to the drive logic 204 (fig. 2) at the frequency indicated by the synchronization signal in the presence of the synchronization signal on the synchronization terminal 140.

Also, in non-fault operation, the drive logic 204 (fig. 2) is reset by the current control logic 206 (fig. 2) based on a predetermined threshold current; however, the variable frequency controller 304 may also provide a reset signal via the reset output 336 to ensure that the duty cycle limit is met during fault operation (e.g., limit the duty cycle of the drive signal applied to the FET to 50%).

Fig. 4 illustrates a partial block diagram, partial electrical schematic, of a variable frequency controller 304 in accordance with at least some embodiments. In particular, the variable frequency controller includes a schmitt trigger buffer 400, a current mirror circuit 402, a comparator 404, switch control logic 406, and a series of capacitors and switches to be addressed in sequence. The exemplary schmitt trigger buffer 400 defines a buffer input 408 coupled to the sense input 330 and a buffer output 410. The buffer output 410 is coupled to the set output 332 and to the switch control logic 406. Schmitt trigger buffer 400 provides a snap action change of state to reduce noise that may be associated with the synchronization signal; however, schmitt trigger buffers are not strictly required, and other non-schmitt trigger buffers may also be used.

The exemplary current mirror circuit 402 includes a current source 412 coupled to a series of transistors and, in the exemplary system, a series of FETs. The primary FET 413 is coupled to a current source 412 and a series of

secondary FETs

414, 416 and 418 define a first mirrored output 420, a second mirrored output 422 and a third mirrored output 424, respectively. Thus, the first mirror output 420 generates a mirror current proportional to the current of the current source 412. The second mirror output 422 produces a mirror current that is proportional to the current of the current source 412. The third mirror output 424 generates a mirror current proportional to the current of the current source 412. In some cases, each mirror current is proportional to the current flowing through current source 412 by 1: 1; however, in other cases, the mirror current may be greater or less than the current flowing through the current source 412 at the discretion of the circuit designer. When a larger image current is desired, the dimensions (e.g., width and length) of the secondary FET 414-418 are selected to be larger than the dimensions (e.g., width and length) of the primary FET 413. Conversely, when less mirror current is required, the size of the

secondary FET

414 and 418 is selected to be smaller than the size of the primary FET 413.

The first mirror output 420 is coupled to a sensing capacitor 426 through an electrically controlled switch 428, which is illustratively depicted as a single pole, single throw switch. The switch, shown as a single pole single throw switch, may take any suitable form (e.g., FET, junction transistor, silicon controlled rectifier). Thus, electrically controlled switch 428 is hereinafter referred to as "switch 428". The switch 428 may take any suitable form, such as a transistor (e.g., a FET). Switch 428 defines a control input 430. The first mirror output 420 is coupled to a first terminal of a switch 428, and a second terminal of the switch 428 is coupled to a first lead of a sensing capacitor 426. The second lead of the sensing capacitor 426 is connected to ground or to the common terminal of the primary side controller. A shorting electrical control switch 432 (hereinafter "shorting switch 432") is coupled in parallel with the sensing capacitor 426. The shorting switch 432 defines a control input 434. As will be discussed in more detail below, switch 428 is periodically closed to charge sensing capacitor 426, and shorting switch 432 is periodically closed to discharge sensing capacitor 426.

Still referring to fig. 4, the second mirrored output 422 is coupled to the sensing capacitor 436 through an electrically controlled switch 438 (hereinafter "switch 438"). The switch 438 defines a control input 440. The second mirror output 422 is coupled to a first terminal of a switch 438, and a second terminal of the switch 438 is coupled to a first lead of a sense capacitor 436. The second lead of the sensing capacitor 436 is connected to ground or to a common terminal of the primary side controller. A short circuit electrical control switch 442 (hereinafter "short circuit switch 442") is coupled in parallel with the sensing capacitor 436. Shorting switch 442 defines a control input 444. As will be discussed in more detail below, the switch 438 is periodically closed to charge the sensing capacitor 436, and the shorting switch 442 is periodically closed to discharge the sensing capacitor 426.

The third mirror output 424 is coupled to a ramp capacitor 446 through an electrically controlled switch 448 (hereinafter "switch 448"). The switch 448 defines a control input 450. The third mirror output 424 is coupled to a first terminal of a switch 448, and a second terminal of the switch 448 is coupled to a first lead of a ramp capacitor 446. The second lead of the ramp capacitor 446 is connected to ground or to the common terminal of the primary side controller. A short circuit electric control switch 452 (hereinafter referred to as "short circuit switch 452") is coupled in parallel with the ramp capacitor 446. The shorting switch 452 defines a control input 454. As will be discussed in more detail below, the switch 448 is periodically closed to charge the ramp capacitor 446, and the shorting switch 452 is periodically closed to discharge the ramp capacitor 446.

The comparator 404 defines a non-inverting input 456, an inverting input 458, and a comparator output 460. The non-inverting input 456 is coupled to the first lead of the ramp capacitor 446 so that the comparator 404 receives the ramp signal in the form of a voltage as a function of the time accumulated on the ramp capacitor 446. The comparator output 460 is coupled to the reset output 336. For the inverting input 458, the inverting input 458 is selectively coupled to either the sense capacitor 426 or the sense capacitor 436. In particular, the example variable frequency controller 304 (and thus the synchronization controller 202) also includes an electrically controlled switch 462 (hereinafter "switch 462") and an electrically controlled switch 464 (hereinafter "switch 464"). Switch 462 has a first terminal coupled to the first lead of sensing capacitor 436, and a second terminal coupled to inverting input 458 of comparator 404. Switch 462 also defines a control input 466. Switch 464 has a first terminal coupled to the first lead of sensing capacitor 426 and a second terminal coupled to inverting input 458 of comparator 404. Switch 464 also defines a control input 468. Thus, by operation of the switch 462 and the switch 464, the variable frequency controller 304 selectively couples the voltage held on the sensing capacitor 426 to the inverting input 458 or couples the voltage held on the sensing capacitor 436 to the inverting input 458.

Still referring to FIG. 4, the switch control logic 406 defines a synchronization input 470 and eight

switch control outputs

472 and 488. The synchronization input 470 is coupled to the buffer output 410. The switch control output 472 is coupled to the control input 430 of the switch 428. The switch control output 474 is coupled to the control input 434 of the switch 432. The switch control output 476 is coupled to the control input 440 of the switch 438. The switch control output 478 is coupled to the control input 444 of the switch 442. The switch control output 480 is coupled to the control input 450 of the switch 448. The switch control output 482 is coupled to the control input 454 of the switch 452. The switch control output 484 is coupled to the control input 466 of the switch 462. The switch control output 486 is coupled to the control input 468 of the switch 464. The switch control output 488 is coupled to the control output 334. Thus, the switch control logic 406 selectively controls all switches in the variable frequency controller 304, and also selectively controls the operation of the set multiplexer 300 (fig. 3) and the reset multiplexer 302 (see also fig. 3) through the switch control output 488.

In operation, the synchronization controller 202, and in particular the variable frequency controller 304, is configured to sense a synchronization signal applied to the synchronization terminal 140 (fig. 1) through the sense input 330 and the schmitt trigger buffer 400. More specifically, the switch control logic 406 senses the presence of a synchronization signal, which may have a frequency that is variable and different from the initial frequency. In the exemplary system, when the synchronization signal is detected, the switch control logic 406 asserts the switch control output 488 to transmit frequency control to the variable frequency controller 304. Once control is transferred to the variable frequency controller 304, the exemplary system asserts a set input to the drive logic 204 at the frequency of the synchronization signal. In particular, in the exemplary system, set output 332 is asserted by schmitt trigger buffer 400 after each assertion of the synchronization signal applied to schmitt trigger buffer 400. The assertion setting output 332 asserts the setting output 210 (fig. 2) of the synchronization controller 202, and thus asserts the setting input 214 (fig. 2) of the drive logic 204.

As described above, in non-fault operation, when the main current reaches a predetermined threshold, the drive logic 204 (fig. 2) is reset by the current control logic 206 (fig. 2). Determining and limiting the duty cycle is a straightforward effort when operating at a fixed initial frequency. However, when tracking a synchronization signal that may have a variable frequency (e.g., from 50 khz to 1 mhz), calculating a duty cycle limit based on an expected period of current cycling of the synchronization signal is not reliable. In other words, determining or calculating the duty cycle before the entire period of the cycle is completed is not reliable, as the duty cycle is defined by the ratio of the asserted time to the period over which the cycle is completed.

Exemplary embodiments solve the duty cycle problem by limiting the duty cycle in each cycle of the synchronization signal based on the parameters of the synchronization signal in the previous cycle. In one exemplary case, the duty cycle is limited in each cycle of the synchronization signal based on a parameter of the synchronization signal in an immediately preceding cycle of the synchronization signal. In one case, the duty cycle is limited in each cycle of the synchronization signal based on the period of the synchronization signal in the immediately preceding cycle.

Consider an arbitrary cycle of the synchronization signal (e.g., an assertion time and immediately following a de-assertion time), referred to as a first cycle. According to an exemplary embodiment, during the first cycle, the sensing capacitor 426 is charged by the first mirror output 420 of the current mirror circuit 402. That is, in a first cycle, switch control logic 406 asserts control input 430 of switch 428 to render switch 428 conductive, and in a first cycle, switch control logic 406 de-asserts control input 434 of switch 432 to render switch 432 non-conductive. When the switch 428 is conductive, the current flowing out of the first mirror output 420 charges the sensing capacitor 426. In an exemplary case, the charging of the sensing capacitor 426 ends at the end of the first cycle (e.g., at the time the synchronization signal is again asserted, initiating an immediately subsequent second cycle). At the end of the first cycle, switch control logic 406 de-asserts control input 430 of switch 428, thereby rendering switch 428 non-conductive, and control input 434 of switch 432 remains de-asserted.

Consider now a second cycle after (e.g., immediately after) the first cycle. In an exemplary embodiment, the variable frequency controller 304 (and thus the synchronous controller 202) asserts the reset output 336 during the second cycle to implement the duty cycle limitation. In an exemplary case, the duty cycle limit of the second cycle is based on the period of the synchronization signal in the previous cycle, here the immediately previous cycle. Specifically, in the exemplary second cycle, the duty cycle limit is set based on the ramp signal and the voltage held on the sensing capacitor 426, where the voltage held on the sensing capacitor 426 indicates the period of the first cycle. The voltage of the ramp signal is compared to the voltage on the sense capacitor 426 and the reset output 336 is asserted when the voltage of the ramp signal transitions through the voltage on the sense capacitor 426. To achieve duty cycle limitation in the second cycle, the switch control logic 406 couples the voltage on the sensing capacitor 426 to the inverting input 458 of the comparator 404 by asserting the control input 468 to make the switch 464 conductive. Further, during the second cycle, the switch control logic 406 couples the ramp capacitor 446 to the third mirror output 424 by asserting the control input 450 of the switch 448, thereby causing the switch 448 to conduct. And in a second cycle, switch control logic 406 de-asserts control input 454 of switch 452 to render switch 452 non-conductive. When the switch 448 is conductive, the current flowing out of the third mirror output 424 charges the ramp capacitor 446, and the rising voltage on the ramp signal is the ramp signal. The comparator output 460 asserts the reset output 336 when the voltage of the ramp signal applied to the non-inverting input 456 transitions through the voltage on the sense capacitor 426 applied to the inverting input 458, thereby enabling duty cycle control. It should be noted that in non-fault operation, when reset output 336 is asserted, drive logic 204 (fig. 2) will have been reset by current control logic 206. However, in which the current control logic 206 is invoking excessive current (e.g., the output voltage V)_OUTShort circuit), the reset output 336 resets the drive logic 204 to prevent an overcurrent condition.

Consider now a third cycle after (e.g., immediately after) the second cycle. In the exemplary system, the sensing capacitor 426 is again used to generate a value indicative of the period of the third cycle. Thus, the example switch control logic 406: decoupling the sensing capacitor 426 from the comparator 404 by deasserting the control input 468 of the switch 464; the sensing capacitor 426 is then discharged by momentarily asserting the control input 434 of the switch 432; the system is then arranged as in the first cycle to charge the sensing capacitor 426 again.

Consider again the first cycle. To provide duty cycle limitation during the first cycle (and while the sensing capacitor 426 is being charged), the variable frequency controller 304 (and thus the synchronous controller 202) again asserts the reset output 336 to implement duty cycle limitation. In an exemplary case, the duty cycle limit for the first cycle is based on the period of the synchronization signal in the previous cycle, here the immediately previous cycle (referred to as the zero cycle). Specifically, in the exemplary first cycle, the duty cycle limit is set based on the ramp signal and the voltage held on the sense capacitor 436. The sensing capacitor 436 charges during the zero cycle, and the voltage held on the sensing capacitor 436 indicates the duration of the zero cycle. The ramp signal is generated during the first cycle and in this case compared to the voltage on the sense capacitor 436. Thus, during the exemplary first cycle, the reset output 336 is asserted when the ramp signal transitions through the voltage on the sense capacitor 436.

To achieve duty cycle limitation in the first cycle, the switch control logic 406 couples the voltage on the sense capacitor 436 to the inverting input 458 of the comparator 404 by asserting the control input 466 to make the switch 462 conductive. Further, during the first cycle, switch control logic 406 asserts control input 450 of switch 448 to make switch 448 conductive, and in the first cycle, switch control logic 406 de-asserts control input 454 of switch 452 to make switch 452 non-conductive. When the switch 448 is conductive, the current flowing out of the third mirror output 424 charges the ramp capacitor 446, thereby again generating a ramp signal. The comparator output 460 asserts the reset output 336 when the voltage of the ramp signal applied to the non-inverting input 456 transitions through the voltage on the sense capacitor 436 applied to the inverting input 458, thereby enabling duty cycle control in the exemplary first cycle. Also, in non-fault operation, the drive logic 204 will have been reset by the current control logic 206. However, in fault operation where the current control logic 206 calls for excessive current, the reset output 336 resets the drive logic 204 to prevent an overcurrent condition.

More abstractly described, during any particular period or cycle of the synchronization signal, charging one capacitor will indicate the voltage of the cycle period, the second capacitor holds a voltage indicating the period of the previous cycle, and the voltage indicating the period of the previous cycle is compared to the ramp signal (recreated in each cycle) to drive the reset output 336 to implement the duty cycle limitation. During (e.g., immediately after) the subsequent cycle, the effect of the sensing capacitor is reversed and one capacitor is charged again with a voltage that would indicate the period of the current cycle, the second capacitor holds a voltage that indicates the period of the previous cycle, and the voltage that indicates the period of the previous cycle is compared to the ramp signal (recreated in each cycle) to drive the reset output 336 to achieve the duty cycle limit.

Prior to charging any particular capacitor, switch control logic 406 discharges the capacitor by temporarily or momentarily asserting the control inputs of the capacitor's shorting switch (e.g., shorting switch 432 for sensing capacitor 426, shorting switch 442 for sensing capacitor 436, and shorting switch 452 for ramping capacitor 446). The ramp capacitor 446 then discharges every cycle of the synchronization signal, while each sense capacitor 426/436 alternately discharges every other cycle.

The exemplary variable frequency controller 304 has three capacitors operable as described above. However, implementation should not be construed as limited to only three capacitors. For example, if the rate of discharge of any capacitor limits the speed of operation, the capacitors can be duplicated such that during any particular cycle, one set of capacitors is discharging while another set of capacitors is charging and/or used as a reference.

The switch control logic 406 may take any suitable form. For example, the switch control logic may be combinational logic circuitry, combinational logic circuitry implementing a state machine, a processor core and embedded software, or any suitable combination of devices and circuitry to implement control of the various control outputs.

FIG. 5 illustrates a method in accordance with at least some embodiments. Specifically, the method starts (block 500) and includes: asserting a set input to drive logic of the primary side controller, asserting at a first frequency set by a DC voltage sensed by a synchronous controller of the primary side controller, sensing through a synchronous terminal and in the absence of a synchronous signal sensed on the synchronous terminal (block 502); sensing, by the primary side controller, a synchronization signal applied to the synchronization terminal, the synchronization signal having a variable second frequency (block 504); then asserting, by the primary side controller, a set input to the drive logic at a second frequency in the presence of the synchronization signal on the synchronization terminal (block 506); and limiting a duty cycle in each cycle of the synchronization signal based on a parameter of the synchronization signal in a previous cycle (block 508). Thereafter, the method ends (block 510), possibly immediately restarting.

Many of the electrical connections in the figures are shown without direct coupling of intervening devices, but are not so explicitly described in the description above. However, for electrical connections shown in the figures without intervening devices, this paragraph should serve as antecedent basis for the claims to refer to any electrical connection as "directly coupled".

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the synchronization signal may take any suitable form, such as an AC signal, a pulse train, and/or a pulse train having a non-zero average voltage. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. A method of operating a switching power converter, comprising:

operating, by a primary side controller, a switching power converter at a first frequency set by a resistor coupled to a first terminal of the primary side controller; and

sensing a synchronization signal applied to the first terminal of the primary side controller, the synchronization signal having a variable second frequency; and then

Operating, by the primary-side controller, the switching power converter at the second frequency.

2. The method of claim 1, wherein operating the switching power converter at the second frequency further comprises limiting a duty cycle of a main switching signal in each cycle of the synchronization signal based on a parameter of the synchronization signal in a previous cycle of the synchronization signal.

3. The method of claim 1, wherein operating the switching power converter at the second frequency further comprises:

charging a first capacitor within the primary side controller during a first cycle of the synchronization signal; and

setting a duty cycle limit of a drive signal driven to a drive terminal of the primary side controller in a second cycle of the synchronization signal, the setting transitioning beyond a voltage held on the first capacitor based on a second ramp signal.

4. The method of claim 3, further comprising setting a duty cycle limit of the drive signal in the first cycle based on a first ramp signal transition exceeding a voltage held on a second capacitor during the first cycle of the synchronization signal, the second capacitor being different from the first capacitor.

5. The method of claim 4, further comprising:

charging the second capacitor within the primary side controller during a third cycle of the synchronization signal immediately prior to the first cycle; and

setting a duty cycle limit of the drive signal in the first cycle based on the first ramp signal transitioning beyond the voltage held on the second capacitor in the first cycle of the synchronization signal.

6. A primary side controller for a switching power converter, the primary side controller comprising:

a synchronization terminal and a drive terminal;

a synchronization controller defining a synchronization input, a set output, and a reset output, the synchronization input coupled to the synchronization terminal;

drive logic defining a set input, a reset input, and a drive output, the set input coupled to the set output, the reset input coupled to the reset output, and the drive output coupled to the drive terminal, the drive logic configured to drive a control input of an electrically controlled switch;

the drive logic is configured to assert the drive output in response to assertion of the set input, and the drive logic is configured to de-assert the drive output in response to assertion of the reset input;

the synchronization controller is configured to:

asserting the set input to the drive logic at a first frequency set by a direct current voltage (DC voltage) sensed on the synchronization terminal by the synchronization controller in the absence of a synchronization signal sensed on the synchronization terminal;

sensing a synchronization signal applied to the synchronization terminal, the synchronization signal having a variable second frequency;

asserting the set input to the drive logic at the second frequency in the presence of the synchronization signal on the synchronization terminal; and

limiting a duty cycle in each cycle of the synchronization signal based on a parameter of the synchronization signal in a previous cycle.

7. The primary-side controller of claim 6, wherein the synchronous controller further comprises:

a current mirror defining a first mirrored output and a third mirrored output;

a first sensing capacitor coupled to the first mirror output;

a second sensing capacitor holding a voltage proportional to a period of a previous cycle of the synchronization signal;

a ramp capacitor coupled to the third mirror output;

during a first cycle of the synchronization signal, the synchronization controller is configured to:

charging the first sensing capacitor through the first mirrored output;

charging the ramp capacitor through the third mirrored output, the charging producing a first ramp signal;

asserting the reset output when a magnitude of the first ramp signal crosses a magnitude of the voltage of the second sensing capacitor.

8. The primary-side controller of claim 7, wherein the synchronous controller further comprises:

the current mirror defining a second mirrored output;

the first sensing capacitor holding a voltage proportional to a period of the first cycle of the synchronization signal;

the second sensing capacitor coupled to the second mirror output;

the ramp capacitor coupled to the third mirror output;

during a second cycle of the synchronization signal, the synchronization controller is configured to:

charging the second sensing capacitor through the second mirrored output;

charging the ramp capacitor through the third mirrored output, the charging producing a second ramp signal;

asserting the reset output when a magnitude of the second ramp signal crosses a magnitude of the voltage of the first sensing capacitor.

9. The primary-side controller of claim 6, wherein the synchronous controller further comprises:

a current mirror defining a first mirrored output, a second mirrored output, and a third mirrored output;

a first sensing capacitor coupled to the first mirror output through a first electrically controlled switch defining a control input;

a second sensing capacitor coupled to the second mirror output through a second electrically controlled switch defining a control input;

a ramp capacitor coupled to the third mirror output through a third electrically controlled switch defining a control input;

a comparator defining a first comparison input, a second comparison input, and a comparison output, the first comparison input coupled to the ramp capacitor;

a fourth electrically controlled switch defining a control input, the fourth electrically controlled switch coupled between the first sensing capacitor and the second comparison input;

a fifth electrically controlled switch defining a control input, the fifth electrically controlled switch coupled between the second sensing capacitor and the second comparison input;

control logic defining a first control output coupled to the control input of the first electrically controlled switch, a second control output coupled to the control input of the second electrically controlled switch, a third control output coupled to the control input of the third electrically controlled switch, a fourth control output coupled to the control input of the fourth electrically controlled switch, a fifth control output coupled to the control input of the fifth electrically controlled switch, and the control logic coupled to the synchronization input;

the control logic is configured to, in a first cycle of the synchronization signal:

coupling the first sensing capacitor to the first mirror output through the first electrically controlled switch;

coupling the second sensing capacitor to the second comparison input through the fifth electrically controlled switch; the control logic is configured to, in a second cycle of the synchronization signal:

coupling the second sensing capacitor to the second mirror output through the second electrically controlled switch; and

coupling the second sensing capacitor to the second mirror output through the second electrically controlled switch.

10. A switching power converter comprising:

a primary side, the primary side comprising:

a primary winding of a transformer;

a main electrical control switch defining a control input, the main electrical control switch configured to selectively couple a supply voltage to the primary winding of the transformer;

a secondary side comprising a secondary winding of the transformer and a rectifier coupled to the secondary winding;

a primary side controller comprising a synchronization terminal and a drive terminal coupled to the control input of the main electrical control switch;

the primary side controller is configured to:

asserting the drive terminal at a first frequency set by a direct current voltage (DC voltage) sensed on the synchronization terminal in the absence of a synchronization signal sensed on the synchronization terminal;

driving the control input of the main electrical control switch at the second frequency in the presence of the synchronization signal on the synchronization terminal; and

11. The switching power converter of claim 10, wherein the primary side controller further comprises:

a current mirror defining a first mirrored output and a third mirrored output;

a first sensing capacitor coupled to the first mirror output;

a ramp capacitor coupled to the third mirror output;

during a first cycle of the synchronization signal, the primary side controller is configured to:

charging the first sensing capacitor through the first mirrored output;

de-asserting the control input of the master electrical control switch when the magnitude of the first ramp signal crosses the magnitude of the voltage of the second sensing capacitor.

12. The switching power converter of claim 11, wherein the primary side controller further comprises:

the current mirror defining a second mirrored output;

the second sensing capacitor coupled to the second mirror output;

the ramp capacitor coupled to the third mirror output;

during a second cycle of the synchronization signal, the primary side controller is configured to:

charging the second sensing capacitor through the second mirrored output;

de-asserting the control input of the master electrical control switch when a magnitude of the second ramp signal crosses a magnitude of the voltage of the first sensing capacitor.