CN111987165A - Method for manufacturing lateral double-diffused transistor - Google Patents

Abstract

The present application provides a method for manufacturing a lateral double diffused transistor, comprising: forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; and etching the gate conductor layer and the gate electrode in the source region The oxide layer is implanted to form the body region; the first type of implantation region is formed by obliquely implanting the photoresist as a mask in the body region; the first barrier layer is formed on the surface of the gate conductor layer and the body region; forming a second type implantation region between the first type implantation regions; and partially etching the first barrier layer, exposing the second type implantation region and part of the first type implantation region, forming a second barrier layer, and using the photoresist as a mask The oblique injection of the mold to form the first type of injection region, and then the step-by-step etching of the first barrier layer can not only reduce the size of the injection region, reduce the size of the device, effectively reduce the source-drain on-resistance, but also save raw materials and costs. The manufacturing process greatly simplifies the process steps and reduces the difficulty of operation.

Description

Manufacturing method of lateral double diffused transistor

technical field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a lateral double diffusion transistor.

Background technique

Lateral Double-Diffused MOSFET (LDMOS) transistor, as a kind of power field effect transistor, has been widely used due to its excellent characteristics such as good thermal stability, high gain and low thermal resistance. The main parameters to measure the performance of LDMOS are on-resistance and breakdown voltage. In practical applications, it is required to reduce the source-drain on-resistance Rdson as much as possible on the premise that the source-drain breakdown voltage off-BV is sufficiently high. The commonly used method is to reduce the surface electric field (Reduce surface electric field, RESURF) theory while continuously increasing the concentration of the drift region, so that it can be completely depleted. In addition, the size of the device also affects the on-resistance of the device. Due to the influence of the manufacturing process, the existing LDMOS has a larger size and a higher impedance.

FIG. 1d shows a schematic cross-sectional view of the source region of a conventional LDMOS. As shown in Fig. 1d, the formation of the LDMOS device includes: providing a substrate 101; forming a drift region 102 on the top of the substrate 101; forming a gate oxide layer 111 and a gate conductor layer 112 on the surface of the drift region 102, and etching to form an opening ; Implanting ions through the opening to form the body region 103; forming a barrier layer 121 on the sidewalls of the gate conductor layer 112 on both sides of the opening; using photoresist as a mask to form an N+ source region in the body region 103; removing the photolithography After the glue is applied, a new photoresist is used as a mask again to form a P+ body contact region in the body region 103; and a metal silicide layer 151 is used to cover the surfaces of the gate conductor layer 112 and the body region 103 respectively; A dielectric layer 161 is formed on the surface of the layer 151, and a through hole penetrating to the surface of the metal silicide layer 151 is etched for drawing out the source electrode. The formation of the N+ source region and the P+ body contact region in the source region is limited by the photolithography capability and has a large size. Taking the NLDMOS of 180nm process as an example, the width of each injection region is about 0.4um. On this basis, the on-resistance between the source and drain of the LDMOS device will be very large, which will reduce the performance of the device; and The steps of forming the structure in this process are relatively complicated, and the photoresist is used many times, which is not easy to operate.

Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present invention provides a manufacturing method of a lateral double diffused transistor, which can reduce the size of the multi-source region injection region, provide a more concise manufacturing process, save raw materials, reduce the size of the device, and effectively The reduced source-drain on-resistance is easy to implement.

According to a method for manufacturing a lateral double diffused transistor provided by the present invention, the method includes:

forming a drift region on top of the substrate;

A gate oxide layer and a gate conductor layer are sequentially stacked on the surface of the drift region, and the gate conductor layer defines a drain region and a source region separated from each other;

In the source region, the gate conductor layer and the gate oxide layer are etched through the patterned photoresist layer to form an opening, and ions are implanted in the drift region through the opening to form a body region;

Using the photoresist layer as a mask, ions are implanted obliquely at both ends of the top of the body region through the opening to form a first-type implantation region;

forming a first barrier layer on the surface of the gate conductor layer and the body region; and

Ions are implanted between the first type implantation regions at both ends of the body region through the first barrier layer to form second type implantation regions.

Preferably, the first barrier layer has a concave shape on the surface of the body region.

Preferably, after forming the second type implantation region, the method further comprises:

The first barrier layer is partially etched to expose the second type implantation region and a portion of the first type implantation region to form a second barrier layer.

Preferably, the width of the first type implantation region in the body region is defined according to the thickness of the photoresist layer.

Preferably, during oblique implantation, the included angle between the implantation direction and the normal line of the substrate surface is 20-60°.

Preferably, the width of the notch of the first barrier layer above the body region is equal to the distance between the first type implantation region, the second type implantation region and the two said implantation regions located at both ends of the body region The first type implanted regions are contiguous, respectively.

Preferably, the second barrier layer is formed in the opening and located on two sidewalls of the gate conductor layer on both sides of the opening and is two mutually independent spacers.

Preferably, the thickness of the first barrier layer formed on the two sidewalls of the gate conductor layer on both sides of the opening is greater than the thickness of the first barrier layer formed at the notch between the two sidewalls a thickness of the barrier layer.

Preferably, the first barrier layer is etched by a dry etching process.

Preferably, by adjusting isotropic and anisotropic etching rates, the surface of the gate conductor layer and the first barrier layer on the surface of the second-type implantation region are completely etched, while the two The first barrier layer on each sidewall is partially etched to form the second barrier layer.

Preferably, the manufacturing method further comprises:

forming a metal silicide layer between the second barrier layers and on the exposed surface of the gate conductor layer;

A dielectric layer is formed on the surfaces of the metal silicide layer and the second barrier layer, and a through hole is formed on the dielectric layer above the region corresponding to the second type of implantation region and is connected to the metal silicide layer ;

Metal contact leads to drain electrodes, gate electrodes and source electrodes are formed in the drain region, the surface of the gate conductor layer and the through holes, respectively.

Preferably, the first-type implanted region has a first doping type, the second-type implanted region has a second doping type, the first doping type is P-type, and the second doping type is N-type; or, the first doping type is N-type, and the second doping type is P-type.

The beneficial effects of the present invention are: the method for manufacturing a lateral double diffused transistor provided by the embodiment of the present invention includes forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; The gate conductor layer and the gate oxide layer are etched with the prepared photoresist, and implanted to form the body region; the first type of implantation region is formed by obliquely implanting the above-mentioned photoresist as a mask in the body region; A first barrier layer is formed on the surface of the region; and a second type implantation region is formed between the first type implantation regions through the first barrier layer. The first type of implantation region is formed by oblique implantation with photoresist as a mask, and the implantation width of the implantation region can be controlled, which can not only reduce the size of the implantation region, reduce the size of the device, effectively reduce the source-drain on-resistance, but also greatly save the process. The steps make the formation of the first type implantation region relatively simple, and reduce the difficulty of the process, thereby realizing the reduction of the on-resistance of the device while simplifying the supply process.

Further, the first barrier layer covers the body region and the gate conductor layer, and the opening position above the body region is in a concave shape, so that the semiconductor structure under the first barrier layer is protected, and when the second barrier layer is subsequently formed, The first barrier layer can also be directly etched, thereby saving raw materials, avoiding waste of barrier layer materials, and saving process steps and costs. The entire manufacturing process greatly simplifies the process steps and reduces the difficulty of operation.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

Figures 1a-1d respectively illustrate schematic cross-sectional structures of source regions at various stages in a conventional manufacturing method of a lateral double diffused transistor;

2 shows a schematic cross-sectional structure diagram of a lateral double diffused transistor in a source region according to an embodiment of the present invention;

3 shows a flowchart of a method for manufacturing a lateral double diffused transistor according to an embodiment of the present invention;

4a to 4h respectively illustrate schematic cross-sectional structures of source regions at various stages in a method for manufacturing a lateral double diffused transistor according to an embodiment of the present invention;

FIGS. 5 a to 5 f respectively illustrate schematic cross-sectional structures of source regions at various stages in a method for manufacturing a lateral double diffused transistor according to another embodiment of the present invention.

Detailed ways

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same or similar reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

In describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it can mean directly on the other layer, another region, or directly on the other layer or region Other layers or regions are also included between another layer and another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region. In order to describe the situation directly above another layer, another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In this application, "A is located directly in B" means that A is located in B, and A is directly adjacent to B, rather than A located in a doped region formed in B.

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

1a to 1d respectively show the cross-sectional structure diagrams of the source region at each stage in the traditional manufacturing method of the lateral double diffusion transistor. The following takes the N-type lateral double diffusion transistor as an example to briefly introduce the source end region of the lateral double diffusion transistor. manufacturing process and its shortcomings.

As shown in FIG. 1a, ion doping and diffusion are performed on the top of an N-type doped semiconductor substrate 101 such as a silicon substrate to form a drift region 102 with a certain ion concentration; The gate dielectric layer 111 and the polysilicon gate 112 form a mask layer, and then use the photoresist layer 113 coated on the polysilicon gate 112 as a barrier in the source region of the semiconductor device to perform the gate dielectric layer 111 and the polysilicon gate 112. Etching, ion doping and diffusion are performed through the etched opening to form a body region 103 with a certain ion concentration, and then the photoresist layer is removed to form a gate structure.

As shown in FIG. 1b, spacers 121 are formed on the sides of the gate structure. When forming the spacers 121, a deposition layer, such as a silicon dioxide layer, is first formed on the surfaces of the polysilicon gate 112 and the body region 103, and then a layer of silicon dioxide is formed on the surface of the polysilicon gate 112 and the body region 103. An etching process forms the sidewall spacers 121 . Then, a photoresist layer 114 is deposited on the surfaces of the polysilicon gate 112 and the body region 103 respectively, and the first doping type ion implantation is performed through the patterned photoresist layer 114 by using a photolithography process and a mask to form a source end region Two N+ implanted regions located below the sidewall spacers 121 and located at both ends of the top of the body region 103 . Since the photoresist 114 may slip on the surface of the body region 103 and the precision of the photolithography process itself is limited, in order to ensure that the N+ implantation region can achieve its function, the size of the region cannot be made very small. For example, in the NLDMOS of the 180nm process, the width of each injection region is about 0.4um.

As shown in FIG. 1c, after the implantation of the N+ source region is completed, the photoresist is removed, and then a photoresist layer 115 is deposited on the surface of the semiconductor structure again. An opening is left in the middle of the photoresist layer 115, and the width of the opening is The width of the gap between the above two N+ source regions. Then, ion implantation of the second doping type is performed on the top of the body region 103 through self-alignment using a photolithography process and a mask to form a P+ implantation region located between the two N+ source regions, that is, a body contact region. The N+ source region is N-type doping, the P+ body contact region is P-type doping, the N-type doping ions include but not limited to phosphorus ions or arsenic ions, and the P-type doping ions include but not limited to boron ions. Due to the same reason as above, the width of the P+ body contact region cannot be too small. In the above process, it is also about 0.4um. Then, the total width of the implantation region in the entire body region 103 reaches about 1.2um. The width of the region 103 cannot be too small, otherwise the performance of the device cannot be achieved.

As shown in FIG. 1d, the photoresist is removed, and a metal silicide layer 151 is formed on the surfaces of the polysilicon gate 112 and the body region 103, wherein the metal silicide layer 151 is a metal silicide (silicide), which is generally TiSi2 ( Then, a dielectric layer 161 is deposited, and the dielectric layer 161 is used to provide isolation and protection; then, a through hole 162 corresponding to the source region is formed on the dielectric layer 161 through etching to the surface of the metal silicide layer, By forming a metal contact to lead out the source electrode, the fabrication of the LDMOS is completed.

According to the above introduction, since both the N+ implantation region and the P+ implantation region in the LDMOS are formed by re-implantation through the photolithography process, the size of the formed implantation region is not too small due to the limitation of the photolithography capability. The width between the side walls 121 is about 1.2um. On the basis of this structure, the on-resistance between the source terminal and the drain terminal of the LDMOS device will be very large, thereby reducing the performance of the LDMOS device and affecting the application prospect of the LDMOS device. In addition, the manufacturing process of the LDMOS is relatively complicated, the steps are cumbersome, the operation is not easy, and the cost is relatively high.

Based on this, the present invention provides a manufacturing method of a lateral double diffused transistor. Through the improvement and optimization of the manufacturing process, the size of the source region of the multi-source end region can be reduced, the size of the formed device can be reduced, and the source-drain on-resistance can be effectively reduced , and can greatly reduce the process steps, simplify the process flow, and facilitate implementation.

FIG. 2 shows a schematic cross-sectional structure diagram of a lateral double diffused transistor in a source region according to an embodiment of the present invention.

Referring to FIG. 2 , an LDMOS device provided by an embodiment of the present invention has the same structure as the LDMOS introduced in FIG. 1d , and also includes: a substrate 201 with a first doping type, a substrate 201 with a second doping type of drift region 202 and a body region 203 having a first doping type, the drift region 202 being located in the substrate 201 and disposed around the body region 203, the body region 203 and the drift region 202 being formed in the substrate 201 for transport The electrons achieve electrical conduction, and the doping concentrations of the body region 203 and the drift region 202 are different to obtain different conduction performance; and the source region, the drain region, the gate structure, and the spacer 261 on the substrate 201 , a metal silicide layer 271 , a dielectric layer 281 and an opening 282 .

The source region is connected to the body region 203, the drain region is connected to the drift region 102, and is used to electrically connect the input of an external voltage; the gate structure includes a gate conductor layer 212 and a gate conductor layer 212 and a substrate located in the gate conductor layer 212. In the gate oxide layer 211 between 201, a spacer 261 is formed on the sidewall of the gate structure, a part of the metal silicide layer 271 covers the upper surface of the source region, and the other part covers the upper surface of the gate structure, and The source region has an N+ implantation region and a P+ implantation region that are independent of each other and do not contain each other. In this embodiment, the source region includes an N+ implantation region, a P+ implantation region, and an N+ implantation region that are adjacent to each other, and are formed through process control. The three regions have the same width.

The dielectric layer 281 is located on the surface of the metal silicide layer 271 , and has a through hole penetrating to the surface of the metal silicide layer 271 in the upper center of the source region, and the through hole is used for drawing out the source electrode.

In the lateral double diffused transistor device formed by the manufacturing method of the lateral double diffused transistor provided by the embodiment of the present invention, the N+ implantation region, the P+ implantation region and the N+ implantation region located in the source region are sequentially connected, independent of each other and not included. Compared with the prior art, the implanted region is not limited by the photolithography process capability, and the three implanted regions formed by it have smaller widths, that is, the spacing of the polysilicon layer in the gate structure above the source region is also smaller. Smaller source-drain on-resistance. The manufacturing method of the LDMOS of the present invention is described below with reference to the flow chart and the cross-sectional structure diagram of the process flow.

3 shows a flowchart of a method for manufacturing a lateral double diffused transistor according to an embodiment of the present invention; FIGS. 4a to 4h respectively show the source region at various stages in the method for manufacturing a lateral double diffused transistor according to an embodiment of the present invention Schematic diagram of the cross-sectional structure.

The manufacturing method of the lateral double diffusion transistor of the present application will be described below with reference to FIGS. 3-4h.

In step S110, a drift region is formed on top of the substrate.

As shown in FIG. 4a, ion doping and diffusion are performed in an N-type doped semiconductor substrate 201 such as a silicon substrate to form a drift region 202 of the first doping type with a certain ion concentration, and the formation of the drift region 202 is a conventional step , without special introduction.

In step S120, a gate oxide layer and a gate conductor layer stacked in sequence are formed on the surface of the drift region, and the gate conductor layer defines a drain region and a source region separated from each other.

As shown in FIG. 4b, a gate oxide layer 211 and a gate conductor layer 212 are sequentially deposited on the surface of the drift region 202 of the semiconductor substrate 201 to form a gate structure. The gate oxide layer 211 and the gate conductor layer 212 stacked in sequence define a mutual The isolated drain region and source region, only the structure of the source region is shown in the figure. The gate oxide layer 211 is, for example, a silicon oxide layer, and the gate conductor layer 212 is, for example, a polysilicon layer. And the formation process of the gate oxide layer 211 and the gate conductor layer 212 is a conventional process, which is not limited in detail here. The gate conductor layer 212 is formed by, for example, chemical vapor deposition. Meanwhile, from the perspective of solution implementation, other dielectric layers may be disposed between the gate oxide layer 211 and the gate conductor layer 212 , or another dielectric layer may be disposed under the gate oxide layer 211 or above the gate conductor layer 212 .

In step S130, the gate conductor layer and the gate oxide layer are etched through the patterned photoresist layer in the source region to form openings, and ions are implanted into the drift region through the openings to form a body region.

Still referring to FIG. 4 b , a photoresist layer 213 is arranged on the surface of the gate conductor layer 212 , and the coated photoresist layer 213 is used as a barrier, and the patterned photoresist layer 213 is used to sequentially adjust the gate conductor layer 212 and the gate electrode through the patterned photoresist layer 213 The oxide layer 211 is etched to form an opening into which the donor region 203 is implanted, through which ion doping and diffusion are performed to form a body region 203 of the second doping type with a certain ion concentration in the drift region 202, and then the light is removed. resist layer. Taking the LDMOS of 180nm process as an example, the width of the opening is about 0.6um, and the width of the opening is limited by the photoresist layer 213 . The opening with this width is set here because the width is sufficient to realize the implantation of the source region in the subsequent process.

In step S140, using the photoresist layer as a mask, ions are implanted obliquely at both ends of the top of the body region through the opening to form a first type implantation region.

As shown in Figure 4c, the photoresist layer 213 used in the previous step is retained, and at the opening, the photoresist layer 213 is used as a mask, and an oblique large-angle injection process is used to inject from the left and right sides to the top of the body region. Doping regions of the first type are implanted into the ends, and implanted along the directions indicated by the two arrows L1 and L2 in the figure to form two implanted regions of the first type. The first-type implantation region includes a first N+ implantation region and a second N+ implantation region, and the N+ implantation region is an N+ source region. In this step, the N+ implantation region on the left is implanted to the left from the direction of the arrow L1 on the right, and the N+ implantation region on the right is implanted to the right from the direction of the arrow L2 on the left. Using this process, the width of the N+ source region (N+ implantation region) is reduced to about 0.2um. In addition, the width of the first type implantation region in the body region 203 is defined according to the thickness of the photoresist layer 213 . By adjusting the thickness of the photoresist layer 213, an appropriate width of the N+ implantation region can be obtained. When the photoresist layer 213 of a certain thickness is used as a mask, an oblique implantation process is adopted, so that the dopant ions in the N+ implantation region can only diffuse in a certain fixed region pointed by the arrow, thereby ensuring a certain width. After the implantation is completed, the photoresist layer 213 is removed.

Further, during the oblique implantation, the included angle between the implantation direction and the normal line of the substrate surface is 20-60°, so that the width of the N+ implantation region is guaranteed.

In step S150, a first barrier layer is formed on the surface of the gate conductor layer and the body region. Further, the first barrier layer has a concave shape on the surface of the body region.

As shown in FIG. 4d, a first barrier layer 221 is formed on the surface of the gate conductor layer 212 and the body region 203. Specifically, a deposition layer is deposited on the surface of the semiconductor structure, and then an etching process is used to form the first barrier layer. For example, the first barrier layer 221 is formed by depositing a silicon oxide layer using a chemical vapor deposition process, and then using an etching process; or by forming a silicon oxide layer first, then forming a silicon nitride layer, and then using an etching process to form it. The cross-section of the formed structure in the source region is shown in Fig. 4d. For example, dry etching is used to etch the deposited layer to form the first barrier layer 221. The first barrier layer 221 has a concave shape on the surface of the body region 203, and its opening above the body region 203 has a funnel shape. diameter is wider. The thickness of the first barrier layer 221 on the two sidewalls of the gate conductor layer 212 above the body region 203 is relatively thick, while the portion of the surface of the body region 203 located between the two sidewalls is thinner, which is insufficient to block subsequent Implantation, that is, the thickness of the first barrier layer 221 formed on the two sidewalls of the gate conductor layer 212 on both sides of the opening is greater than the thickness of the first barrier layer 221 formed at the notch in the middle of the two sidewalls. However, a thin layer deposited on the surface of the gate conductor layer 212 and the body region 203 can protect the semiconductor structure. Here is the first etching of the deposited layer, and the first barrier layer 221 is formed. Further, the width of the bottom of the notch of the concave-shaped first barrier layer is the same as the width of the gap between the two N+ implanted regions, so as to limit the width of the second type of implanted region to be implanted later.

In step S160, ions are implanted between the first type implantation regions at both ends of the body region through the first barrier layer to form second type implantation regions.

As shown in FIG. 4e , through the first barrier layer 221 under the notch of the concave first barrier layer 221, the implantation of the second type implantation region is performed through self-alignment to form the second type implantation region between the first type implantation regions. Two-type implantation region, wherein the second-type implantation region is a P+ implantation region, that is, a P+ body contact region. The notch width of the first barrier layer 221 above the body region 203 is equal to the distance between the first type implantation regions, and the second type implantation regions adjoin the two first type implantation regions at both ends of the body region 203 respectively. The first type implanted region has a first doping type, and the second type implanted region has a second doping type. The material of the first spacer 221 may be, but not limited to, silicon dioxide or silicon nitride. The thin first barrier layer 221 remaining on the surface of the semiconductor structure in the previous step not only protects and isolates the structure, but also does not affect the implantation of the implantation region.

In step S170, the first barrier layer is partially etched to expose the second type implantation region and part of the first type implantation region to form a second barrier layer.

As shown in FIG. 4f, the first barrier layer 221 is etched again by a dry etching process to remove the barrier layer on the surface of the body region 203 and the gate conductor layer 212, so that the second type implantation region and part of the first type implantation region are The region is exposed, and the remaining unetched barrier layer forms the second barrier layer 261 . By adjusting the isotropic and anisotropic etching rates, the first barrier layer 221 on the surface of the gate conductor layer 212 and the surface of the second type implantation region is completely etched, while the gate conductor layer 212 on both sides of the opening is completely etched. The first barrier layer 221 on both sidewalls is partially etched to form the second barrier layer 261 .

Since the thickness of the first barrier layer 221 on the sidewalls on both sides of the opening is relatively thick, and during the etching process, both anisotropic etching and isotropic etching are used, so that the completed barrier layer is only on the opening. The side walls on both sides retain a certain thickness. By adjusting the isotropic and anisotropic etching rates, the width of the formed second barrier layer 261 is, for example, 0.2um, which is easy to implement in the existing 180nm process.

Further, the second barrier layer 261 is formed in the opening, and is two mutually independent spacers on two sidewalls of the gate conductor layer 212 on both sides of the opening. The surface height of the spacer 261 is the same as the edge height of the gate conductor layer 212 on both sides thereof. In addition, the thickness of the first barrier layer 221 formed on the two sidewalls is greater than the thickness of the second barrier layer 261 formed on the two sidewalls.

This step is the second etching of the deposition layer, the first etching to form the first barrier layer 221, the second etching to form the second barrier layer 261, that is, the first barrier layer is etched step by step etch to form the second barrier layer 261, thereby saving the material of the deposition layer and saving the cost. In the conventional solution, after the implantation through the second-type implantation region, the first barrier layer needs to be removed, redeposited, and etched to form the second barrier layer, which wastes raw materials. However, in this embodiment, when the deposition layer is etched for the first time to form the first barrier layer, the etching is not completely completed, and one layer remains, that is, the semiconductor structure is protected, and the implantation is not affected, and During the second etching, the etching can be performed on the basis of the original first barrier layer, and there is no need to deposit again, saving process steps.

Compared with the traditional manufacturing process, the manufacturing method of this embodiment simplifies the formation of the N+ implantation region and the formation of the second barrier layer, so that the process steps are more concise and easy to operate, and the cost is greatly reduced. Operational complexity. The fabricated LDMOS structure is more reliable, and the size of the device can be optimized, the size of the device can be reduced, and the on-resistance can be reduced.

To sum up, using the photoresist layer as a mask and using oblique implantation to form the N+ implantation region reduces the width of the N+ implantation region, reduces the process complexity, and reduces a lot of masks and photoresist layers. In addition, the deposition layer is etched twice to form a first barrier layer and a second barrier layer, which can protect the semiconductor structure and save raw materials, simplify the process steps, and make the source region free from Due to the limitation of the photolithography process capability, the formed implantation region is smaller, which not only effectively reduces the spacing of the openings above the body region, but also simplifies the process steps and saves raw materials and costs. Taking the N-type LDMOS device of 180nm process as a reference, the total width of the implanted region in this embodiment can be reduced to 0.6um as a whole, which greatly reduces the size of the formed device and reduces the source-drain on-resistance.

The process of FIG. 4g and FIG. 4h is similar to that of conventional LDMOS.

Further, the manufacturing method of the lateral double diffused transistor in this embodiment further includes: forming a metal silicide layer between the second barrier layers 261 and on the exposed surface of the gate conductor layer 212 .

As shown in FIG. 4g, a metal silicide layer 271 is formed, wherein the metal silicide layer 271 (silicide) is generally a TiSi2 (titanium silicide) film, which is formed by depositing polysilicon on the surface of the source region after removing the mask. layer, deposit a layer of metal layer (usually Ti, Co or Ni) on the surface of the polysilicon layer and gate structure by sputtering, and then perform rapid heating and annealing treatment (RTA) to make the polysilicon surface and deposition The metals react to form metal silicides that isolate and protect the semiconductor structure from reacting with other deposited layers.

The manufacturing method further includes: forming a dielectric layer on the surfaces of the metal silicide layer and the second barrier layer, and the dielectric layer is formed with a through hole above the region corresponding to the second type implantation region, which is connected to the metal silicide layer.

As shown in FIG. 4h, a dielectric layer 281 is deposited, and the dielectric layer 281 is used to provide isolation, and the cross-section of the deposited structure at the source end region is shown in the figure. A dielectric layer 281 is deposited on the surfaces of the aforementioned metal silicide layer 271 and the second barrier layer 261. The dielectric layer 281 is used to provide isolation protection, and the material of the dielectric layer 281 can be, but not limited to, silicon nitride.

After that, through hole lithography is used to form through holes corresponding to the source region, the drain region and the gate structure through to the surface of the metal silicide layer 271 (metal silicide layer), and the cross-section of the formed structure in the source region is as follows: as shown in the figure. For example, by etching the dielectric layer 281, a through hole 282 that penetrates to the surface of the metal silicide layer and corresponds to the second type implantation region is formed, and then the source electrode is drawn out through the through hole 282 to form a metal contact. The width of the two types of implantation regions is equivalent, or the area of the through hole is equivalent to the surface area of the second type of implantation regions. The dielectric layer 281 is etched with a hole lithography, and due to the presence of the metal silicide layer 271, the N+ source region and the P+ body contact region are connected, and are led out through the through hole 282, saving the arrangement of metal lines.

The manufacturing method further comprises: forming metal contacts to lead out the drain electrode, the gate electrode and the source electrode in the drain region, the surface of the gate conductor layer and the through hole, respectively.

The source electrode, the drain electrode and the gate electrode are respectively drawn out by forming metal contacts. Thus, the fabrication of the LDMOS of this embodiment is completed. Generally, in practical applications, the substrate electrode and the source electrode are connected in common, so in this embodiment, the substrate electrode and the source electrode are collectively referred to as the source electrode.

The first doping type is P-type, and the second doping type is N-type; or, the first doping type is N-type, and the second doping type is P-type. N-type dopant ions include but are not limited to phosphorus ions or arsenic ions, and P-type dopant ions include but are not limited to boron ions.

According to the manufacturing method of the present embodiment, the formed LDMOS has a reduced size of the implanted region in the source region, thereby reducing the overall size of the device, so the on-resistance is reduced, the performance of the device is improved, and the manufacturing process is simple and easy to operate , which is easy to implement.

It should be noted that the above description is mainly for the formation process of the source region of the LDMOS device in the prior art and the schematic cross-sectional structure of each stage in the formation process. For the structure of the drain region of the device, reference may be made to the common knowledge in the prior art. It is understood that the present invention will not describe it again.

Further, in the above embodiments of the present invention, the N-type LDMOS device and the manufacturing method thereof are described, but the present invention is not limited thereto, and is also applicable to the manufacture of the P-type LDMOS device. In addition, the 180 nm process is used as an example in the present invention, but it is also applicable to other process nodes, which is not limited here.

FIGS. 5 a to 5 f respectively illustrate schematic cross-sectional structures of source regions at various stages in a method for manufacturing a lateral double diffused transistor according to another embodiment of the present invention.

The process steps of FIGS. 5a-5c are the same as those of FIGS. 4a-4c, which will not be repeated here, and those skilled in the art can refer to them.

The difference of this embodiment is that, in FIG. 5d, a first barrier layer 321 is formed, and the first barrier layer 321 is a sidewall formed on the sidewalls on both sides of the opening above the body region 203, and its thickness is relatively thick , the width of the space between the sidewalls is the implantation width of the second type of implantation region, and then implanted to form a P+ implantation region.

In FIG. 5e, the first barrier layer 321 needs to be removed first, and then an oxide layer and the like are deposited again to form a second barrier layer 361 through etching, which is also a spacer. From the process steps of FIGS. 5e to 5f, reference may be made to the process steps of FIGS. 4f-4h.

The size of the LDMOS structure obtained by the above embodiments is small, the process steps are simple, the on-resistance is small, and the device performance is improved.

To sum up, the method for manufacturing a lateral double diffused transistor provided by the embodiment of the present invention includes forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; The photoresist etches the gate conductor layer and the gate oxide layer, and is implanted to form a body region; the above-mentioned photoresist is used as a mask to implant obliquely in the body region to form a first type implantation region; on the surface of the gate conductor layer and the body region forming a first barrier layer; forming a second type implantation region between the first type implantation regions through the first barrier layer; and partially etching the first barrier layer to expose the second type implantation region and part of the first type implantation region, Form the second barrier layer, use the photoresist as a mask to implant obliquely to form the first type of implantation region, control the implantation width of the implantation region, and then etch the first barrier layer in steps, which can not only reduce the size of the implantation region, but also reduce the size of the device. The size can effectively reduce the source-drain on-resistance, and it can also save raw materials, avoid the waste of barrier layer materials, and save costs. The entire manufacturing process greatly simplifies the process steps and reduces the difficulty of operation, so as to simplify the supply process and reduce the number of devices. on-resistance.

In addition, in the manufacturing process of the LDMOS device using the Shield Gate Trench (SGT) process to form the channel region, some or all of the steps in the manufacturing method of the LDMOS device provided in the above-mentioned embodiments can also be applied to form a very large-scale LDMOS device. The extraction of the small source electrode reduces the spacing of the polysilicon layer above the source region in the gate structure, which can also reduce the size of the formed device and reduce the source-drain on-resistance.

Although the embodiments are described and described separately above, some common technologies are involved, and in the opinion of those of ordinary skill in the art, they can be replaced and integrated between the embodiments. Reference is made to another example described.

It should be noted that the inclusion of the terms "comprising", "comprising" or any other variation thereof herein is intended to encompass non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. However, the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (12)

1. A method of fabricating a lateral double diffused transistor, comprising:

forming a drift region on top of a substrate;

forming a gate oxide layer and a gate conductor layer which are stacked in sequence on the surface of the drift region, wherein the gate conductor layer defines a drain end region and a source end region which are separated from each other;

etching the grid conductor layer and the grid oxide layer in the source end region through a patterned photoresist layer to form an opening, and injecting ions into the drift region through the opening to form a body region;

injecting ions into the openings from the top two ends of the body region obliquely by taking the photoresist layer as a mask to form a first type injection region;

forming a first barrier layer on the surfaces of the gate conductor layer and the body region; and

and implanting ions between the first type implantation regions at two ends of the body region through the first barrier layer to form a second type implantation region.

2. The method of manufacturing of claim 1, wherein the first barrier layer is reentrant at the body surface.

3. The method of manufacturing of claim 2, wherein the forming the second type implant region further comprises:

and partially etching the first barrier layer to expose the second type injection region and part of the first type injection region so as to form a second barrier layer.

4. The method of manufacturing of claim 1, wherein a width of the first type implant region within the body region is defined according to a thickness of the photoresist layer.

5. The manufacturing method according to claim 1, wherein, in the oblique injection, an angle between an injection direction and a normal to the surface of the substrate is 20 to 60 °.

6. The method of manufacturing of claim 2 wherein said first barrier layer has a recess width over said body region equal to the distance between said first type implant regions, said second type implant regions being contiguous with two of said first type implant regions respectively located at either end of said body region.

7. The manufacturing method according to claim 3, wherein the second barrier layer is formed in the opening and is formed on two sidewalls of the gate conductor layer on two sides of the opening, wherein the two sidewalls are independent of each other.

8. The manufacturing method according to claim 7, wherein a thickness of the first barrier layer formed on both sidewalls of the gate conductor layer on both sides of the opening is larger than a thickness of the first barrier layer formed at a notch between the both sidewalls.

9. The manufacturing method according to claim 7, wherein the first barrier layer is etched using a dry etching process.

10. The manufacturing method according to claim 9, wherein the first barrier layer on the surface of the gate conductor layer and the surface of the second-type implantation region is completely etched and the first barrier layer on the two sidewalls is partially etched by adjusting the isotropic and anisotropic etch rates to form the second barrier layer.

11. The manufacturing method according to claim 1, wherein the manufacturing method further comprises:

forming a metal silicide layer between the second barrier layers and on the exposed surface of the gate conductor layer;

forming a dielectric layer on the surfaces of the metal silicide layer and the second barrier layer, wherein a through hole is formed in the dielectric layer above a region corresponding to the second type injection region and is communicated with the metal silicide layer;

and respectively forming a metal contact leading-out drain electrode, a grid electrode and a source electrode in the drain end region, the surface of the grid conductor layer and the through hole.

12. The method of manufacturing of claim 1, wherein the first type implant region has a first doping type, the second type implant region has a second doping type, the first doping type is P-type, the second doping type is N-type; or, the first doping type is an N type, and the second doping type is a P type.

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