CN111987147A - Power semiconductor device - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, and particularly discloses a power semiconductor device, which comprises: the semiconductor substrate, the semiconductor substrate is divided into active area and terminal area, the active area is located the center district of semiconductor substrate, the terminal area is located the outer lane of active area and encircle the active area sets up, the active area with the terminal area all includes the loop configuration, the radius of curvature of every loop configuration in active area is all the same, the radius of curvature of every loop configuration in terminal area is all the same, just the radius of curvature of the loop configuration in terminal area equals the radius of curvature of the loop configuration in active area. The power semiconductor device provided by the invention can effectively improve and control the breakdown voltage.

Description

A power semiconductor device

technical field

The present invention relates to the technical field of integrated circuits, and in particular, to a power semiconductor device.

Background technique

Generally speaking, in the layout of power semiconductor power components, the corner design of the four corners is closely related to the breakdown voltage of the components, and even more so for the Super-Junction. The superjunction junction device has both P-type doped region pillars and N-type doped region pillars. In the case of reverse bias, maintaining an ideal depletion state and obtaining a higher breakdown voltage (Breakdown) is the focus of the design. .

As far as the breakdown voltage is concerned, the design of any power component needs to consider the active area and the terminal area, and the first charge balance of the superjunction junction is more difficult to design. The bending position of the four corners More because of the unideal design, it is easy to cause the imbalance of charge and reduce the breakdown voltage. Therefore, how to simplify the corner design without distorting the breakdown voltage has always been a technical problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The present invention provides a power semiconductor device, which solves the problem of lower breakdown voltage caused by charge imbalance of the power semiconductor device existing in the related art.

As an aspect of the present invention, a power semiconductor device is provided, which includes: a semiconductor substrate, the semiconductor substrate is divided into an active area and a terminal area, the active area is located in a central area of the semiconductor substrate, and the terminal area The active area is located on the outer ring of the active area and is arranged around the active area. Both the active area and the terminal area include annular structures. The curvature radius of each annular structure of the active area is the same. The radius of curvature of each annular structure of the region is the same, and the radius of curvature of the annular structure of the terminal region is equal to the radius of curvature of the annular structure of the active region.

Further, the semiconductor substrate includes a first columnar doping region and a second columnar doping region both provided in the active region and the terminal region, and the first columnar doping region and the second columnar doping region The columnar doped regions are adjacent and alternately arranged.

Further, the width of the ring structure formed by the first columnar doped region located in the active region gradually decreases from the width at the corner to the width away from the corner, and the width away from the corner remains the same.

Further, the width of the ring structure formed by the first columnar doping region located in the termination region at the corner position and the width away from the corner position are both the same.

Further, the first columnar doping region located in the active region and the terminal region is formed by implanting or etching and then filling polysilicon, and the total height of the first columnar doping region is 30 μm. Between ~100 μm, the second columnar doped regions located in the active region and the termination region are epitaxially grown by MOCVD.

Further, the dopant in the first columnar doping area is arsenic or phosphorus, and the concentration of the dopant in the first columnar doping area is 1*10 ¹⁴ cm ^-3 ~5*10 ¹⁵ cm Between ^-3 , the dopant in the second columnar doping area is boron, and the concentration of the dopant in the second columnar doping area is 1*10 ¹⁴ cm ^-3 ~5*10 ¹⁵ cm ^-3 between.

Further, in the active region, a deep doping region is implanted on the first columnar doping region, and an oxide layer, a polysilicon layer and a dielectric layer are formed on the second columnar doping region, and the well is deep A source doping region is implanted on the doping region, and a metal layer is formed on the source doping region.

Further, the power semiconductor device is an N-type power semiconductor device.

The power semiconductor device provided by the present invention, in the structure of the superjunction junction, abandons the general traditional straight-line layout and closed layout, and uses a continuous annular layout instead, and the curvature of the active region and the terminal region is The radii are equal, which can effectively avoid the charge imbalance caused by the design defects of the straight or closed type itself, and then can effectively improve and control its breakdown voltage.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and together with the following specific embodiments, are used to explain the present invention, but do not constitute a limitation to the present invention.

FIG. 1 is a schematic diagram of one of the corners of the mask layout structure of the power semiconductor device provided by the present invention.

Fig. 2 is a schematic cross-sectional view of the position from A to A' in Fig. 1 .

Detailed ways

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order for those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

In this embodiment, a power semiconductor device is provided. FIG. 1 is a schematic diagram of the layout structure of the power semiconductor device provided according to the embodiment of the present invention. As shown in FIG. 1 , it includes: a semiconductor substrate, and the semiconductor substrate is divided into active area and a terminal area, the active area is located in the central area of the semiconductor substrate, the terminal area is located in the outer circle of the active area and is arranged around the active area, both the active area and the terminal area include a ring The radius of curvature R2 of each annular structure in the active region is the same as the radius of curvature R1 of each annular structure in the terminal region.

In the power semiconductor device provided by the embodiment of the present invention, in the structure of the superjunction junction, the general traditional straight-line layout and closed layout are abandoned, and a continuous annular layout is used instead, and the active area and the terminal area are arranged in a continuous ring. The radii of curvature are all equal, which can effectively avoid the charge imbalance caused by the design defects of the straight or closed type itself, and then can effectively improve and control its breakdown voltage.

As shown in FIG. 1 , the semiconductor substrate includes a first columnar doping region B1 or B3 and a second columnar doping region B2 or B4 disposed in both the active region and the terminal region, and the first columnar doping region B2 or B4 A columnar doping region and the second columnar doping region are adjacent and alternately arranged.

As shown in FIG. 1 , the semiconductor substrate includes the first columnar doping region B1 in the active region and the first columnar doping region B3 in the termination region, and all the columnar doping regions in the active region the second columnar doping region B2 and the second columnar doping region B4 in the termination region. R1 is the radius of curvature of the annular structure in the terminal region, and R2 is the radius of curvature of the annular structure in the active region. In the embodiment of the present invention, all the annular structures maintain the same radius of curvature, that is, R1 =R2.

It should be noted that B1 and B3 are epitaxial first columnar doping regions, B1 is located in the active region, and B3 is located in the termination region, with the same concentration, but the designed length may vary according to their breakdown voltage requirements. B2 and B4 are epitaxial second columnar doping regions, B2 is located in the active region, and B4 is located in the termination region, with the same concentration, but the designed length may vary according to its breakdown voltage requirements.

R1 is the curvature radius of the design ring of the terminal area, and R2 is the curvature radius of the ring structure of the active area. In order to achieve the charge balance of the active area, R1 is equal to R2, but the width and quantity of the terminal areas B3 and B4 depend on the voltage of the designer. Condition needs will vary.

Specifically, the width of the ring structure formed by the first columnar doped region located in the active region gradually decreases from the width at the corner to the width away from the corner, and the width away from the corner remains the same.

As shown in FIG. 1 and FIG. 2 , “far away” in the embodiment of the present invention can be understood as, taking the corner position and direction of the active area shown in FIG. 1 as an example, the distance along the x and y directions in the figure The corner position of the active area. The width of the first columnar doping region B1 located in the active region is L1, and the width of the first columnar doping region B1 located at the corner of the active region is L1', and L1' represents The maximum width of the first columnar doping region B1 at the corner position of the active region, in the embodiment of the present invention, from L1 to L1' to L1, the width of the first columnar doping region B1 will be equal to Progressive from small to large to small.

As shown in FIG. 1 and FIG. 2 , the width of the annular structure formed by the first columnar doping region B3 located in the termination region at the corners and the widths away from the corners are both the same.

L1 and L2 are the widths of the first columnar doped region and the second columnar doped region. In order to obtain the best breakdown voltage, charge balance should be maintained between the two interfaces to achieve complete depletion. Their values can be obtained through simulation and experimental results. It can be found that L1 and L2 provided by the present invention are between 5um and 30um. L1' and L2 are the corner widths of the first columnar doping region and the second columnar doping region. In order to obtain the best breakdown voltage, charge balance should be maintained between the two interfaces to achieve complete depletion, and their values are also transparent. According to simulation and experimental results, L1' and L2 provided by the present invention are between 5um and 30um.

Specifically, the first columnar doped regions located in the active region and the terminal region are formed by implantation or etching and then filled with polysilicon, and the total height of the first columnar doped regions is 30 μm Between ~100 μm, the second columnar doped regions located in the active region and the termination region are epitaxially grown by MOCVD.

In this embodiment, the first columnar doped region can be formed by ion distribution and heating diffusion, or can be etched and filled with polysilicon to save the times and cost of mask lithography process. To form a first columnar doping region, the concentration of the ion implantation process can be 1*10 ¹⁵ cm ^-3 ~ 5*10 ¹⁵ cm ^-3 , and the energy can be 30KeV ~ 150KeV, so that the first columnar doping region is in the The implant thicknesses of the substrates are respectively 0.8 μm˜2 μm.

Specifically, the power semiconductor device includes an N-type power semiconductor device.

More specifically, the dopant in the first columnar doping region is arsenic or phosphorus, and the concentration of the dopant in the first columnar doping region is 1*10 ¹⁴ cm ⁻³ ~5*10 ¹⁵ cm ⁻³ , the dopant in the second columnar doping region is boron, and the concentration of the dopant in the second columnar doping region is 1*10 ¹⁴ cm ⁻³ ~5*10 ¹⁵ between cm ^-3 .

It should be noted that the resistance value of the N-type substrate preferably has a resistance value of 0.002 to 0.004 ohm-cm.

Specifically, as shown in FIG. 2 , in the active region, a deep well doped region 105 is implanted on the first columnar doping region B1, and an oxide layer 106, an oxide layer 106 is formed on the second columnar doping region B2 For the polysilicon layer 103 and the dielectric layer 102 , the source doped region 104 is implanted on the deep well doped region 105 , and the metal layer 101 is formed on the source doped region 104 .

FIG. 2 is a schematic cross-sectional structure diagram of positions A to A' in FIG. 1. In the embodiment of the present invention, the dielectric layer 102 is coated by CVD chemical vapor deposition method, and the thickness of the dielectric layer 102 is 5000Å~ 10000Å, the deposition temperature is 250~400°C, and the deposition rate is 20~30nm/min. In this embodiment, the dielectric layer 102 obtained by the electrochemical deposition method has good uniformity, few particles, good step coverage, and good deposition. The temperature is low, the deposition rate is high, and the cost is extremely low; then a reactive ion etching equipment (RIE) is used to etch the dielectric layer 102 .

Preferably, the process prescription of the dielectric layer is: pressure 7Pa (low pressure to remove polymer); power 100W; CF4 flow rate 50sccm; etching rate 150nm/min. However, the process prescription and etching rate vary with different types. The etching rate of silicon dioxide with more solidified oxygen is fast, and the silicon dioxide with more carbon content is slow. The equation is SiO2 (solid) + CF4 (gas) )+e-→SiF4(gas)+CO(gas).

Preferably, the polysilicon (Poly-Si) process requires that the polysilicon can be etched in an anisotropic manner in a chlorine gas environment, and the process prescription is: pressure 13Pa (low pressure=high selection ratio=low voltage); power 30W; SF6 flow rate 50sccm. But this kind of anisotropic etching is not necessary, it requires more chlorine gas, and it is expensive, so it is not used. Under low pressure SF6 plasma, isotropic etching with good selectivity ratio can be obtained, its selectivity ratio is 100:1, and the equation is Si(solid)+SF6(gas)+O2+e-→SiF4(gas) +SO2 (gas), in plasma etching, process control parameters include temperature and electrode gap in addition to RF power, gas flow, and chamber pressure.

Specifically, the deposition of the metal layer 101 adopts an ion beam sputtering method, wherein Al adopts a high-purity metal target of 99.99%, the sputtering ion beam current is 100mA, and the acceleration voltage is 3000V. The thickness is 50μm~800μm, and the limiting current density of Al is 1.21×10 ⁵ A/cm ² .

It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present invention, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (8)

1. A power semiconductor device, comprising: the semiconductor substrate is divided into an active area and a terminal area, the active area is located in a central area of the semiconductor substrate, the terminal area is located on an outer ring of the active area and surrounds the active area, the active area and the terminal area both comprise annular structures, the curvature radius of each annular structure of the active area is the same, the curvature radius of each annular structure of the terminal area is the same, and the curvature radius of each annular structure of the terminal area is equal to the curvature radius of each annular structure of the active area.

2. The power semiconductor device of claim 1, wherein the semiconductor substrate includes first and second columnar doped regions disposed within both the active region and the termination region, and wherein the first and second columnar doped regions are adjacent and alternating.

3. The power semiconductor device of claim 2, wherein the width of the ring-shaped structure formed by the first pillar-shaped doped region in the active region gradually decreases from the corner position to the corner position, and the width of the ring-shaped structure away from the corner position is uniform.

4. The power semiconductor device of claim 2, wherein the first pillar-shaped doped region in the termination region forms a ring-shaped structure having a width at a corner location that is substantially the same as a width away from the corner location.

5. The power semiconductor device of claim 2, wherein the first columnar doped regions in the active region and the termination region are formed by implanting or etching and then filling polysilicon, the total height of the first columnar doped regions is between 30 μm and 100 μm, and the second columnar doped regions in the active region and the termination region are epitaxially grown by MOCVD.

6. The power semiconductor device of claim 5, wherein the dopant in the first pillar-shaped doped region is arsenic or phosphorus, and the concentration of the dopant in the first pillar-shaped doped region is 1 x 10¹⁴cm^-3~5*10¹⁵cm^-3In the second columnar dopingThe dopant in the region is boron, and the concentration of the dopant in the second columnar doped region is 1 x 10¹⁴cm^-3~5*10¹⁵cm^-3In the meantime.

7. The power semiconductor device according to claim 2, wherein a well-deep doped region is implanted on the first pillar-shaped doped region, an oxide layer, a polysilicon layer and a dielectric layer are formed on the second pillar-shaped doped region, a source doped region is implanted on the well-deep doped region, and a metal layer is formed on the source doped region.

8. The power semiconductor device of claim 1, wherein the power semiconductor device is an N-type power semiconductor device.

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