CN111987003B - Method for realizing electromagnetic shielding function of GaAs chip and GaAs chip - Google Patents
Method for realizing electromagnetic shielding function of GaAs chip and GaAs chip Download PDFInfo
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- CN111987003B CN111987003B CN202010872395.XA CN202010872395A CN111987003B CN 111987003 B CN111987003 B CN 111987003B CN 202010872395 A CN202010872395 A CN 202010872395A CN 111987003 B CN111987003 B CN 111987003B
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Abstract
本发明适用于半导体技术领域，提供了一种实现GaAs芯片电磁屏蔽功能的封装的方法及GaAs芯片，该方法包括：将seal ring结构的两圆片进行键合，即将两圆片的信号连接压点、接地孔压点和seal ring压点分别对应键合，形成封装结构的金属围墙形式；将所述两圆片中的任一圆片的所述信号连接压点和所述seal ring压点通过对应的GaAs衬底引出，将另一圆片的所述接地孔压点和所述seal ring压点通过对应的GaAs衬底引出，形成封装结构的屏蔽金属盖，最终在圆片上实现芯片级电磁屏蔽封装结构，抗干扰能力强。根据本实施例提供的实现GaAs芯片电磁屏蔽功能的封装的方法，可实现大批量生产制作，工艺成本低，结构重复性好，可靠性高。
The invention is applicable to the technical field of semiconductors, and provides a packaging method for realizing the electromagnetic shielding function of a GaAs chip and a GaAs chip. The method includes: bonding two wafers with a seal ring structure, that is, connecting the signals of the two wafers under pressure The point, the ground hole pressure point and the seal ring pressure point are respectively bonded correspondingly to form a metal wall form of the package structure; the signal connection pressure point of any one of the two wafers is connected to the seal ring pressure point. Lead out through the corresponding GaAs substrate, lead out the ground hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate, form the shielding metal cover of the package structure, and finally realize the chip level on the wafer. Electromagnetic shielding package structure, strong anti-interference ability. According to the packaging method for realizing the electromagnetic shielding function of the GaAs chip provided in this embodiment, mass production can be realized, the process cost is low, the structure repeatability is good, and the reliability is high.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a packaging method for realizing an electromagnetic shielding function of a GaAs chip and the GaAs chip.
Background
With the reduction of the size of the device and the improvement of the integration level of the chip, the three-dimensional integration technology is the development direction of the field of future microsystems. The three-dimensional integration technology is a technology and a process for stacking and interconnecting chips in a third dimension and optimizing circuit connection, thereby showing advantages in multiple aspects such as chip multi-functionalization, signal delay reduction, power consumption reduction, chip performance improvement and the like. However, after the chips are stacked, mutual electromagnetic interference exists between the chips, and particularly, the radio frequency circuit is more sensitive to the surrounding electromagnetic interference, and the circuit cannot work normally when the radio frequency circuit is serious.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for implementing a package of a GaAs chip with an electromagnetic shielding function and a GaAs chip, which are used to solve the problem in the prior art that mutual electromagnetic interference exists between chips after the chips are stacked.
In order to achieve the above object, a first aspect of the embodiments of the present invention provides a method for implementing a package of a GaAs chip with an electromagnetic shielding function, including:
respectively setting two wafers into seal ring structures, wherein the two wafers respectively comprise a GaAs substrate, signal connection pressure points, grounding hole pressure points and seal ring pressure points surrounding the signal connection pressure points and the grounding hole pressure points, and the signal connection pressure points and the grounding hole pressure points are arranged on the GaAs substrate;
respectively and correspondingly bonding the signal connection pressure points, the grounding hole pressure points and the seal ring pressure points of the two wafers;
and leading out the signal connection pressure point and the seal ring pressure point of any one of the two wafers through the corresponding GaAs substrate, and leading out the grounding hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate.
As another embodiment of the present application, the bonding of the signal connection pressure point, the ground via pressure point, and the seal ring pressure point of the two wafers respectively includes:
and respectively and correspondingly carrying out gold bonding on the signal connection pressure points, the grounding hole pressure points and the seal ring pressure points of the two wafers.
As another embodiment of the present application, the leading out of the signal connection pressure point and the seal ring pressure point of any one of the two wafers through a corresponding GaAs substrate includes:
thinning the first GaAs substrate of any first wafer of the two wafers;
punching a hole on the back of the thinned first GaAs substrate to expose a signal connection pressure point of the first wafer and a seal ring pressure point of the first wafer;
electroplating a first metal layer on the first GaAs substrate after punching, and leading out a signal connection pressure point of the first wafer and a seal ring pressure point of the first wafer;
corroding the first metal layer on the first metal layer by adopting a wet corrosion process to realize intermetallic isolation;
and preparing a protective layer on the surface of the isolated first metal layer.
As another embodiment of the present application, the electroplating a metal layer on the first GaAs substrate after the hole punching to lead out the signal connection pressure point of the first wafer and the seal ring pressure point of the first wafer includes:
and preparing a first metal layer on the punched first GaAs substrate by adopting a deep hole sputtering and deep hole electroplating interconnection process, and leading the signal connection pressure point of the first wafer and the seal ring pressure point of the first wafer to the surface of the back surface of the first GaAs substrate.
As another embodiment of the present application, the material used for the first metal layer is gold.
As another embodiment of the present application, the material of the protection layer is silicon nitride.
As another embodiment of the present application, the leading out of the ground hole pressure point and the seal ring pressure point of another wafer through a corresponding GaAs substrate includes:
thinning the second GaAs substrate of the other second wafer;
punching a hole in the back of the thinned second GaAs substrate to expose a ground hole pressure point of the second wafer and a seal ring pressure point of the second wafer;
and electroplating a second metal layer on the punched second GaAs substrate, and leading out the grounding hole pressure point of the second wafer and the seal ring pressure point of the second wafer.
As another embodiment of the present application, the second metal layer is made of gold.
A second aspect of an embodiment of the present invention provides a GaAs chip, including:
the first signal connection pressure point and the second signal connection pressure point, the first grounding hole pressure point and the second grounding hole pressure point, and the first seal ring pressure point and the second seal ring pressure point are correspondingly arranged in a bonding mode, the first seal ring pressure point surrounds the first signal connection pressure point and the first grounding hole pressure point, and the second seal ring pressure point surrounds the second signal connection pressure point and the second grounding hole pressure point;
the first signal connection pressure point, the first ground hole pressure point and the first seal ring pressure point are provided with first through holes, and the first GaAs substrate is provided with a metal isolation region; arranging a first metal layer in the first through hole, the intermetallic isolation region and the first GaAs substrate, and arranging a protective layer on the first metal layer;
and the second signal connection pressure point, the second grounding hole pressure point and the second GaAs substrate are arranged on the second seal ring pressure point, wherein second through holes are respectively arranged at the positions on the second GaAs substrate corresponding to the second grounding hole pressure point and the second seal ring pressure point, and second metal layers are arranged in the second through holes and on the second GaAs substrate.
As another embodiment of the present application, the first through hole and the second through hole are V-shaped holes with a wide top and a narrow bottom;
the first metal layer and the second metal layer are made of gold;
the protective layer is made of silicon nitride.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: compared with the prior art, the two wafers of the seal ring structure are bonded, namely the signal connection pressure points, the grounding hole pressure points and the seal ring pressure points of the two wafers are correspondingly bonded respectively to form a metal enclosing wall form of the packaging structure; and leading out the signal connection pressure point and the seal ring pressure point of any one of the two wafers through the corresponding GaAs substrate, and leading out the grounding hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate to form a shielding metal cover of a packaging structure, and finally realizing a chip-level electromagnetic shielding packaging structure on the wafers, wherein the anti-interference capability is strong. According to the packaging method for realizing the electromagnetic shielding function of the GaAs chip, mass production and manufacturing can be realized, the process cost is low, the structure repeatability is good, and the reliability is high.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic implementation flow diagram of a method for implementing a package of a GaAs chip electromagnetic shielding function according to an embodiment of the present invention;
FIG. 2(1) is a schematic diagram of a wafer provided by an embodiment of the present invention;
FIG. 2(2) is a schematic view of another wafer according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a two-wafer bonding provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a signal connection pad and a seal ring pad led out through a corresponding GaAs substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a GaAs chip provided by an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic implementation flow diagram of a method for implementing a package of a GaAs chip with an electromagnetic shielding function according to an embodiment of the present invention, which is described in detail below.
Optionally, the seal ring structure of the wafer is prepared in a previous process of chip preparation, that is, the seal ring pressure points are set to surround the signal connection pressure points and the ground hole pressure points. As shown in fig. 2(1) and 2(2), fig. 2(1) and 2(2) are two wafers, wherein 11 and 21 respectively represent GaAs substrates of the wafers, 12 and 22 respectively represent seal ring pressure points of the wafers, 13 and 23 respectively represent signal connection pressure points of the wafers, and 14 and 24 respectively represent ground hole pressure points of the wafers.
And 102, correspondingly bonding the signal connection pressure points, the grounding hole pressure points and the seal ring pressure points of the two wafers respectively.
As shown in fig. 3, the signal connection pressure points, the ground hole pressure points, and the seal ring pressure points of the two wafers are respectively and correspondingly bonded, so that the first wafer and the second wafer are stacked together.
Optionally, in this step, gold-to-gold bonding may be performed on the signal connection pressure points, the ground hole pressure points, and the seal ring pressure points of the two wafers, respectively, that is, gold wire or gold tape bonding is adopted.
And 103, leading out the signal connection pressure point and the seal ring pressure point of any one of the two wafers through the corresponding GaAs substrate, and leading out the ground hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate.
Optionally, in this step, the leading out of the signal connection pressure point and the seal ring pressure point of any one of the two wafers through the corresponding GaAs substrate may include:
thinning the first GaAs substrate of any first wafer of the two wafers;
punching a hole on the back of the thinned first GaAs substrate to expose a signal connection pressure point of the first wafer and a seal ring pressure point of the first wafer;
electroplating a first metal layer on the first GaAs substrate after punching, and leading out a signal connection pressure point of the first wafer and a seal ring pressure point of the first wafer;
corroding the first metal layer on the first metal layer by adopting a wet corrosion process to realize intermetallic isolation;
and preparing a protective layer on the surface of the isolated first metal layer.
As shown in fig. 4, the signal connection voltage point and the seal ring voltage point are led out through the corresponding GaAs substrate, in fig. 4, the first metal layer is divided into two parts according to different functions, 5 denotes a shielding metal in the first metal layer, 6 denotes a signal connection voltage point leading-out terminal in the first metal layer, and 7 denotes a protection layer on the first metal layer.
Optionally, when the first GaAs substrate is thinned, the first wafer may be thinned through a die bonding process, a coarse thinning process, a fine thinning process, and a polishing process.
Optionally, the electroplating a metal layer on the first GaAs substrate after the hole punching to lead out the signal connection pressure point of the first wafer and the seal ring pressure point of the first wafer may include:
and preparing a first metal layer on the punched first GaAs substrate by adopting a deep hole sputtering and deep hole electroplating interconnection process, and leading the signal connection pressure point of the first wafer and the seal ring pressure point of the first wafer to the surface of the back surface of the first GaAs substrate.
Optionally, the first metal layer is made of gold.
Optionally, a wet etching process is used to etch the first metal layer on the first metal layer, and when the intermetallic isolation is achieved, a photoresist may be coated on the first metal layer, and then exposure and development are performed, where a development region is an intermetallic isolation region to be performed, and then wet etching is performed on the development region, and the signal connection pressure point and the metal isolation region are defined. And then the metal in the isolation region is completely corroded by utilizing the masking of the photoresist, thereby achieving the purpose of intermetallic isolation. And then removing the masking photoresist, and finally finishing the manufacture of the shielding metal cover and the signal connection pressure point of the packaging structure of the first wafer.
Optionally, the protective layer is made of silicon nitride.
In this step, the leading out of the ground hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate may include:
thinning the second GaAs substrate of the other second wafer; punching a hole in the back of the thinned second GaAs substrate to expose a ground hole pressure point of the second wafer and a seal ring pressure point of the second wafer; and electroplating a second metal layer on the punched second GaAs substrate, and leading out the grounding hole pressure point of the second wafer and the seal ring pressure point of the second wafer.
Optionally, the second metal layer is made of gold.
The process flow for thinning the second GaAs substrate of the second wafer is the same as the process flow for thinning the first GaAs substrate of the first wafer, and details are not repeated here.
And preparing a second metal layer on the punched second GaAs substrate by adopting a deep hole sputtering and deep hole electroplating interconnection process, and leading the grounding hole pressure point of the second wafer and the seal ring pressure point of the second wafer to the surface of the back surface of the second GaAs substrate.
Fig. 5 shows a finished GaAs chip with electromagnetic shielding function, and 8 in fig. 5 shows a second metal layer, which is a lower shielding metal layer and can be used for grounding.
According to the method for realizing the encapsulation of the GaAs chip electromagnetic shielding function, the two wafers of the seal ring structure are bonded, namely, the signal connection pressure points, the grounding hole pressure points and the seal ring pressure points of the two wafers are correspondingly bonded respectively to form a metal enclosing wall form of the encapsulation structure; and leading out the signal connection pressure point and the seal ring pressure point of any one of the two wafers through the corresponding GaAs substrate, and leading out the grounding hole pressure point and the seal ring pressure point of the other wafer through the corresponding GaAs substrate to form a shielding metal cover of a packaging structure, and finally realizing a chip-level electromagnetic shielding packaging structure on the wafers, wherein the anti-interference capability is strong. According to the packaging method for realizing the electromagnetic shielding function of the GaAs chip, mass production and manufacturing can be realized, the process cost is low, the structure repeatability is good, and the reliability is high.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The embodiment of the invention provides a GaAs chip corresponding to the method for realizing the electromagnetic shielding function of the GaAs chip. As shown in fig. 5, the apparatus may include:
the first signal connection pressure point and the second signal connection pressure point, the first grounding hole pressure point and the second grounding hole pressure point, and the first seal ring pressure point and the second seal ring pressure point are correspondingly arranged in a bonding mode, the first seal ring pressure point surrounds the first signal connection pressure point and the first grounding hole pressure point, and the second seal ring pressure point surrounds the second signal connection pressure point and the second grounding hole pressure point;
the first signal connection pressure point, the first ground hole pressure point and the first seal ring pressure point are provided with first through holes, and the first GaAs substrate is provided with a metal isolation region; arranging a first metal layer in the first through hole, the intermetallic isolation region and the first GaAs substrate, and arranging a protective layer on the first metal layer;
and the second signal connection pressure point, the second grounding hole pressure point and the second GaAs substrate are arranged on the second seal ring pressure point, wherein second through holes are respectively arranged at the positions on the second GaAs substrate corresponding to the second grounding hole pressure point and the second seal ring pressure point, and second metal layers are arranged in the second through holes and on the second GaAs substrate.
In fig. 5, the first signal connection pressure point is 13, the second signal connection pressure point is 23, the first ground hole pressure point is 14, the second ground hole pressure point is 24, the first seal ring pressure point is 12, and the second seal ring pressure point is 22. The first GaAs substrate is 11 and the second GaAs substrate is 21. 5 and 6 denote first metal layers, 8 denotes second metal layers, and 7 denotes protective layers.
Optionally, as shown in fig. 5, the first through hole and the second through hole are V-shaped holes with a wide top and a narrow bottom;
the first metal layer and the second metal layer are made of gold;
the protective layer is made of silicon nitride.
The GaAs chip is correspondingly bonded with a first signal connection pressure point, a second signal connection pressure point, a first grounding hole pressure point, a second grounding hole pressure point, a first seal ring pressure point and a second seal ring pressure point to form a metal enclosing wall form of a packaging structure; the first signal connection pressure point and the first seal ring pressure point are led out through the corresponding first GaAs substrate, the second grounding hole pressure point and the second seal ring pressure point are led out through the corresponding second GaAs substrate, a shielding metal cover of a packaging structure is formed, finally, the chip-level electromagnetic shielding packaging structure is achieved on the wafer, and the anti-interference capability is high.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
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