CN111970514A - Military audio-video coding chip - Google Patents

Abstract

The invention discloses a military audio and video coding chip, which adopts an H.264 audio and video compression principle and adopts a multi-core high-integration SOC framework of an ARM + DSP + hardware acceleration engine; the military audio and video coding chip comprises a control chip W99200F, SAA7114H of PHILIPS, 1 MX16 bits SDRAM of Winbond and pcm1800 of BURR-BROWN, wherein the upd485505g of NEC cooperates with the W99200F to form an audio and video acquisition compression card; the chip adopts an H.264 audio and video compression principle and adopts a multi-core high-integration SOC framework of an ARM + DSP + hardware acceleration engine; the complexity of the system is greatly reduced, and the performance and the stability of the system are improved.

Description

Military audio and video coding chip

technical field

The invention relates to the field of chips, in particular to a military audio and video coding chip.

Background technique

The pursuit of information by human beings, from simple chronicle of knots, symbolic records to rich graphics, and later audio and video films, has always been the pursuit of the most practical human sensory enjoyment. Entering the Internet age, information explosion, the huge information flow has brought The richness of human culture has also brought about the trouble of storing information. Especially the huge data of video information has given birth to the demand of video compression technology. Video compression technology has become one of the most popular technologies in the multimedia era, and is widely used in the fields of image transmission and storage such as television, film, videophone, video conference, and remote monitoring.

Therefore, there is an urgent need to provide an audio and video coding chip with high performance and high stability.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a military audio and video coding chip to solve the above-mentioned problems in the prior art.

For achieving the above object, the present invention provides the following scheme:

The invention provides a military audio and video coding chip, which adopts the H.264 audio and video compression principle, and adopts a multi-core and highly integrated SOC framework of ARM+DSP+hardware acceleration engine;

The military audio and video coding chips include control chip W99200F, SAA7114H of PHILIPS, 1M×16bits SDRAM of Winbond, pcm1800 of BURR-BROWN, upd485505g of NEC and W99200F to form an audio and video capture and compression card;

The military audio and video coding chip is composed of six pieces of the capture and compression cards and supporting components;

The kit includes a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter, and a digital audio and video interface; wherein, the output end of the 6-channel analog-to-digital converter ADC and the input of the digital filter The output end of the digital filter is connected with the 2-channel digital-to-analog converter and the digital audio and video interface respectively;

The military audio and video coding chip adopts a 0.13 μm process and is packaged in LFBGA400, with a size of 23×23 mm and an indirect pin of 0.5 mm.

Further, the input end of each channel of the 6-channel analog-to-digital converter is connected to the first mute function circuit, and the first mute circuit is connected to the output end of the programmable gain amplifier.

Further, the output end of each channel of the 2-channel digital-to-analog converter is connected to the second mute function circuit.

Further, the analog-to-digital converter is a 24-bit Sigma-Delta converter, which operates at a sampling rate of 128 times, and the sampling rate ranges from 8kHz to 96kHz. The analog-to-digital converter includes a digital high-pass filter and a digital volume control. circuit.

Further, the digital audio and video interfaces include digital video interfaces, USB, ETH, I2S, I2C, GPIO, SPI, UART, SD RAM, and DDR interfaces.

The present invention discloses the following technical effects:

The invention provides a high-performance, high-stability military audio and video coding chip, which adopts the H.264 audio and video compression principle, and adopts a multi-core high-integration SOC framework of ARM+DSP+hardware acceleration engine; The complexity improves the performance and stability of the system.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail, which detailed description should not be construed as a limitation of the invention, but rather as a more detailed description of certain aspects, features, and embodiments of the invention.

It should be understood that the terms described in the present invention are only used to describe particular embodiments, and are not used to limit the present invention. Additionally, for numerical ranges in the present disclosure, it should be understood that each intervening value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intervening value in a stated range and any other stated value or intervening value in that stated range is also encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention relates. Although only the preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention. All documents mentioned in this specification are incorporated by reference for the purpose of disclosing and describing the methods and/or materials in connection with which the documents are referred. In the event of conflict with any incorporated document, the content of this specification controls.

It will be apparent to those skilled in the art that various modifications and variations can be made in the specific embodiments of the present invention without departing from the scope or spirit of the invention. Other embodiments will be apparent to those skilled in the art from the description of the present invention. The description and examples of the present application are only exemplary.

The embodiment of the present invention provides a military audio and video coding chip, the military audio and video coding chip adopts the H.264 audio and video compression principle, and adopts a multi-core and highly integrated SOC framework of ARM+DSP+hardware acceleration engine;

The military audio and video coding chips include control chip W99200F, SAA7114H of PHILIPS, 1M×16bits SDRAM of Winbond, pcm1800 of BURR-BROWN, upd485505g of NEC and W99200F to form an audio and video capture and compression card;

The military audio and video coding chip is composed of six pieces of the capture and compression cards and supporting components;

The kit includes a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter, and a digital audio and video interface; wherein, the output end of the 6-channel analog-to-digital converter ADC is connected to the digital filter. The input end of the digital filter is connected to the input end of the digital filter, and the output end of the digital filter is respectively connected to the 2-channel digital-to-analog converter and the digital audio and video interface; The mainstream A/D chip on the market can only collect two signals, which greatly reduces the complexity, cost and power consumption of the system;

The military audio and video coding chip adopts a 0.13 μm process and is packaged in LFBGA400, with a size of 23×23 mm and an indirect pin of 0.5 mm.

As another aspect of this embodiment, the input end of each channel of the 6-channel analog-to-digital converter is connected to a first mute function circuit, and the first mute circuit is connected to the programmable gain amplifier. output connection.

As another aspect of this embodiment, the output end of each channel of the 2-channel digital-to-analog converter is connected to the second mute function circuit.

As another aspect of this embodiment, the analog-to-digital converter is a 24-bit Sigma-Delta converter, which operates at a sampling rate of 128 times, and the sampling rate ranges from 8kHz to 96kHz, and the analog-to-digital converter includes a digital high-pass filter and digital volume control circuit.

As another aspect of this embodiment, the digital audio and video interfaces include digital video interfaces, USB, ETH, I2S, I2C, GPIO, SPI, UART, SD RAM, and DDR interfaces.

The military audio and video encoding chip described in this embodiment adopts the H.264 audio and video compression principle, and adopts a multi-core and highly integrated SOC architecture of ARM+DSP+hardware acceleration engine; Prediction, inter-frame prediction, motion estimation and motion compensation, integer transformation and other methods to improve the compression rate of the image. The intra-frame prediction is that the chip adopts a new intra-frame prediction mode according to the properties of adjacent pixels in the image that may be the same, using the correlation of adjacent pixels, through the left and upper pixels of the current pixel block. ) for prediction, and only the difference between the actual value and the predicted value is encoded, so that the pixel block information of the intra-frame encoding can be expressed with a smaller number of bits; while the inter-frame prediction uses multi-frame references and smaller motion prediction areas, etc. The method accurately predicts the next frame, thereby reducing the amount of transmitted data and reducing the temporal correlation of images. The chip can transform the residual results of motion estimation and intra-frame prediction from the time domain to the frequency domain, using an integer transform similar to the 4×4 discrete cosine transform DCT (Discrete Cosine Transform), rather than MPEG2 and MPEG4. Floating point transformation using 8×8 DCT. Integer-based spatial transformation has the advantages of good effect, fast calculation (only addition and shift operations), and no adaptation problems in the inverse transformation process. Combined with the quantization process, it ensures that in a 16-bit computing system The result of the calculation has maximum precision and will not overflow. The 4×4 transform block and 8×8 can reduce the block effect and ringing effect, thus greatly reducing the complexity of the system and improving the performance and stability of the system.

The military audio and video coding chip described in this embodiment is composed of the core of ARM+DSP+Video Codec Accelerator+Graphics Engine Scaler, which integrates a wealth of peripheral interfaces, and the internal integration includes algorithms such as digital watermarking and DES/3DES, making a single chip It can meet all basic tasks, reduce the development difficulty of cooperating with other chips, and also avoid the repeated development of standard parts such as algorithms by manufacturers, which greatly reduces the investment threshold for equipment manufacturers. With the development kits of different application forms, various products such as PMP, videophone, network monitoring, PVR, video intercom, etc. can be developed. Moreover, as a codec chip of the SoC architecture, the chip is designed with full consideration of compatibility and ease of use, and supports almost all series of AD/DA chips produced by companies. The chip can work either as an independent encoder, or as an independent decoder, or at the same time for encoding and decoding, which fully considers various applications in the encoding and decoding market. The chip is a typical multi-application single-chip solution, which greatly reduces the BOM composition and cost of the device.

The above-mentioned embodiments are only to describe the preferred modes of the present invention, but not to limit the scope of the present invention. Without departing from the design spirit of the present invention, those of ordinary skill in the art can make various modifications to the technical solutions of the present invention. Variations and improvements should fall within the protection scope determined by the claims of the present invention.

Claims (5)

1. A military audio and video coding chip is characterized in that the military audio and video coding chip adopts an H.264 audio and video compression principle and adopts a multi-core high-integration SOC framework of an ARM + DSP + hardware acceleration engine;

the military audio and video coding chip comprises a control chip W99200F, SAA7114H of PHILIPS, 1 MX16 bits SDRAM of Winbond and pcm1800 of BURR-BROWN, wherein the upd485505g of NEC cooperates with the W99200F to form an audio and video acquisition compression card;

six acquisition compression cards and matched elements are adopted to form the military audio and video coding chip;

the matched elements comprise a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio and video interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio/video interface;

the military audio and video coding chip is packaged by LFBGA400 by adopting a 0.13-micron process, the size of the military audio and video coding chip is 23mm multiplied by 23mm, and the pin indirection is 0.5 mm.

2. The military audio/video coding chip of claim 1, wherein an input terminal of each of the 6-channel analog-to-digital converters is connected to a first mute function circuit, and the first mute circuit is connected to an output terminal of a programmable gain amplifier.

3. The military audio/video coding chip of claim 1, wherein an output terminal of each of the 2-channel digital-to-analog converters is connected to a second mute function circuit.

4. The military audio-video coding chip of claim 1, wherein the analog-to-digital converter is a 24-bit Sigma-Delta type converter operating at 128 times oversampling rate and having a sampling rate in the range of 8kHz to 96kHz, the analog-to-digital converter comprising a digital high-pass filter and a digital volume control circuit.

5. The military audio-video coding chip of claim 1, wherein the digital audio-video interface comprises a digital video interface, USB, ETH, I2S, I2C, GPIO, SPI, UART, SD RAM, DDR interface.