CN1119748C - Memory page management device and method for tracking access to memory - Google Patents

Abstract

The present invention relates to a memory page management device and a method. The device is used for tracking the access of a memory main control circuit to a memory. The memory page management device comprises a page temporary storage circuit, a comparison circuit, an utilization rate temporary storage circuit and an assurance circuit, wherein the page temporary storage circuit has a plurality of storage units for storing address date of a plurality of memory pages. The comparison circuit is connected to the page temporary storage circuit. An access address is accepted and is compared with the stored address date to generate a selected signal as reference for controlling the memory. The utilization rate temporary storage circuit and the assurance circuit are used for managing the reference of the storage units.

Description

Memory page management devices and method in order to track memory accesses

The present invention relates to a kind of memory management unit and method, but and be particularly related to memory page management devices and the method that a kind of track memory accesses situation is chosen rate with raising and reduced memory-access delays.

In current multiplex's computer operating system, continuous a plurality of access actions of each storer governor circuit (memory master) are the some address areas in storer mostly, therefore how to make expend time in (overhead) of the access memory of storer governor circuit to reduce to time delay (latency) minimum and that reduce access, become present most important problem.

Existing Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random AccessMemory, abbreviation SDRAM) 4 secondary area pieces (sub-bank) is arranged at most, because each secondary area piece only can be opened a memory page, just can open 4 memory pages at most, therefore the existing memory controller is managed the memory page of DRAM respectively at the control circuit of each memory block (bank) designs fix, for example can open 2 memory pages or 4 memory pages at most simultaneously, 4 groups of control circuits then will be arranged.

The shortcoming of therefore existing way is:

1. do not plug SDRAM as if on certain memory block, or plug SDRAM, but this SDRAM has only two secondary area pieces, this moment, the control circuit that is not used to was just wasted because the control circuit that is not used to can not be used by other memory block.

2. if what use in system is tunnel SDRAM (Virtual Channel SDRAM is called for short VC-SDRAM), because VC-SDRAM can open 16 passages at most simultaneously, therefore if only make 4 groups of control circuits, then has 12 passages to use.Correspondingly, if make 16 groups of control circuits, then control circuit can take too big area, do not meet the economic benefit requirement, and because circuit causes delay too big too greatly, so be not suitable in the system at a high speed, in addition, if use SDRAM, then have at least 12 groups of control circuits to be wasted.

Therefore at the problems referred to above and other purposes, the present invention proposes a kind of memory page management devices in order to track memory accesses, utilize and do not use (Least Recently Used at most, abbreviation LRU) algorithm, no matter which kind of storer is system use, for example EDO DRAM, SDRAM or VC-SDRAM all can be shared, the rubber-like great advantage.

The memory page management devices in order to track memory accesses that the present invention proposes comprises one page buffering circuit, a contrast circuit, a utilization factor buffering circuit, reaches an affirmation circuit.

Have a plurality of storage elements in the page or leaf buffering circuit, use for the address date that stores a plurality of memory pages, wherein each this storage element is deposited the address date of a memory page.

This contrast circuit is connected to this page buffering circuit, in order to accept an access address, and according to the comparing result of the data of this access address and this page buffering circuit, export a selected signal, when one of the address date of these memory pages that store in this page buffering circuit was chosen in this access address, this selected signal was effect.

This utilization factor buffering circuit is connected to this page buffering circuit, in order to control the use situation of these storage elements.Whether this affirmation circuit is connected to this page buffering circuit, effective in order to the data of judging these storage elements;

Wherein this page buffering circuit comprises a data storing table, a latch cicuit, and these storage elements are arranged in this data storing table, and this latch cicuit is connected to this contrast circuit, latchs in order to this selected signal with this contrast circuit output.

According to one of the present invention preferred embodiment, this page buffering circuit comprises a data storing table, one latch cicuit, reach one and select circuit, these storage elements are arranged in this data storing table, this latch cicuit is connected to this contrast circuit, in order to this selected signal latched bit with this contrast circuit output, this selection circuit is connected to this latch cicuit, this utilization factor buffering circuit, this confirms circuit, and this data storing table, in order to according to individual one of among these storage elements of this data storing table of output signal selection of this selected signal of latching and this utilization factor buffering circuit and this affirmation circuit.

In addition, also have a plurality of acknowledgement bits among the memory page management devices, each acknowledgement bit corresponds respectively to one of these storage elements, and when this acknowledgement bit was setting, the data that are stored in this corresponding storage element were only effectively.And this contrast circuit judges according to these acknowledgement bits whether the data of these storage elements are effectively, and this contrast circuit also is responsible for upgrading the value of these acknowledgement bits.

Also have a plurality of utilization factor data in this memory page management devices, each utilization factor data is corresponding to one of these storage elements, in order to represent the utilization factor of these storage elements.This utilization factor buffering circuit is according to the use situation of these these storage elements of utilization factor Data Control, and responsible these utilization factor data of upgrading.

According to one of the present invention preferred embodiment, wherein these utilization factor data can be used the utilization factor of this storage element of digitized representation correspondence, when the value of these utilization factor data is big more, represent corresponding of a specified duration more not being used of this storage element.

This memory page management devices is in when operation, when the address date of these memory pages that store in these storage elements is not chosen in this access address, this access address is stored to this storage element corresponding to a peak use rate value.And, when the affirmation bit corresponding to this storage element of this peak use rate data value when being effective, before this access address being stored to corresponding to this storage unit of this peak use rate value, produce one according to the address date of this storage element and go back raw address, in order to reduce the state of one of corresponding memory page.

According to another practice of the present invention, this memory page management devices is accepted an access address, and an output one page selected signal and a block selected signal, and this memory page management devices comprises one page buffering circuit, a contrast circuit, a utilization factor buffering circuit, and one confirms circuit.

Wherein this page buffering circuit has a plurality of storage elements, uses for the address date that stores a plurality of memory pages, and wherein each this storage element is deposited the address date of a memory page, and each this address date comprises block address data and one page address date.

This contrast circuit is connected to this page buffering circuit, in order to accept an access address, and according to the comparing result of the data of this access address and this page buffering circuit, export this page selected signal and this block selected signal, when the block address data of one of address date of these memory pages that store in this page buffering circuit are chosen in this access address, this block selected signal is effect, when these block address data of one of address date of these memory pages that store in this page buffering circuit and this page address data were chosen in this access address, this block selected signal and this page selected signal acted on simultaneously.

This utilization factor buffering circuit is connected to this page buffering circuit, in order to control the use situation of these storage elements, when the address date of these memory pages is not chosen in this access address,, and this is deposited the address deposit this untapped at most storage element in by finding out a untapped at most storage element in these storage elements according to this utilization factor buffering circuit.

Whether this affirmation circuit is connected to this page buffering circuit, effective in order to the data of judging these storage elements.

According to one of the present invention preferred embodiment, when this access address choose these memory pages that store in this page buffering circuit one of address date the block address data but when not choosing these page address data, then upgrade this page address data according to this access address.

According to above-mentioned memory page management devices of the present invention, the present invention proposes a kind of memory page management method in order to track memory accesses, comprises the following steps:

Provide a plurality of storage elements, in order to store the address date of a plurality of memory pages;

Accept an access address;

Address date contrast with this access address and these storage elements;

When the address date of one of these storage elements is chosen in this access address, send a selected signal;

When the address date of one of these storage elements is not chosen in this access address, find out a untapped at most storage element by these storage elements, deposit this access address in this untapped at most storage element; And

When this access address does not choose the address date of one of these storage elements and this untapped at most storage element to store effective address date, this access address is deposited in this at most untapped storage element before, produce a reduction address signal according to the original address date that stores of this untapped at most storage element, in order to reduce the state of one of corresponding memory page.

According to the memory page management devices that the invention described above proposed in order to track memory accesses, can be via the access action of trace memory governor circuit, choose rate and data can share for the storer governor circuit except increasing page or leaf, and can prejudge next streamline access (pipelined access) and whether need precharge, in order to when carrying out existing access, promptly send precharge (precharge) order to give another memory block earlier, in advance another memory block is carried out precharge, can reduce the time delay of access.

State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Fig. 1 is the calcspar of the memory page management devices in order to track memory accesses of the present invention.

Fig. 2 is the synoptic diagram of the data storing table that uses in the memory page management devices of the present invention.

Fig. 3 be memory page management devices of the present invention contrast circuit than detailed block diagram.

Fig. 4 be memory page management devices of the present invention the page or leaf buffering circuit than detailed block diagram.

Fig. 5 A be memory page management devices of the present invention the utilization factor buffering circuit than detail circuits figure.

Fig. 5 B be memory page management devices of the present invention the affirmation circuit than detail circuits figure.

Fig. 6 is the operational flowchart of memory page management devices of the present invention.

Fig. 7 A to Fig. 7 G is the synoptic diagram of operating process of the tables of data of memory page management devices of the present invention.

Fig. 8 A to Fig. 8 D and Fig. 9 A to Fig. 9 B are the sequential chart of memory page management devices of the present invention under the different operating situation.

In order to reach the function of following the tracks of each storer governor circuit, store table (page tabel) in system storage controller bist data, so can allow the process of system storage controller according to storer governor circuit access memory, the memory page that record is opened and the information of memory block, then when access subsequently, can compare with the content of data storing table, so can improve page or leaf and choose rate (page hitrate) and promote data to share, also can reduce and expend time in.

Please refer to Fig. 1, its expression is according to the synoptic diagram of a kind of memory page management devices in order to track memory accesses of a preferred embodiment of the present invention.

As shown in the figure, memory page management devices 100 is the signal DA[27:11 of location data acceptably], SEGIN[1:0], and BANK[9:0], data with internal reservoir contrast again, send selected signal then, signal DA[27:11 wherein], SEGIN[1:0], and BANK[9:0] can be the address signal sent by storer governor circuit (master) (not shown) and resultant through the decoding circuit (not shown), in addition, selected signal can comprise that page or leaf chooses (page hit) signal ONPAG, block is chosen (bank hit) signal BKHIT, and (segment hit) signal SEGHIT in the selected parts.Reference when the selected signal that memory page management devices 100 is sent can supply the memorizer control circuit control store, for example according to the resulting selected signal of address signal for not acting on, the address of then representing its access is the memory page of closing at storer, therefore before the data of carrying out access memory, must send relevant order and give storer, for example precharge (precharge) and startup (activate) order are used for closing the memory page of having opened and open required memory page.

Mainly comprise contrast circuit 110, page or leaf buffering circuit 120, utilization factor buffering circuit 130 in the memory page management devices 100, reach and confirm circuit 140.

In page or leaf buffering circuit 120, have data storing table 125, in data storing table 125, have a plurality of storage elements, can be for the related data that stores about track memory accesses.Data storing table 125 can use the form of Fig. 2 to represent.With each line (row) in the form is a storage element, and (A～H) is an example with 8 storage elements at this.At each row, promptly store data in each storage element about storage access.Wherein storing hurdle BKVC is the address date that is used for storing VC-SDRAM.Store hurdle BNK and be used for storing the block of SDRAM or VC-SDRAM or the address date of secondary area piece (sub-bank).Store hurdle SEG and be the address date of the sections (segment) that is used for storing VC-SDRAM.Store hurdle PAG and be the address date of the memory page that is used for storing SDRAM or VC-SDRAM.The level data of the utilization factor (utilization) that storage hurdle LRU is referenced to for this storage element.Store hurdle VLD and represent whether the data of this storage element are effective (valid).Certainly, known this operator knows, in data storing table 125, is not limited to store above-mentioned data, also can store about other required data of storage access control by actual needs.In addition, each field in the data storing table 125 is also decided by the side circuit design, and design for example, stores hurdle LRU and can design in utilization factor buffering circuit 130 in different circuit box, can design among affirmation circuit 140 and store hurdle VLD.

Please refer to Fig. 3, its expression contrast circuit 110 than detailed block diagram.As shown in the figure, contrast circuit 110 comprise page contrast circuit 310, block contrast circuit 320 and with non-(NAND) door 330,340, and 350.Wherein page or leaf contrast circuit 310 is with the signal DA[27:11 of input] and signal SEGIN[1:0] contrast with address date 311～318, output signal PAGHIT[7:0 then] and SEGHIT[7:0], as previously mentioned, address date 311～318 can be to be stored in data PAG, SEG in the data storing table 125, and BKVC, and represent the PAG value of storage element A with " PAG-A ", the sign of other data is also with reference to this mode.Block contrast circuit 320 is with signal BANKIN[9:0] contrast with address date 321～328, Shu Chu signal BKHIT_[H:A then] _, PGHIT_[H:A] _, and SGHIT_[H:A] _, as previously mentioned, address date 321～328 can be data BNK and the VLD that is stored in the data storing table 125.In this embodiment, signal BKHIT_[H:A] _, PGHIT_[H:A] _, and SGHIT_[H:A] _ be to represent that with electronegative potential this signal is effect.Therefore, signal BKHIT_[H:A] _, PGHIT_[H:A] _, and SGHIT_[H:A] _ again through NAND lock 330,340, and 350 producing selected signal BKHIT, ONPAG, and SEGHIT, these three selected signals also are that to represent it with electronegative potential be effect.

Please refer to Fig. 4, its expression page or leaf buffering circuit 120 than detailed block diagram.As shown in the figure, in page or leaf buffering circuit 120, except data storing table 125, still comprise latch cicuit 410 and select circuit 420 with the required address date of storing memory operation.Latching the signal latch that signal that (latch) circuit 410 can send contrast circuit 110 and other circuit (illustrating) send here lives, deliver to selection circuit 420 by the signal that latch cicuit 410 latchs through line 412, line 412 has the many signal line corresponding to the input signal of latch cicuit 410, delivers in order to the signal that will latch and selects circuit 420.Select 420 in circuit according to latch cicuit 410, utilization factor buffering circuit 130, and confirm that the signal that circuit 140 is sent here produces signal SEL, be used for selecting the storage element in the data storing table 125.Then,, for example signal BANK, LDA[27:11 according to other input signal], SEGMENT, and VCSDRAM, carry out Data Update at the storage element that is chosen to.As previously mentioned, store address date 431～438 in the data storing table 125, and these address dates use in the time of can operating for contrast circuit 110.

Please refer to Fig. 5 A, its expression utilization factor buffering circuit 130 than detail circuits figure.As shown in the figure, utilization factor buffering circuit 130 is the values that are used for upgrading LRU.It is contemplated that, will corresponding to selected to the LRU value of storage element be made as 0, that is represent its data for using recently.And will than selected to the little LRU value of original LRU value of storage element all add one, with so that other LRU value all greatly than the LRU value that is chosen to.Its key must be unique for the LRU value of each storage element, with the LRU value with eight storage elements is example, the LRU value of each storage element must be one of among 0 to 7, and be unique, the summation of promptly all LRU values must equal 28, that is is assigned to the summation of 0 to 7 value of the LRU value of each project.Otherwise the operation of this device promptly can go wrong.The value of upgrading LRU is to carry out after the one-period that receives comparison signal PGCMP or update signal PGUPD, and the time delay of one-period can be for calculating new LRU value.When it chooses memory block, then after contrast, determine that it is the address date of choosing certain storage element, so after the one-period of signal PGCMP, carry out the renewal of LRU value, relative, when other do not choose the situation of any storage element, then when upgrading the data of storage element, upgrade its LRU value, so after the one-period of signal PGUPD, carry out the renewal of LRU value.When this device begins to operate at first, also need the LRU value of each storage element is initialized, for selection action thereafter.

Please refer to Fig. 5 B, its expression confirm circuit 140 than detail circuits figure.As shown in the figure, confirm whether circuit 140 can be active data in order to the storage values of confirming corresponding storage element according to the affirmation bit of the signal output of importing corresponding to each storage element.For example, when its acknowledgement bit when setting (set) (as being made as 1), the storage values of representing the storage element that it is corresponding is effective memory page address, can be used for and the address signal imported contrasts from contrast circuit 110.And when acknowledgement bit when not setting (reset) (as being made as 0), then its corresponding storage element is invalid for not storing valid data or stored data as yet.

According to the above memory page management devices of narrating 100 of the present invention, when operation, mainly comprise following several main step:

The first, in when beginning, be preset value (for example, address date being set as 0) with the content setting of each storage element of data storing table, to avoid any correct comparison of uncertain data influence.

The second, the address of existing storage access and the content of data storing table are compared, to upgrade or replace the content of data storing table with decision.

The 3rd, finish not use at most (Least Recently Used is called for short LRU) and acknowledgement bit, to upgrade or be substituted to determine that storage element.

Please refer to Fig. 6, its expression is according to the operational flowchart of the memory page management devices of embodiments of the invention.

As shown in the figure, after the beginning,, accept the access address that the storer governor circuit is sent in step 610.

In step 612,, judge whether to choose the address value of certain storage element with the address value contrast of the access address that obtains and tables of data.

If the address value of certain storage element is chosen in the access address that obtains, then to step 614, send selected signal, arrive step 628 again, upgrade relevant LRU value, the LRU value that also is about to the storage element chosen is made as 0, and the LRU value of each storage element that will be littler than its former LRU value adds one respectively, to the step that finishes, finish the processing of existing access address then.

If the address value of any one storage element is not chosen in the access address that obtains,, in tables of data, find out storage element with maximum LRU value then to step 620.

In step 622, judge whether the VLD value of the storage element of being found out with maximum LRU value is effective.

If the VLD value of the storage element of being found out with maximum LRU value is for effective, represent that this storage element has stored effective address date, then to step 624, raw address is gone back in address value generation according to this storage unit stores, in order to close the memory page of the correspondence of having opened, then to step 626.

If the VLD value of the storage element with maximum LRU value that is found represents that this storage element does not store effective address date as yet, then directly to step 626 for invalid.

In step 626, put into the storage element that is found with maximum LRU value with rigidly connecting the existing access address of receiving.

In step 628, upgrade relevant LRU value, the LRU value of the storage element with maximum LRU value that also is about to be found is made as 0, and the LRU value of other storage element then adds one respectively.To the step that finishes, finish the processing of existing access address then.

For the above-described operating principle of clearer description, below will cooperate its operating process of figure explanation.

Please refer to Fig. 7 A to Fig. 7 G, it is represented to be the synoptic diagram of the operation of tables of data.In order to make explanation more succinct understandable, the tables of data in the diagram does not comprise all projects, as only represent the address of memory page and memory block with address value.Even so, existing this operator still should be able to understand, and its principle of operation is still consistent.

Please refer to Fig. 7 A, it is represented to open the beginning data for tables of data.The address value of all storage elements all is set at preset value, and all as shown in the figure address values all are set at 0, makes it when operation, can avoid because of existing uncertain address value to influence correct contrast in the tables of data.Because all address values all are useless, so the VLD value of all storage elements all is set at invalidly, all is made as 0 as shown in the figure.The LRU of each storage element then is set at unique LRU value, and as shown in the figure, storage element A～H is set at 7～0 respectively.

It is represented to please refer to Fig. 7 B, when the storer governor circuit carries out first time access to storer, the address value of supposing the memory page that it is sent is " 10 ", because this moment, all storage elements did not all use, so the LRU value is maximum storage element A in the option table, deposit the address in wherein address value hurdle, and set its VLD value, promptly change into 1 by 0, then affiliated LRU value is made as 0, and the LRU value less than 7 of other storage elements in the tables of data all added one, the LRU value that is about to storage element B～H all adds one.

It is represented to please refer to Fig. 7 C, when the storer governor circuit carries out second time access to storer, supposes that the address value of the memory page that it is sent is " 20 ".With the available data contrast in the tables of data, do not choose any data of tables of data.Therefore find out the maximum storage element of LRU value in the tables of data, promptly the LRU value is 7 storage element B, then address value is deposited in wherein, and set its affiliated VLD value, for example, from 0 original change 1, again the LRU value under it is made as 0, and all are added one less than 7 LRU value.

It is represented to please refer to Fig. 7 D, and after storer being carried out access for several times, the data of all storage elements in the tables of data are all effectively, last address value, the LRU value of tables of data, reaches the VLD value as shown in the figure.

Please refer to Fig. 7 E, when once more storer being carried out access, suppose that the address value of the memory page that it is sent is " 90 ".With the available data contrast in the tables of data, do not choose any data in the tables of data, therefore find out the maximum storage element of LRU value in the tables of data, be that the LRU value is 7 storage element A, then address value deposited in wherein that its VLD value was set originally, need not to set again, at last, the LRU value under it is made as 0, and all are added one less than 7 LRU value.Because the VLD value of storage element A was set originally, therefore be updated to new address value before, need the memory page of having opened to be closed according to original address value, for example, send precharge command and carry out precharge action.

Please refer to Fig. 7 F, when once more storer being carried out access, suppose that the address value of the memory page that it is sent is " 40 ".After the contrast of available data in the tables of data, determine to choose the address date of the storage element D in the tables of data, therefore need not change its address value and VLD value, only need to upgrade relevant LRU value, being about to its LRU value changes by original 5 and is made as 0, and with all LRU values less than other storage elements of 5, for example storage element A, D, F, G and H, affiliated LRU value adds one.

Please refer to Fig. 7 F, when CPU carried out access to storer once more, the address value of supposing the memory page that it is sent was " 22 ", supposed that itself and address value are that the memory page of " 20 " is in same memory block.Therefore after the address date contrast with the storage element B in address value " 22 " and the tables of data, be found to be block and choose (bank hit).Because in same memory block, at one time in, can only open a memory page.Therefore it is constant to keep its VLD value, but its address is updated to new address value " 22 ", and upgrades the LRU value of being correlated with, and promptly its original LRU value is 7, thus the LRU value under it is made as 0, and all are added one less than 7 LRU value.Wherein, before the new memory page of unlatching, must the memory page of having opened in the same memory block be closed according to original address value.

Please refer to Fig. 8 A to Fig. 8 D and Fig. 9 A to Fig. 9 B, it is represented to be the sequential chart of memory page management devices 100 of the present invention under the different operating situation.Wherein, therefore the operation of all circuit will be that benchmark is explained with clock signal DCLK in sequential chart all with reference to common clock signal DCLK.

It is represented to please refer to Fig. 8 A, the access (or in selected parts of VC-SDRAM (segment-hit)) that it is chosen for page or leaf, because its memory block reaches the information of the column address that has started and has been stored in the storage element of tables of data, therefore need not to change its address contents, only need to upgrade its LRU value, for example be made as 0.As shown in the figure, that supposes to be chosen is the data of storage element A, after the access address is sent, through after the contrast of contrast circuit 110, after period T 0, its output signal ONPAG and BKHIT are become noble potential, and the expression page or leaf chooses and block is chosen, then, after period T 7, PGCMP becomes noble potential, lives in order to the signal latch that contrast circuit 110 is sent, as the usefulness of Data Update.The variation of signal LRU-A after period T 9 is that the LRU value under the storage element A is made as 0.

It is represented to please refer to 8B, and it is chosen for block but memory page is not chosen the access context of (page-miss).Because in one of SDRAM memory block, at one time, only allow to start row (promptly opening a memory page), therefore according to the selected storage element that arrives in address that cooperates access action to send, wherein deposit need be updated to the address of this access corresponding to the address of the memory page of same storage block.As shown in the figure, after period T 0,, have only signal BKHIT to become noble potential by the signal that contrast circuit 110 is sent.At this moment, the address date of data-driven table is closed the memory page of having opened.Then, signal PGCMP becomes noble potential after period T 5, live in order to the signal latch that contrast circuit 110 is sent, and with the storage element of selecting to be chosen, and the memory page information that is used for upgrading the selected storage element that arrives.After period T 7, upgrade relevant LRU value, and after period T 10, cooperate signal PGUPD and PAG-A to come the information of updated stored page or leaf, and open required new memory page.

When carrying out the access of storer, after the data contrast of its address and tables of data, when its result does not choose the situation of (bank-miss) for block, then must be by looking for a storage element to deposit nearest used data in the tables of data, in this case, can be divided into two kinds of situations and discuss, cooperation figure is described below respectively.

It is represented to please refer to Fig. 8 C, and it is the unchecked access context of block, and still has untapped storage element in tables of data.Address by contrast circuit 110 contrast storage access, determine not choose the data of any one storage element, so signal ONPAG and BKHIT all do not change, after period T 1, PGCMP lives signal latch by signal, selects the storage element of VLD value for not setting again, according to foregoing mode of operation, must select the maximum storage element of LRU value, for example the LRU value is 7 storage element, this suppose selected to be storage element A.Then, after period T 4, cooperate signal PGUPD, the address date of signal PAG-A and BNK-A is write storage element A, simultaneously set its VLD value by signal VLD-A, pass through one-period again after, via signal LRU-A its LRU value is made as 0, the LRU value of simultaneously also that other are relevant storage element is upgraded, and the LRU value that is about to less than 7 all adds one.

It is represented to please refer to Fig. 8 D, and it is the unchecked access context of block, and the store data all of the storage element in the tables of data.When this situation, must not use the storage element of (LeastRecently Used is called for short LRU) to deposit new data by finding out in the tables of data at most, for example the LRU value is 7 storage element.As shown in the figure, address by contrast circuit 110 contrast storage access, determine not choose the data of any one storage element, so signal ONPAG and BKHIT all do not change, after period T 1, PGCMP lives signal latch by signal, and finds out the maximum storage element of LRU value, for example the LRU value is 7 storage element, supposes the selected storage element A that arrives.Before replacing original data of the selected storage element that arrives, must be first SDRAM be done the action of precharge (precharge), in order to close original memory block and secondary area piece (sub-bank) according to original memory block data with new value.This can use scanning flip-flop (flip flop) to reach, during the rising edge of the clock signal when signal PGCMP occurs, it is the rising edge of period T 7, the original data latching of the selected storage element that arrives is lived, reach the precharge command of time block with the memory block that produces signal LPGBK and LPGSB.Then, after period T 6, cooperate signal PGUPD, the data that signal PAG-A and BNK-A are sent write the selected storage element that arrives in the tables of data.And after period T 8, upgrade relevant LRU value, be about to selected to the LRU value of storage element be made as 0, and the LRU value of other all storage elements is added one.

For above mentioned signal LPGBK and LPGSB, have eight memory block in the supposing the system, then with the signal LPGBK[0:7 of eight bit widths] represent that wherein each bit is corresponding to a memory block, and signal LPGBK[0] first memory block of representative system.And, suppose to have in each memory block four time blocks, then with the signal LPGSB[1:0 of two bits] represent.When using VC-SDRAM, if the storage element data with existing of being chosen also need produce reduction (restore) information (RXPAG[27:11], RXsEG[1:0]) for reduction cycle (restore cycle).

Because in computer system, may use the storer of different types simultaneously, therefore must consider to cooperate the control mode of different storeies, on control mode, cooperated.When for example in computer system, using EDO/FP DRAM and SDRAM simultaneously, the signal CAS#[7:0 of 8 bit widths of EDO/FP DRAM] use with SDRMAM.In addition carry out DRAM upgrade (refresh) before, all memory block must idle in the spare time (idle) state, promptly passes through precharge.Web update signal PGFLH is used for acknowledgement bit is made as invalid (be about to corresponding VLD value be made as 0), the usefulness when switching to SDRAM in order to reach as the memory updating cycle by EDO/FP DRAM.Next matching timing figure discussion is switched to the situation of SDRAM by EDO/FP DRAM.

Please refer to Fig. 9 A, it is represented does not choose and access context will switch to SDRAM by EDO/FP DRAM the time for block.As shown in the figure, primary access is the data of access EDO/FP DRAM before supposing, when period T 1, according to previous access, cooperate signal PGUPD, deposit the address date of signal PAG-A and BNK-A in storage element A, and in period T 3, through signal LRU-A its LRU value is made as 0, signal VLD-A then remains setting.Then, signal PGCMP in period T 4 appearance, be access to SDRAM, after contrast circuit 110 contrasts, determine not choose the data of any one storage element, because during not the using of EDO/FP DRAM, therefore the memory page that can not be held open still deposits the data of this access with storage element A.After period T 5, signal PGFLH becomes noble potential, makes signal VLD-A become electronegative potential afterwards when period T 6, is used for closing EDO/FPDRAM, then, in period T 7, cooperate signal PGUPD, deposit the address information of the SDRAM of signal PAG-A and BNK-A in storage element A, and open required memory page, simultaneously when period T 8 signal VLD-A is reverted to noble potential, in order to its VLD value is set at effectively, its LRU value then is maintained 0.

Please shine Fig. 9 B, its represented access context for choosing the memory block of SDRAM and will switching to SDRAM by EDO/FPDRAM.As shown in the figure, primary access is the data of access EDO/FP DRAM before supposing, when period T 1,, cooperate signal PGUPD according to previous access, deposit the address date of signal PAG-A and BNK-A in storage element A, and in period T 3, through signal LRU-A its LRU value is made as 0, synchronous signal LRU-B also changes thereupon, for example the LRU value with storage element B adds one, and signal VLD-A then remains setting.Then, signal PGCMP in period T 3 appearance, be access, after contrast circuit 110 contrasts, determine the data that it chooses storage element B SDRAM, therefore after period T 5, directly upgrade relevant LRU value, promptly by signal LRU-B the LRU value of storage element B is made as 0, the LRU value littler than the original LRU value of storage element B then adds one, for example, via signal LRU-A the LRU value of storage element A is changed into 1 by 0.And after period T 5, signal PGFLH becomes noble potential, makes signal VLD-A become electronegative potential, in order to close EDO/FPDRAM.

As in the update cycle of storer, then different with situation about narrating previously, it is invalid the VLD value of all storage elements must to be made as, because all memory block all must be carried out precharge.After memory updating, the then principle operation of narrating by the front.In addition, when using VC-SDRAM, because it uses the auto-precharge order, so do not need to upgrade its relevant storage information.

According to the memory page management devices of above narration in order to track memory accesses, has following advantage, each access action via the trace memory governor circuit, not only can increase page or leaf chooses rate and data to share for the storer governor circuit, and can prejudge next streamline access (pipelined access) and whether need precharge, so can be when carrying out existing access, promptly send precharge command to give another memory block earlier, in order in advance another memory block is carried out precharge, can reduce the time delay of access.

Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any present technique field personnel, without departing from the spirit and scope of the present invention; when the change that can do a little and modification, so protection scope of the present invention is when being determined by accompanying Claim.

Claims (11)

1. memory page management devices in order to track memory accesses comprises:

One page buffering circuit has a plurality of storage elements, uses for the address date that stores a plurality of memory pages, and wherein each this storage element is deposited the address date of a memory page;

One contrast circuit, be connected to this page buffering circuit, in order to accept an access address, and according to the comparing result of the data of this access address and this page buffering circuit, export a selected signal, when one of the address date of these memory pages that store in this page buffering circuit was chosen in this access address, this selected signal was effect;

One utilization factor buffering circuit is connected to this page buffering circuit, in order to control the use situation of these storage elements; And

Whether one confirms circuit, is connected to this page buffering circuit, effective in order to the data of judging these storage elements;

Wherein this page buffering circuit comprises a data storing table, a latch cicuit, and these storage elements are arranged in this data storing table, and this latch cicuit is connected to this contrast circuit, latchs in order to this selected signal with this contrast circuit output.

2. the memory page management devices in order to track memory accesses as claimed in claim 1, wherein this page buffering circuit comprises that also one selects circuit, this selection circuit is connected to this latch cicuit, this utilization factor buffering circuit, this affirmation circuit, and this data storing table, in order to according to individual one of among these storage elements of this data storing table of output signal selection of this selected signal that latchs and this utilization factor buffering circuit and this affirmation circuit.

3. the memory page management devices in order to track memory accesses as claimed in claim 1, wherein also have a plurality of acknowledgement bits, each acknowledgement bit corresponds respectively to one of these storage elements, and when this acknowledgement bit was setting, the data that are stored in this corresponding storage element were only effectively.

4. the memory page management devices in order to track memory accesses as claimed in claim 3, wherein this contrast circuit judges according to these acknowledgement bits whether the data of these storage elements are effectively, and this contrast circuit also is responsible for upgrading the value of these acknowledgement bits.

5. the memory page management devices in order to track memory accesses as claimed in claim 4, wherein also have a plurality of utilization factor data, each utilization factor data is corresponding to one of these storage elements, in order to represent the utilization factor of these storage elements, this utilization factor buffering circuit is according to the use situation of these these storage elements of utilization factor Data Control, and responsible these utilization factor data of upgrading.

6. the memory page management devices in order to track memory accesses as claimed in claim 5, wherein these utilization factor data are with the digitized representation utilization factor, and the value of these utilization factor data is big more, represents corresponding of a specified duration more not being used of this storage element.

7. the memory page management devices in order to track memory accesses as claimed in claim 6, when the address date of these memory pages that store in these storage elements is not chosen in this access address, this access address is stored to this storage element corresponding to a peak use rate value.

8. the memory page management devices in order to track memory accesses as claimed in claim 7, when the affirmation bit corresponding to this storage element of this peak use rate data value when being effective, before this access address being stored to corresponding to this storage element of this peak use rate value, produce one according to the address date of this storage element and go back raw address, in order to reduce the state of one of corresponding memory page.

9. memory page management devices in order to track memory accesses, in order to accepting an access address, and an output one page selected signal and a block selected signal, this memory page management devices comprises:

One page buffering circuit has a plurality of storage elements, uses for the address date that stores a plurality of memory pages, and wherein each this storage element is deposited the address date of a memory page, and each this address date comprises block address data and one page address date;

One contrast circuit, be connected to this page buffering circuit, in order to accept an access address, and according to the comparing result of the data of this access address and this page buffering circuit, export this page selected signal and this block selected signal, when the block address data of one of address date of these memory pages that store in this page buffering circuit are chosen in this access address, this block selected signal is effect, when these block address data of one of address date of these memory pages that store in this page buffering circuit and this page address data were chosen in this access address, this block selected signal and this page selected signal acted on simultaneously;

One utilization factor buffering circuit, be connected to this page buffering circuit, in order to control the use situation of these storage elements, when the address date of these memory pages is not chosen in this access address,, and this is deposited the address deposit this untapped at most storage element in by finding out a untapped at most storage element in these storage elements according to this utilization factor buffering circuit; And

Whether one confirms circuit, is connected to this page buffering circuit, effective in order to the data of judging these storage elements,

Wherein this page buffering circuit comprises a data storing table, a latch cicuit, and these storage elements are arranged in this data storing table, and this latch cicuit is connected to this contrast circuit, latchs in order to this selected signal with this contrast circuit output.

10. the memory page management devices in order to track memory accesses as claimed in claim 9, when this access address choose these memory pages that store in this page buffering circuit one of address date the block address data but when not choosing these page address data, then upgrade this page address data according to this access address.

11. the memory page management method in order to track memory accesses comprises the following steps:

Provide a plurality of storage elements, in order to store the address date of a plurality of memory pages;

Accept an access address;

Address date contrast with this access address and these storage elements;

When the address date of one of these storage elements is chosen in this access address, send a selected signal;

When the address date of one of these storage elements is not chosen in this access address, find out a untapped at most storage element by these storage elements, deposit this access address in this untapped at most storage element; And

When this access address does not choose the address date of one of these storage elements and this untapped at most storage element to store effective address date, this access address is deposited in this at most untapped storage element before, produce a reduction address signal according to the original address date that stores of this untapped at most storage element, in order to reduce the state of one of corresponding memory page.

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