CN111969106A - Phase change memory device and method of manufacturing the same - Google Patents

Abstract

The invention discloses a phase change memory device and a method for manufacturing the same, comprising a stacked layer formed by alternately stacking a plurality of insulating layers and a plurality of memory layers on a substrate, and a first electrode penetrating through the stacked layer, wherein each memory layer comprises a heating electrode surrounding the first electrode, and a phase change layer surrounding the heating electrode. The annular laminated structure of the first electrode, the heating electrode and the phase change layer is separated by a plurality of insulating layers, and the storage layer can realize multi-layer stacking in the first longitudinal direction, so that the storage density is improved.

Description

A phase-change memory device and method of making the same

technical field

The present invention generally relates to the field of semiconductors, and in particular, to a phase-change memory device and a manufacturing method thereof.

Background technique

Compared with the current dynamic random access memory (DRAM) and flash memory (FLASH), phase change random access memory (PCRAM) has obvious advantages: its small size, low driving voltage, low power consumption, fast read and write speed, and non-volatile. Phase change memory is not only non-volatile memory, but also has the potential to be made into multi-machine storage, and is suitable for ultra-low temperature and high temperature environment, anti-irradiation, anti-vibration, so it will not only be widely used in daily portable electronic products, but also in aerospace. There are huge potential applications in the field. Especially, in portable electronic products, its high speed and non-volatile just make up for the deficiencies of flash memory (FLASH) and ferroelectric memory (FERAM). Intel Corporation has predicted that phase change memory will replace FLASH, DRAM and static random access memory (SRAM). In this case, it is more urgent to develop phase-change random access memory cell devices. The phase-change memory cell device at the nanometer scale is conducive to the rapid phase change of reversible phase-change thin film materials, and is also conducive to the improvement of the integration of the memory.

In order to improve the storage speed and demonstrate greater advantages than existing storage technologies, it is particularly important to prepare phase-change memory cells from phase-change thin-film materials to form two-dimensional or three-dimensional nanoscale memory cells with electrodes. More traditional research is on unit devices with electrodes and phase change materials connected vertically, and then the density of the device is increased by vertical stacking of unit devices, but the thermal efficiency utilization in this structure is very low, and only less than 1% of the heat is actually used for During the phase change, the rest of the heat is diffused in the bottom electrode and the dielectric layer, and the heat diffused in the bottom electrode accounts for about 70%. At the same time, the traditional phase-change memory unit can only achieve a two-layer stack structure, and the storage capacity can only reach 128Gb at most.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a phase change memory device and a manufacturing method thereof, aiming at improving the storage density of the phase change memory device and reducing heat dissipation at the same time.

In one aspect, the present invention provides a phase-change memory device, comprising:

substrate;

a stacked layer formed by alternately stacking a plurality of insulating layers and a plurality of storage layers on the substrate;

A first electrode penetrating the stacked layer in a first longitudinal direction perpendicular to the substrate;

Wherein, each of the storage layers includes a heating electrode surrounding the first electrode, and a phase change layer surrounding the heating electrode.

Further preferably, the first electrode is cylindrical.

Further preferably, the storage layer further includes a word line surrounding the phase change layer and extending in a first lateral direction parallel to the substrate.

Further preferably, it also includes a bit line electrically connected to the top of the first electrode.

Further preferably, it also includes a peripheral control circuit, the peripheral control circuit includes a transistor, the drain of the transistor is connected to the word line, and the source of the transistor is connected to the bit line.

In another aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:

provide a substrate;

forming a stacked layer formed by alternately stacking a plurality of insulating layers and a plurality of conductor layers on the substrate;

forming electrode vias through the stacked layers in a first longitudinal direction perpendicular to the substrate;

Each of the conductor layers is partially etched through the electrode through holes to leave a plurality of phase change spaces, and a plurality of phase change layers are deposited in the plurality of phase change spaces, one of the phase change layers is covered by a the conductor layer surrounds;

Each of the phase change layers is partially etched to leave a plurality of electrode spaces, and a plurality of heating electrodes are deposited in the plurality of electrode spaces, one of the heating electrodes is surrounded by one of the phase change layers and is connected to the plurality of electrode spaces. Electrode through hole handover;

A first electrode is formed in the electrode through hole, and the first electrode is surrounded by a plurality of the heating electrodes.

Further preferably, the first electrode is cylindrical.

Further preferably, after the conductor layers are partially etched, word lines surrounding the phase change layer are formed in a first lateral direction parallel to the substrate.

Further preferably, it also includes: forming a bit line electrically connected to the top of the first electrode.

Further preferably, it also includes forming a peripheral control circuit, the peripheral control circuit includes a transistor, the drain of the transistor is connected to the word line, and the source of the transistor is connected to the bit line.

The beneficial effects of the present invention are: to provide a phase-change memory device and a manufacturing method thereof, including a stack layer formed by alternately stacking a plurality of insulating layers and a plurality of storage layers on a substrate; The first longitudinal direction runs through the first electrodes of the stacked layers, wherein each of the storage layers includes a heater electrode surrounding the first electrode, and a phase change layer surrounding the heater electrode. The lateral stacked structure of the first electrode, the heating electrode and the phase change layer is isolated by the insulating layer, which can reduce the size of the storage unit and reduce heat dissipation. The storage unit is vertically stacked in multiple layers, which can improve the storage density .

Description of drawings

The technical solutions and other beneficial effects of the present invention will be apparent through the detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

1 is a schematic longitudinal cross-sectional view of a phase change memory device provided by an embodiment of the present invention;

Figure 2a is a schematic cross-sectional view of a phase change memory device provided by an embodiment of the present invention along the AA' plane;

Figure 2b is a schematic cross-sectional view of the phase change memory device provided by an embodiment of the present invention along the BB' plane;

3 is a schematic flowchart of a method for manufacturing a phase change memory device provided by an embodiment of the present invention;

4a is a schematic longitudinal cross-sectional view of the phase change memory device after step S3 is completed;

4b is a schematic longitudinal cross-sectional view of the phase change memory device after step S4 is completed;

4c is a schematic longitudinal cross-sectional view of the phase change memory device after step S5 is completed;

FIG. 4d is a schematic longitudinal cross-sectional view of the phase change memory device after step S6 is completed.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

It should be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and similarly, a second component could be termed a first component, without departing from the scope of the present invention.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar fashion.

As used herein, the term "layer" refers to a portion of material having a region of thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers above and/or below it. Layers may include multiple layers, eg, interconnect layers may include one or more conductor and contact layers and one or more dielectric layers.

As used herein, the term "memory device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate. As used herein, the term "vertically/perpendicularly" refers nominally to a lateral surface perpendicular to the substrate.

It should be noted that the drawings provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic way, although the drawings only show the components related to the present invention rather than the number and shape of the components in actual implementation. and size drawing, the type, quantity and proportion of each component may be changed at will in actual implementation, and the component layout may also be more complicated.

Please refer to FIG. 1. FIG. 1 is a schematic longitudinal cross-sectional view of a phase change memory device provided by an embodiment of the present invention. The phase change memory device 10 includes a substrate 11 , a stack layer 14 formed by alternately stacking a plurality of insulating layers 12 and a plurality of memory layers 13 on the substrate 11 , and a first longitudinal direction perpendicular to the substrate 11 penetrating the stack The first electrode 15 of the layer 14 . Wherein, each storage layer 13 includes a heating electrode 131 surrounding the first electrode 15 and a phase change layer 132 surrounding the heating electrode 131 .

The substrate 11 may be a semiconductor material, the insulating layer 12 may be an insulating material such as silicon oxide, the material of the first electrode 15 may be tungsten or other metal materials, and the heating electrode 131 may be a good conductive material, such as W, TiN, etc. It mainly plays the role of conducting and heating the phase change material. Materials for phase change layer 132 include materials such as chalcogenide-based materials that include the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) that form part of Group VIA of the periodic table. ) any of them. Materials of the phase change layer 132 are, for example, compounds of chalcogens with more electropositive elements or radicals, combinations of chalcogenides with other materials such as transition metals, and chalcogenide alloys. Chalcogenide alloys typically contain one or more elements from Group IVA of the Periodic Table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include one or a combination of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Numerous phase-change based memory materials have been described in the technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb /Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb /S.

In this embodiment, the storage layer 13 may further include word lines 133 surrounding the phase change layer 132 . The word lines 133 extend parallel to the first lateral direction of the substrate 11 and generally have a rectangular cross-section.

In this embodiment, the memory device 10 further includes a bit line 16 that is electrically connected to the top of the first electrode 15 , which can be electrically connected through a metal plug 161 .

In this embodiment, the phase change memory device 10 further includes a peripheral control circuit (not shown in the figure), the peripheral control circuit includes a transistor, the drain of the transistor is connected to the word line 133 , and the source of the transistor is connected to the word line 133 . bit line 16. Specifically, a high level (such as 3.3V) is applied to the drain, and a control signal is applied to the gate of the transistor to make the drain and source conduct, and the current flows from the drain to the first electrode 15 through the bit line 16, and is heated The electrode 131 and the phase change layer 132 (in the direction of the solid line with the arrow as shown in FIG. 1 ) flow to the word line 133 and finally to the source electrode. The heating electrode 131 will heat the phase change layer 132. Since the material of the phase change layer 132 has reversible phase change characteristics, storage can be realized by using its high resistance characteristics in amorphous state and low resistance characteristics in crystalline state.

Wherein, the word line 133 and the bit line 16 may be perpendicular to different planes, or may be parallel to different planes or intersect at a certain angle on different planes.

Please refer to FIG. 2a. FIG. 2a is a schematic cross-sectional view of the phase change memory device provided by the embodiment of the present invention along the AA' plane. The first electrode 15 of the phase change memory device 10 is preferably cylindrical, and the heating electrode 131 surrounds the first electrode. 15. The annular structure of the sidewall, the phase change layer 132 is an annular structure surrounding the sidewall of the heating electrode 131, and the transverse cross-section of the word line 133 is a rectangle. The fork on the first electrode 15 indicates that the direction of the heating current is toward the page and inward.

In other embodiments, the first electrode 15 may be other columnar structures, and its transverse cross section may be other shapes, such as a square or a rectangle.

Please refer to FIG. 2b. FIG. 2b is a schematic cross-sectional view of the phase change memory device provided by the embodiment of the present invention along the BB' plane. The insulating layer 12 surrounds the first electrode 15 , and the first electrode 15 can serve as a common electrode of the plurality of memory cells, and the insulating layer 12 can isolate the plurality of memory layers 13 .

The phase change memory device 10 provided by the embodiment of the present invention stacks multiple storage layers 13 in the first vertical direction, and the multiple storage layers 13 are isolated by the insulating layer 12 without affecting each other, and a phase change memory with high storage density can be realized. Each of the storage layers 13 includes a heating electrode 131 surrounding the first electrode 15 and a phase change layer 132 surrounding the heating electrode 131 . The phase change unit of the annular stacked structure can reduce heat dissipation, thereby reducing energy consumption.

The embodiment of the present invention also provides a method for manufacturing the above-mentioned phase-change memory device 10 , so the structure numbers of the phase-change memory device 10 are referenced in the steps of the manufacturing method. FIG. 3 is a schematic flowchart of a method for manufacturing a phase change memory device according to an embodiment of the present invention. The method for manufacturing a phase change memory device includes the following steps S1-S6.

Step S1 : providing the substrate 11 .

Step S2: On the substrate 11, a stacked layer 14' formed by alternately stacking a plurality of insulating layers 12 and a plurality of conductor layers 13' is formed.

Wherein, the insulating layer 12 can be made of silicon oxide or the like, and the conductor layer 13' can be made of metal such as tungsten. The deposition methods of the insulating layer 12 and the conductor layer 13' may be, but are not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atom Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD) such as thermal Various methods such as oxidation, evaporation, sputtering, etc. The number of pairs of insulating layers 12/conductor layers 13' in the stacked layer 14' can be 32, 64, 96, 128 or more, and the specific number can be set according to actual needs, which is not limited here.

Step S3: forming an electrode through hole 141 penetrating the stacked layer 14' in the first longitudinal direction perpendicular to the substrate 11.

For example, the electrode through holes 141 may be formed using a photolithography process and an etching process. The structure of the phase change memory device after step S3 is completed is shown in FIG. 4a.

Step S4: Partially etch each conductor layer 13' through the electrode through holes 141 to vacate a plurality of phase change spaces, and deposit a plurality of phase change layers 132 in the plurality of phase change spaces, one phase change layer 132 is A conductor layer 13' surrounds.

The phase change space may be formed by an etching process, and then the phase change layer 132 may be formed by a deposition process. The structure of the phase change memory device after step S4 is completed is shown in FIG. 4b. In this embodiment, the portion of the conductor layer 13' left after being etched forms the word line 133. The word lines 133 extend parallel to the first lateral direction of the substrate 11 and surround the phase change layer 132 .

Step S5: Partially etch each phase change layer 132 to vacate a plurality of electrode spaces, and deposit a plurality of heating electrodes 131 in the plurality of electrode spaces. One heating electrode 131 is surrounded by a phase change layer 132 and is connected to the electrode space. The through holes 141 are handed over.

The electrode space may be formed by an etching process, and then the heating electrode 131 may be formed by a deposition process. The structure of the phase change memory device after step S5 is completed is shown in FIG. 4c.

Step S6 : the first electrode 15 is formed in the electrode through hole 141 , and the first electrode 15 is surrounded by the plurality of heating electrodes 131 .

The first electrode 15 can be formed by the above-mentioned deposition method, and the material of the first electrode 15 can be tungsten or other metal materials. The structure of the phase change memory device after step S6 is completed is shown in FIG. 4d .

Please continue to refer to FIG. 1 , after step S6 , it also includes forming a bit line 16 electrically connected to the top of the first electrode 15 . Specifically, a dielectric layer 17 can be formed on the stacked layer 14 , and then a metal plug 161 connected to the top of the first electrode 15 is formed in the dielectric layer 17 , and then a bit line 16 is formed on the dielectric layer 17 . The first electrode 15 It is electrically connected to the bit line 16 through a metal plug 161 . The formed phase change memory device is shown in FIG. 1 , and the heating electrode 131 , the phase change layer 132 and the word line 133 form the memory layer 13 shown in FIG. 1 .

In this embodiment, the manufacturing method further includes forming a peripheral control circuit (not shown in the figure), the peripheral control circuit includes a transistor, the drain of the transistor is connected to the word line 133, and the source of the transistor is connected to the bit Line 16.

In other embodiments, steps S4 and S5 may be replaced by the following steps: partially etching each conductor layer 13 ′ through the electrode through holes 141 to vacate a plurality of storage spaces, and sequentially depositing all the storage spaces in each storage space. The phase change layer 132 surrounded by the conductor layer 13 ′ and the heating electrode 131 surrounded by the phase change layer 132 . The heating electrode 131 is connected to the electrode through hole 141 . At this time, the time and rate control of the deposition process is more demanding.

In the method for manufacturing a phase change memory device provided by the embodiment of the present invention, firstly, a stacked layer 14' is formed by alternately stacking insulating layers 12 and conductor layers 13', and then the conductor layer 13' is formed by etching and depositing through electrode through holes 141. The word line 133, the phase change layer 132 surrounded by the word line 133, and the heating electrode 131 surrounded by the phase change layer 132, and finally the first electrode 15 is formed in the electrode through hole 141, so that the heating electrode 131 surrounds the first electrode 15, The formed annular stacked structure can reduce heat dissipation, and each storage layer 13 is isolated by the insulating layer 12 without affecting each other. The manufacturing method is simple, the cost is reduced, and the phase change memory device with high storage density can also be manufactured.

The descriptions of the above embodiments are only used to help understand the technical solutions of the present invention and their core ideas; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or modify some of the technical solutions. The features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A phase change memory device, comprising:

a substrate;

a stack layer formed by alternately stacking a plurality of insulating layers and a plurality of memory layers on the substrate;

a first electrode penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;

wherein each of the memory layers includes a heater electrode surrounding the first electrode, and a phase change layer surrounding the heater electrode.

2. The phase-change memory device as claimed in claim 1, wherein the first electrode has a cylindrical shape.

3. The phase-change memory device as claimed in claim 1, wherein the memory layer further comprises word lines surrounding the phase-change layer and extending in a first lateral direction parallel to the substrate.

4. The phase-change memory device as claimed in claim 3, further comprising a bit line electrically connected to a top portion of the first electrode.

5. The phase-change memory device as claimed in claim 4, further comprising a peripheral control circuit including a transistor having a drain connected to the word line and a source connected to the bit line.

6. A method of manufacturing a phase change memory device, comprising:

providing a substrate;

forming a stacked layer in which a plurality of insulating layers and a plurality of conductor layers are alternately stacked on the substrate;

forming an electrode via hole penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;

partially etching each conductor layer through the electrode through holes to form a plurality of phase change spaces, and depositing a plurality of phase change layers in the plurality of phase change spaces, wherein one phase change layer is surrounded by one conductor layer;

partially etching each phase change layer to form a plurality of electrode spaces, depositing a plurality of heating electrodes in the electrode spaces, wherein one heating electrode is surrounded by one phase change layer and is connected with the electrode through hole;

forming a first electrode in the electrode through-hole, the first electrode being surrounded by the plurality of heating electrodes.

7. The method of manufacturing a phase-change memory device according to claim 6, wherein the first electrode has a cylindrical shape.

8. The method of manufacturing a phase-change memory device as claimed in claim 6, wherein the conductor layers partially etched for each of the conductor layers are formed with word lines surrounding the phase-change layer in a first lateral direction parallel to the substrate.

9. The method of manufacturing a phase-change memory device according to claim 8, further comprising: forming a bit line electrically connected to a top of the first electrode.

10. The method of manufacturing a phase-change memory device according to claim 9, further comprising forming a peripheral control circuit including a transistor having a drain connected to the word line and a source connected to the bit line.

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