CN111968692B - Circuit and chip for reducing area of column redundancy replacement circuit - Google Patents
Circuit and chip for reducing area of column redundancy replacement circuit Download PDFInfo
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- CN111968692B CN111968692B CN202011141934.9A CN202011141934A CN111968692B CN 111968692 B CN111968692 B CN 111968692B CN 202011141934 A CN202011141934 A CN 202011141934A CN 111968692 B CN111968692 B CN 111968692B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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Abstract
The invention discloses a circuit and a chip for reducing the area of a column redundancy replacement circuit, wherein the circuit comprises a control circuit for controlling read-write erasing after the column redundancy replacement is finished and a decoding circuit for replacing column redundancy information, the column redundancy information decoding circuit is divided into a column redundancy information pre-decoding circuit and a column redundancy replacement information secondary decoding circuit, and the column redundancy replacement information secondary decoding circuit is dispersed into each sensitive amplifier, so that wiring traversing the left and right of the chip is greatly reduced, the area of the column redundancy replacement circuit is obviously reduced, the cost increase brought to the area of the chip by adding the column redundancy replacement circuit is reduced, and the yield of chip testing can be improved.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a circuit and a chip for reducing the area of a column redundancy replacement circuit.
Background
With the process of semiconductor chip process being increasingly reduced, the characteristics of the memory cells in the nonvolatile memory chip are more difficult to control, defects are more easily introduced in the chip manufacturing process to cause the characteristics of the memory cells to be poor, although the characteristics of only a few memory cells are often poor, in order to ensure the reliability and the durability of the memory chip, the chip is screened out as long as the memory cells with the erasing performance or the reliability possibly risking are found in the wafer test and the packaging test process, but the loss of the test yield is brought along, and the cost of the chip is increased.
In order to reduce the screening rate of the whole chip (increase the yield of chip test and reduce the cost of chip) due to the possible defect of poor erasing performance or reliability of a few memory cells, column redundancy replacement is the main solution of the current mainstream nonvolatile memory manufacturers, and replaces the memory cells with poor erasing performance or reliability risk of the main memory region by using column redundancy, thereby achieving the purpose of increasing the yield, but the circuit design of column redundancy replacement also increases the area of the chip, if the circuit design of column redundancy replacement is not reasonable, the excessive chip area is increased, even if the yield of wafer test and packaging chip test of the nonvolatile memory chip is increased by column redundancy replacement, if the yield increase rate is lower than the rate of the increase of the chip area due to the newly increased column redundancy replacement circuit design, but rather further increases the cost of the non-volatile memory chip. The area reduction work of the column redundancy replacement circuit is necessary and valuable for reducing the cost of the nonvolatile memory chip.
Compared with the prior art, the design of the common column redundancy replacement circuit is mainly composed of two parts, wherein one part is a decoding circuit for column redundancy replacement information, and the other part is a circuit for controlling read-write erasing after the completion of the column redundancy replacement.
Taking serial NOR Flash as an example, in order to increase the speed of data reading, 128 sense amplifiers corresponding to main memory region bit lines inside a chip are usually set, 1 sense amplifier corresponding to column redundancy bit lines is usually set, and fig. 1 illustrates the corresponding relationship between main memory region bit lines, column redundancy bit lines and corresponding sense amplifiers by taking main memory region 8192 bit lines and column redundancy 64 bit lines as examples.
As can be seen from fig. 1, the main storage area 8192 bit lines and the column redundancy area 64 bit lines become 128 main storage area secondary bit lines and 1 column redundancy secondary bit line after passing through the bit line gating circuit, and correspond to the corresponding sense amplifier (the sense amplifier is abbreviated as SA in fig. 1, and is an abbreviation of sense amplifier), respectively, and whether the corresponding memory cell stores data 1 or data 0 is detected by the sense amplifier.
For example, 8192 main memory bit lines and 64 column redundancy bit lines in fig. 1, a common decoding circuit for column redundancy replacement information is to send information whether data detected by a sense amplifier corresponding to one column redundancy bit line replaces data detected by a sense amplifier corresponding to one bit line of a main memory to 128 main memory bit line sense amplifiers (since the number of the sense amplifiers corresponding to one bit line of the main memory is usually set to 128), that is, the column redundancy replacement information decoding circuit needs to output 128 flag signals whether to replace to 128 main memory bit line sense amplifiers.
As shown in fig. 2, it is a schematic diagram of decoding circuit and physical layout wiring of the column redundancy replacement information of the scheme of fig. 1. As can be seen from fig. 2, the traces of the 128 signal lines marked for replacement or not in this scheme occupy more chip area, the chip area occupied by these traces also accounts for the column redundancy circuit area, because the 128 sense amplifiers are uniformly distributed and occupy the lateral width of the chip, if the signals marked for replacement or not in 128 signal lines traverse the width direction of the chip, the chip area is increased, for the medium-low capacity serial NOR Flash, because the chip area is smaller, for the 8Mbit serial NOR Flash, the area ratio of the 128 metal traces and the mutual spacing increase chip is 1.0% -1.5%, which is really too large for the 8Mbit serial NOR Flash without adding the column redundancy replacement function (the test yield of the 8Mbit serial NOR Flash without adding the column redundancy replacement function is usually about 96%).
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a circuit and a chip for reducing the area of a column redundancy replacement circuit, and aims to solve the problems that the area of the column redundancy replacement circuit is too large due to too many transverse wires of the conventional chip, the yield of chip testing cannot be improved, and the cost of the chip cannot be reduced at the same time.
The technical scheme of the invention is as follows: a circuit for reducing the area of a column redundancy replacement circuit comprises a control circuit for controlling read-write erasing after column redundancy replacement is completed and a decoding circuit for replacing column redundancy information, wherein the decoding circuit comprises a pre-decoding circuit for pre-decoding the column redundancy information and a secondary decoding circuit for replacing the column redundancy information, the number of the secondary decoding circuits is consistent with the number of sensitive amplifiers on bit lines of a chip main storage area which need column redundancy replacement, each secondary decoding circuit corresponds to one sensitive amplifier on the bit lines of a chip main storage area one by one, and each secondary decoding circuit is arranged in one sensitive amplifier on the bit lines of the chip main storage area.
The circuit for reducing the area of the column redundancy replacement circuit is characterized in that the secondary decoding circuit comprises a first three-input AND gate, a second three-input AND gate and a third three-input AND gate, the output end of the first three-input AND gate is connected with a corresponding sensitive amplifier on a bit line of a main storage area of a chip, the first input end of the first three-input AND gate is connected with the output end of the second three-input AND gate, the second input end of the first three-input AND gate is connected with the output end of the third three-input AND gate, and the third input end of the first three-input AND gate is connected with the pre-decoding circuit; the first input end, the second input end and the third input end of the second three-input AND gate are all connected with the pre-decoding circuit, and the first input end, the second input end and the third input end of the third three-input AND gate are all connected with the pre-decoding circuit.
The circuit for reducing the area of the column redundancy replacement circuit comprises a predecoding circuit and a decoding circuit, wherein the predecoding circuit comprises a first NOT gate and a second NOT gate, the output end of the first NOT gate is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with a corresponding second-stage decoding circuit, the output end of the first NOT gate is connected with a corresponding second-stage decoding circuit, and the input end of the first NOT gate is connected with an input/output port.
The circuit for reducing the area of the column redundancy replacement circuit is characterized in that the sense amplifier comprises a third NOT gate and a fourth NOT gate, the output end of the third NOT gate is connected with the input end of the fourth NOT gate, and the input end of the third NOT gate is connected with the output end of the first three-input AND gate.
The circuit for reducing the area of the column redundancy replacement circuit is characterized in that the sense amplifier further comprises a sense amplifier SA, a latch SA _ latch of the sense amplifier SA, a first control switch and a second control switch, wherein one end of the first control switch is connected with the latch SA _ latch, and the other end of the first control switch is connected with the data output end of the sense amplifier; one end of the second control switch is connected with the redundant information input, and the other end of the second control switch is connected with the data output end of the sensitive amplifier; the switch of the first control switch is controlled by the output result of the output end of the fourth NOT gate, and the switch of the second control switch is controlled by the output result of the output end of the third NOT gate.
A chip comprising a circuit for reducing the area of a column redundancy replacement circuit as claimed in any one of the preceding claims.
The invention has the beneficial effects that: the invention provides a circuit and a chip for reducing the area of a column redundancy replacement circuit, wherein the circuit comprises a control circuit for controlling read-write erasing after the column redundancy replacement is finished and a decoding circuit for replacing column redundancy information, the column redundancy information decoding circuit is divided into a column redundancy information pre-decoding circuit and a column redundancy replacement information secondary decoding circuit, and the column redundancy replacement information secondary decoding circuit is dispersed into each sensitive amplifier, so that wiring traversing the left and right of the chip is greatly reduced, the area of the column redundancy replacement circuit is obviously reduced, the cost increase brought to the area of the chip by adding the column redundancy replacement circuit is reduced, and the yield of chip testing can be improved.
Drawings
FIG. 1 is a diagram illustrating the correspondence between bit lines and sense amplifiers of a NOR Flash memory in the prior art.
Fig. 2 is a schematic diagram of a decoding circuit and physical layout wiring of column redundancy replacement information in the prior art.
Fig. 3 is a schematic diagram of a circuit for reducing the area of the column redundancy replacement circuit in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 3, a circuit for reducing the area of a column redundancy replacement circuit includes a control circuit for controlling reading and writing after column redundancy replacement is completed and a decoding circuit for replacing column redundancy information, where the decoding circuit includes a pre-decoding circuit for pre-decoding column redundancy information and a secondary decoding circuit for replacing column redundancy information, the number of the secondary decoding circuits is the same as the number of sense amplifiers on bit lines of a chip main storage area that need column redundancy replacement, each secondary decoding circuit corresponds to one sense amplifier on the bit lines of the chip main storage area one by one, and each secondary decoding circuit is disposed in one sense amplifier on the bit lines of the chip main storage area.
In some embodiments, the secondary decoding circuit includes a first three-input and gate, a second three-input and gate, and a third three-input and gate, an output terminal of the first three-input and gate is connected to a corresponding sense amplifier on a bit line of the main storage area of the chip, a first input terminal of the first three-input and gate is connected to an output terminal of the second three-input and gate, a second input terminal of the first three-input and gate is connected to an output terminal of the third three-input and gate, and a third input terminal of the first three-input and gate is connected to the predecoding circuit; the first input end, the second input end and the third input end of the second three-input AND gate are all connected with the pre-decoding circuit, and the first input end, the second input end and the third input end of the third three-input AND gate are all connected with the pre-decoding circuit.
In some specific embodiments, the predecoding circuit includes a first not gate and a second not gate, an output end of the first not gate is connected with an input end of the second not gate, an output end of the second not gate is connected with a corresponding secondary decoding circuit, an output end of the first not gate is connected with a corresponding secondary decoding circuit, and an input end of the first not gate is connected with an input/output port.
In some embodiments, the sense amplifier comprises a third not gate and a fourth not gate, wherein an output terminal of the third not gate is connected with an input terminal of the fourth not gate, and an input terminal of the third not gate is connected with an output terminal of the first three-input and gate.
In some embodiments, the sense amplifier further includes a sense amplifier SA and a latch SA _ latch thereof, a first control switch and a second control switch, one end of the first control switch is connected to the latch SA _ latch, and the other end of the first control switch is connected to the sense amplifier data output terminal; one end of the second control switch is connected with the redundant information input, and the other end of the second control switch is connected with the data output end of the sensitive amplifier; the switch of the first control switch is controlled by the output result of the output end of the fourth NOT gate, and the switch of the second control switch is controlled by the output result of the output end of the third NOT gate.
In the technical scheme, the column redundancy information decoding circuit module is split into the column redundancy information pre-decoding circuit and the column redundancy replacement information secondary decoding circuit, and the column redundancy replacement information secondary decoding circuit is dispersed into each sense amplifier, so that the wiring crossing the left and right of the chip is greatly reduced. Also taking 8192 main memory region bit lines and 64 column redundancy region bit lines as an example, if the circuit for reducing the area of the column redundancy replacement circuit is adopted, the number of the traces traversing the left and right of the chip is changed from 128 in the prior art to 14.
According to the technical scheme, the secondary decoding circuit is additionally arranged in the sensitive amplifier on the bit line of the main storage area of the chip to replace a physical connection line between column redundancy replacement information decoding circuits in the prior art, and the length of the connection line between the secondary decoding circuit and the sensitive amplifier on the bit line of the main storage area of the chip is very short, so that the extra obvious occupation of the area of the chip is avoided, and the secondary decoding circuit can be ignored.
Compared with a common column redundancy replacement circuit method, the circuit for reducing the area of the column redundancy replacement circuit has 14 wires crossing the left and right of the chip, the number of the wires is about 11% of that of the wires in the traditional method, the wires crossing the left and right of the chip are greatly reduced, the area of the column redundancy replacement circuit is obviously reduced, and the cost increase caused by the increase of the column redundancy replacement circuit to the area of the chip is reduced.
The technical scheme also protects a chip which comprises the circuit for reducing the area of the column redundancy replacement circuit.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (4)
1. A circuit for reducing the area of a column redundancy replacement circuit is characterized by comprising a control circuit for controlling read-write erasing after column redundancy replacement is finished and a decoding circuit for replacing column redundancy information, wherein the decoding circuit comprises a pre-decoding circuit for pre-decoding the column redundancy information and a secondary decoding circuit for replacing the column redundancy information, the number of the secondary decoding circuits is consistent with the number of sensitive amplifiers on bit lines of a chip main storage area which need column redundancy replacement, each secondary decoding circuit corresponds to one sensitive amplifier on the bit lines of a chip main storage area one by one, and each secondary decoding circuit is arranged in one sensitive amplifier on the bit lines of the chip main storage area;
the input end of each secondary decoding circuit is connected with the output end of the pre-decoding circuit through a plurality of wires;
the second-stage decoding circuit comprises a first three-input AND gate, a second three-input AND gate and a third three-input AND gate, wherein the output end of the first three-input AND gate is connected with a corresponding sensitive amplifier on a bit line of a main storage area of the chip; the first input end, the second input end and the third input end of the second three-input AND gate are connected with the pre-decoding circuit;
the predecoding circuit comprises a first NOT gate and a second NOT gate, wherein the output end of the first NOT gate is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with a corresponding secondary decoding circuit, the output end of the first NOT gate is connected with a corresponding secondary decoding circuit, and the input end of the first NOT gate is connected with the input/output port.
2. The circuit for reducing the area of a column redundancy replacement circuit according to claim 1, wherein the sense amplifier comprises a third not gate and a fourth not gate, wherein an output terminal of the third not gate is connected with an input terminal of the fourth not gate, and an input terminal of the third not gate is connected with an output terminal of the first three-input and gate.
3. The circuit for reducing the area of column redundancy replacement circuit according to claim 2, wherein the sense amplifier further comprises a sense amplifier SA and its latch SA _ latch, a first control switch and a second control switch, one end of the first control switch is connected to the latch SA _ latch, and the other end of the first control switch is connected to the sense amplifier data output terminal; one end of the second control switch is connected with the redundant information input, and the other end of the second control switch is connected with the data output end of the sensitive amplifier; the switch of the first control switch is controlled by the output result of the output end of the fourth NOT gate, and the switch of the second control switch is controlled by the output result of the output end of the third NOT gate.
4. A chip comprising a circuit for reducing the area of a column redundancy replacement circuit according to any one of claims 1 to 3.
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| CN202011141934.9A CN111968692B (en) | 2020-10-22 | 2020-10-22 | Circuit and chip for reducing area of column redundancy replacement circuit |
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| CN202011141934.9A CN111968692B (en) | 2020-10-22 | 2020-10-22 | Circuit and chip for reducing area of column redundancy replacement circuit |
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| CN113569517B (en) * | 2021-06-29 | 2024-02-23 | 南方电网科学研究院有限责任公司 | Circuit and chip for reducing area of column redundancy replacement circuit |
| CN114297005A (en) * | 2021-12-29 | 2022-04-08 | 成都博尔微晶科技有限公司 | Small-area and repeated row redundancy replacement method for Norflash |
| WO2025111800A1 (en) * | 2023-11-28 | 2025-06-05 | 长江存储科技有限责任公司 | Memory apparatus, system, and decoding circuit |
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| US7330369B2 (en) * | 2004-04-06 | 2008-02-12 | Bao Tran | NANO-electronic memory array |
| KR101100958B1 (en) * | 2010-09-06 | 2011-12-29 | 주식회사 하이닉스반도체 | Nonvolatile memory device |
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| CN101563675A (en) * | 2006-12-15 | 2009-10-21 | 爱特梅尔公司 | A new implementation of column redundancy for a flash memory with a high write parallelism |
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