CN111966571B - Co-processing Method for Time Estimation Based on ARM-FPGA Coprocessor Heterogeneous Platform - Google Patents

Abstract

The invention discloses a time estimation cooperative processing method based on an ARM-FPGA coprocessor heterogeneous platform, which is applied to a scene that a big data storage unit and a computing unit are separated. The high-performance hardware FPGA coprocessor is deployed in the storage unit through the AXI protocol interface, so that the data processing capacity of the storage unit node is enhanced, and calculation power is provided for preprocessing of mass data. When the redundant information in the source data is too small, if the source data preprocessing is performed again, the data interaction time and the data preprocessing time of the storage unit are increased, and the time delay problem of the whole process cannot be reasonably reduced. Therefore, the pre-processing amount of the source data is estimated in a probability mode, so that whether the data pre-processing is needed or not is determined. And the time spending in the whole process is estimated by a time estimation method, wherein the estimated time spending comprises the sum of time delays of source data extraction, transmission communication, calculation and the like. And finally, selecting a proper processor to perform data processing, so that the efficiency is maximized, and the overall performance of the system is improved.

Description

Co-processing Method for Time Estimation Based on ARM-FPGA Coprocessor Heterogeneous Platform

technical field

The invention belongs to the technical field of distributed computing for heterogeneous platform cooperative processing, in particular to a time-predictable collaborative processing method based on ARM-FPGA coprocessor heterogeneous system.

Background technique

The explosive growth of data volume in the era of big data has led to a lot of redundant and invalid information in massive big data. In the big data system scenario where the data storage unit and the computing unit are separated, how to efficiently perform data preprocessing in the face of massive data and remove redundant data, so as to save data storage nodes, reduce data communication delay and improve data availability , is a problem worthy of attention. In traditional data processing, high-performance processors or multiple processors are used for online processing to meet the needs of big data processing. With the constraints of Moore's Law, the improvement of the main frequency of processors under different architectures is greatly limited, and driven by the amount of information in the data explosion, based on ARM processors and high-performance new hardware (GPU, field programmable gate array) Synergistic hybrid architectures, which have received extensive attention from researchers, have become the focus of this field.

The ARM processor has a dual instruction set, uses a large number of registers, executes instructions faster, has flexible addressing modes, and has high execution efficiency. It has the characteristics of small size, low power consumption, low cost, high performance, etc., and is widely used in embedded systems. The processor has the advantage of parallel processing in the execution of program tasks. However, the complexity of program logic also limits the parallelism of program execution instructions, and it is difficult to achieve overloaded multi-threading. With the complexity of massive data and structure, it is unrealistic to rely on only one processing, and the data calculation pressure of the processor is shared by equipped with co-processors. As a programmable logic device of a semi-defined circuit, FPGA can formulate any logic function through programmable features. It has outstanding advantages such as efficient programming, short development cycle, parallel computing and low power consumption. These characteristics make data processing faster and more real-time, which cannot be achieved by many new hardware.

Therefore, FPGA is used as a heterogeneous platform equipped with a coprocessor, software and hardware are co-processed, and redundant data is removed through preprocessing of massive data, so as to reduce the amount of data transmitted between nodes, the communication delay between each other and save data Space to store nodes. It can effectively deal with problems such as opening distribution and transmission time. However, during data preprocessing, there may be little redundancy in preprocessing data information, but data preprocessing will process the entire data, which cannot effectively reduce data internal communication traffic, network transmission delay, and calculation processing time, and the gain outweighs the gain. Therefore, in the application scenario where the source data storage and computing nodes are separated, how to predict and judge the task in advance when processing massive data on heterogeneous platforms is based on the time and computing characteristics of different processors, so that the data computing nodes are in different Reasonable allocation among processors, further reducing data preprocessing calculation time and network communication time, giving full play to the respective advantages of heterogeneous platform performance, and maximizing efficiency are issues worthy of attention.

Contents of the invention

The present invention aims to solve the above problems of the prior art. A time estimation co-processing method based on ARM-FPGA co-processor heterogeneous platform is proposed. Technical scheme of the present invention is as follows:

A time-predictable collaborative processing method based on an ARM-FPGA coprocessor heterogeneous platform, the method comprising:

In the application scenario where the big data storage unit and the computing unit are separated, the AXI4.0 interface will deploy the coprocessor FPGA in the data storage unit, and the information including the redundancy in the source data will be estimated and the communication time during the entire implementation process will be estimated. The sum of the delay and the comprehensive selection of the processor, the specific steps are as follows:

S1. Through the AXI4.0 interface, realize the high-speed data interaction between the ARM processor and the FPGA interconnection;

S2. The source data of the storage unit node is stored in the form of an index table, and the data representation is divided into two categories, the data set with strong regularity and the data set with complex regularity;

S3. According to different representation forms of source data, establish a class index table probability storage structure to represent the probability problems of different data distribution forms, so as to judge whether the source data needs to be preprocessed;

S4. There is time delay in each process of source data processing. Therefore, it is necessary to clarify the communication process of each data transmission stage, calculate the sum of the entire time delay, and provide a reliable basis for the final decision of the source data processor. Therefore, it is necessary to Estimate the overall time delay of ARM processor data processing and FPGA data processing respectively;

S5. After the overall delay estimation is completed, according to the estimated delay, make a decision on the choice of processor for source data processing; if you want to accurately determine which processor is more suitable, only use the overall communication estimated delay to make a decision Not very appropriate, also consider the current state of ARM processors and FPGA processors.

Further, in the step S1, when a data request is generated, the ARM processor extracts the data by accessing the memory. When the source data cannot all be stored in the processor memory, the source data stored in the storage medium (hard disk) can be accessed, and all the source data can be sent to the computing unit processor; however, if the FPGA is used for data preprocessing, The AXI interface will enable high-speed communication and data interaction between the ARM processor and the FPGA.

Further, in the step S2, different data characteristics are used to describe in different ways, the gender column distribution satisfies the binomial distribution, the node records the probability value of its occurrence, the age column is described by a uniform distribution, and the node records it The maximum and minimum values of the score column are relatively complex, and the key value of the data is obtained by hashing for processing; among them, different key value columns are marked with different numbers, the gender column is marked with 1, and the age column is marked with 2 is marked, and the grade column is marked with 3.

Further, in the step S3, for the source data with strong regularity, the probability distribution is relatively single, and the probability value is estimated by using fixed value calculation. In the source data with complex rules, the key of each data is described by the structure of the class, and the class index table is established to estimate the data size; the index node table is established based on the size of the key value of the source data, and the node index table is established in the process of , its nodes are established with frequently indexed data key values to ensure the accuracy of estimation; the underlying leaf nodes store the probability value of data A, and P _{i, j} represents the node data between A _i < A < the probability value of A _j ; taking the first leaf node in the index structure as an example, P _0,4 indicates the probability value of the node data less than A ₄ ; if the symmetric probability distribution is satisfied in the interval A<A ₄ , it can be based on P A probability value of _0,4 estimates a certain probability value.

Further, in the step S4, the ARM processor system is used to process the source data. The time delay of the whole process mainly includes the source data extraction and transmission time, the network transmission time delay and the source data calculation time, which are respectively represented by T _Ao-t and T _{Af -n} and T _Ao-c represent; the processing process first takes out the source data from the storage node unit, and then forwards it to the computing node unit, and its overall time cost is represented by the T _Arm symbol; the formula is: T _Arm = T _Ao-t + T _Ao-c ; the internal storage unit of the source data communicates with the high-speed PCIe interface, and its communication delay is the product of the stable transmission rate (V ₁ ) and the amount of source data (A _o ), expressed as T _Ao-t = V ₁ * A _o ;

Further, in the step S4, the FPGA is used as a coprocessor to perform source data preprocessing, and the entire process delay includes extracting source data communication delay, data preprocessing delay in FPGA, post-processing data network transmission delay and calculation The unit processing delay is represented by T _Fo-t , T _Fo-c , T _Ff-n and T _Ff-c respectively; the source data FPGA communicates with ARM processing through the AXI interface, and the communication delay is a stable transmission rate The product of (V) and the amount of source data (A _o ), expressed as T _Fo-t = (V+V ₁ )*A _o ; the delay of data transmission in the network is determined by the current network speed (N _v ) and transmission It is determined by the amount of data (A _o+f ), which is expressed as T _Af-n , T _Ff-n =N _v *A _o+f ; when there is a source data processing request, the ARM processor parses the task message, so that the FPGA The processor interacts with the source data from ARM processing through the AXI protocol interface, and then performs data preprocessing. After the source data preprocessing is completed, the processed data is directly sent to the computing node unit through the network through the integrated network card on the FPGA; the overall The time overhead is represented by T _Fpga . The formula is: T _Fpga =T _Fo-t +T _Fo-c +T _Ff-n +T _Ff-c .

Further, in the step S5, when we consider that both processors currently have a task being processed, the required processing time is respectively T _A-now and T _F-now , if another task arrives at this time, the task The time of using ARM processor and FPGA processor is T _Arm and T _Fpga respectively, then it can be judged that the total time required for ARM processor and FPGA processor to process tasks is T _A-all and T _F-all , where T _{A- all} ＝T _A-now +T _Arm , TF _-all ＝T _F-now +T _Fpga , we can make a reasonable decision according to the total time required to complete the task, when TA _-all < _TF-all , Choose the ARM processor for task data processing, and vice versa, choose the FPGA processor for task data processing.

Advantage of the present invention and beneficial effect are as follows:

1. Deploy the FPGA coprocessor in the data storage unit based on the AXI4.0 protocol interface. Here we focus on how to preprocess the source data and reduce invalid data in the process of data transmission, so as to slow down network congestion and reduce the amount of data transmission. Mainly taking advantage of the characteristics of FPGA programmable flexibility, short development cycle and powerful parallel computing efficiency, hardware FPGA is deployed in a distributed manner on the edge side, and software and hardware are co-processed to accelerate the preprocessing of source data. Rather than focus on how to add hardware processing in the source data transmission path to achieve the final effect.

2. Estimate the amount of invalid data in the source data in a probabilistic way to decide whether data preprocessing is required. During data preprocessing, there may be little redundancy in preprocessing data information, but data preprocessing will process the entire data, which cannot effectively reduce data internal communication traffic, network transmission delay, and calculation processing time, and the gain outweighs the gain. Therefore, whether to perform source data preprocessing is particularly important. Here, the probability method is used to estimate the data, and the source data is stored in the form of an index table. There are two situations. One is that the source data has obvious rules, which can be analyzed through the fixed value probability to solve the estimation of the source data preprocessing The second problem is that the source data is relatively complex, but the data is stored in the form of an index table, and the data size is estimated by the probability of the index table structure. Although the final estimation result is greatly affected by the established class index structure, this method can greatly reduce the processing time during estimation, and we do not need to adopt a fine-grained scheme to fine-tune the source data redundancy, which brings Too much computational pressure. The accuracy of the estimator has little effect on the result, and overall it seems that the loss of accuracy has greatly improved the processing time.

3. Estimate the time overhead of different processors in the whole process through the time estimation method. Here we can measure the time of the entire communication process, provide a basis for the reasonable sharing of workload among different processors, select different processors for different tasks, give full play to the advantages of each processor, and improve the overall system efficiency.

4. Decision-making for processor selection. According to the comprehensive decision-making of each processor's processing time overhead and the current processor's real-time state estimation factors, FPGA coprocessor or ARM processor is selected for data processing.

Description of drawings

Fig. 1 is an application scenario based on the separation of a large data storage unit and a computing unit in a preferred embodiment provided by the present invention;

Fig. 2 is a schematic diagram of deploying an FPGA device in a storage data unit according to a preferred embodiment of the present invention;

Figure 3 is an index structure diagram;

FIG. 4 is a probability storage structure diagram for establishing a class index table according to the index table example above;

Fig. 5 is the data preprocessing process figure that is finished by ARM processor system;

Fig. 6 is by FPGA as the source data processing process of coprocessor;

Detailed ways

The technical solutions in the embodiments of the present invention will be described clearly and in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the invention.

The technical scheme that the present invention solves the problems of the technologies described above is:

The invention is based on a time-predictable collaborative processing method of an ARM-FPGA coprocessor heterogeneous platform. Based on the application scenario where the big data storage unit and computing unit are separated, the scenario structure is shown in Figure 1. The AXI4.0 interface will deploy the coprocessor FPGA in the data storage unit, the redundancy in the source data and other information will be estimated, the sum of the delay in the entire implementation process will be estimated, and a comprehensive decision will be made on the processing options. Contains the following specific steps:

1. Through the AXI4.0 interface protocol, the FPGA device will be deployed in the storage data unit. The structure diagram of the storage unit deployed is shown in Figure 2. When a data request is generated, the ARM processor extracts the data by accessing the memory. When all the source data cannot be stored in the processor memory, the source data stored in the storage medium (hard disk) can be accessed, and all the source data can be sent to the computing unit processor. However, if the FPGA is used for data preprocessing, the AXI interface will enable high-speed communication and data interaction between the ARM processor and the FPGA.

2. The source data in the storage unit is stored in the form of an index table. The structure of the index table is shown in Figure 3. Data forms are roughly divided into two categories, data sets with strong regularity and data sets with complex regularity. Here, a specific example is used to explain the data classification problem. The gender column distribution satisfies the binomial distribution, and the nodes record the probability value of its occurrence. The age column is described by a uniform distribution, and the nodes record its maximum and minimum values. The distribution of the score column is relatively complicated, and the key value of the data is obtained by hashing for processing. Among them, different key-value columns are marked with different numbers. The gender column is marked with 1, the age column is marked with 2, and the grade column is marked with 3.

3. According to the index table example above, the probability storage structure of the class index table is established as shown in Figure 4.

For the source data with strong regularity, the probability distribution is relatively simple, and the probability value is estimated by fixed value calculation.

In the source data with complex rules, the key of each data is described by the class structure, and the class index table is established to estimate the data size. The index node table is built with the size of the key value of the source data. In the process of building the node index table, the node is created with the key value of the frequently indexed data to ensure the accuracy of the estimation. The bottom leaf node stores the probability value of data A, and P _i,j represents the probability value of A _i <A<A _j among node data. Taking the first leaf node in the index structure as an example, P _0,4 represents the probability value that the node data is smaller than A ₄ . If the symmetric probability distribution is satisfied in the interval A<A ₄ , a certain probability value can be estimated based on the probability value of P _0,4 . Therefore, under this node index table storage structure, the number of nodes is positively correlated with the final prediction accuracy. That is, the larger the number of nodes, the more accurate the final accuracy will be. Conversely, the smaller the number of nodes, the greater the error.

4. For the entire communication delay in the source data processing process, it is necessary to clarify the communication process of each stage of data transmission, and calculate the sum of the entire delay, so as to select the final decision during the source data processing. Therefore, it is necessary to estimate the overall time delay of ARM processor preprocessing and FPGA preprocessing respectively.

The data preprocessing process completed by the ARM processor system is shown in Figure 5. The source data is processed by the ARM processor system. The delay in the whole process mainly includes the source data extraction and transmission time, network transmission delay and source data calculation time, which are represented by T _Ao-t , T _Af-n and T _Ao-c respectively. The processing process first takes out the source data from the storage node unit, and forwards it to the computing node unit. Its overall time overhead is expressed in T _Arm notation. The formula is: T _Arm =T _Ao-t +T _Ao-c +T _Af-n . The internal storage unit of the source data uses a high-speed PCIe interface for data communication, and its communication delay is the product of the stable transmission rate (V ₁ ) and the amount of source data (A _o ), expressed as T _Ao-t = V ₁ *A _o .

Figure 6 shows the source data processing process with FPGA as coprocessor. FPGA acts as a coprocessor for source data preprocessing. The whole process delay includes the communication delay of extracting source data, data preprocessing delay in FPGA, data network transmission delay after processing, and computing unit processing _delay . _t , _TFo-c , _TFf-n and _TFf-c represent. The source data FPGA uses the AXI interface to process data with ARM, and its round-trip communication delay is the product of the stable transmission rate (V) and the source data volume (A _o ), expressed as T _Fo-t = (V+V ₁ ) *A _o . The delay of data transmission in the network is determined by the current network speed (N _v ) and the amount of data transmitted (A _o+f ), which is expressed as T _Af-n , T _Ff-n = N _v *A _{o+ f} . When there is a source data processing request, the ARM processor parses the task message, so that the FPGA processor interacts with the source data from the ARM processor through the AXI protocol interface, and then performs data preprocessing. After the source data preprocessing is completed, it directly passes through the FPGA The integrated network card on the upper end sends the processed data to the computing node unit through the network. The overall time overhead is represented by T _Fpga . The formula is: T _Fpga =T _Fo-t +T _Fo-c +T _Ff-n +T _Ff-c . Among them, the data processing time of the computing unit is determined by the processing speed of the computing unit and the size of the data volume, and is positively correlated with the number of rows of data stored in the index table. The specific time delay is estimated through experiments.

5. After the overall delay estimation is completed, a decision is made on the choice of processor for source data preprocessing according to the estimated delay. If you want to accurately determine which processor is more suitable, it is not appropriate to use the estimated overall communication delay to make a decision, because we also need to consider the current state of the ARM processor and FPGA processor. At this time, when we think that two processors are currently processing a task, the required processing time is T _A-now and T _F-now respectively. If another task arrives at this time, the task uses the ARM processor and FPGA The processor times are T _Arm and T _Fpga , respectively. Then it can be judged that the total time required by the ARM processor and the FPGA processor to process tasks is T _A-all and T _F-all . Where T _A-all = T _A-now + T _Arm , T _F-all = T _F-now + T _Fpga . We can make reasonable decisions based on the total time required for the task to complete. When T _A-all < T _F-all , select the ARM processor for task data processing, otherwise, select the FPGA processor for task data processing.

The above implementation method uses an example in conjunction with the accompanying drawings to explain in detail the specific process of the time-predictable collaborative processing method based on the ARM-FPGA coprocessor heterogeneous platform, and completes the data processing of the separation of the storage unit and the calculation unit in the big data system. accelerate.

It should also be noted that the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes Other elements not expressly listed, or elements inherent in the process, method, commodity, or apparatus are also included. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above embodiments should be understood as only for illustrating the present invention but not for limiting the protection scope of the present invention. After reading the contents of the present invention, skilled persons can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims (3)

1. The time estimation collaborative processing method based on the ARM-FPGA coprocessor heterogeneous platform is characterized in that, in the application scenario where the big data storage unit and the computing unit are separated, the coprocessor FPGA is deployed in the data storage through the AXI4.0 interface unit, estimate the information including the redundancy in the source data, estimate the sum of the communication delay in the entire implementation process, and make a comprehensive decision on the processor. The specific steps are as follows: S1. Realize high-speed data interaction between ARM processor and FPGA through AXI4.0 interface; S2. The source data of the storage unit node is stored in the form of an index table, and the data representation is divided into two categories, the data set with strong regularity and the data set with complex regularity; S3. According to the different forms of source data, establish a class index table probability storage structure to represent the probability of different data distribution forms, so as to judge whether the source data needs to be preprocessed; in the step S3, for the source with strong regularity For the data, use fixed value calculation to estimate the probability value; for the source data with complex laws, the key name of each data is described by the structure of the class, and the class index table is established to estimate the data size; S4. There is time delay in each process of source data processing. It is necessary to clarify the communication process of each data transmission stage and calculate the sum of the entire time delay. It is necessary to estimate the overall time delay of ARM processor data processing and FPGA data processing respectively. ; S5. After the overall time delay estimation is completed, according to the estimated time delay, a decision is made on the choice of the processor when processing the source data; when making the decision, the state of the current ARM processor and the FPGA processor should also be considered; In the step S1, when the data request is generated, the ARM processor extracts the data by accessing the memory; when the source data cannot be completely stored in the processor memory, the source data stored in the storage medium can be accessed, and the All source data is sent to the processor of the computing unit; if FPGA is used for data preprocessing, it will use the AXI4.0 interface to enable high-speed communication and data interaction between the ARM processor and FPGA; In the step S2, the gender column distribution satisfies the binomial distribution, the node records the probability value of its occurrence, the age column is described by a uniform distribution, the node records its maximum and minimum values, and the achievement column obtains data in a hash manner Key value, so as to process; Among them, different key value columns are marked with different numbers, the gender column is marked with 1, the age column is marked with 2, and the grade column is marked with 3; In the step S4, the ARM processor system is used to process the source data. The time delay of the whole process mainly includes the source data extraction and transmission time, the network transmission time delay and the source data calculation time. T _Ao-t , T _Af-n and T _Ao-c means; the processing process first takes out the source data from the storage node unit, and then forwards it to the computing node unit, and the overall time cost is represented by the T _Arm symbol; the formula is: T _Arm = T _Ao-t + T _{Ao- c} ; the internal storage unit of the source data communicates with a high-speed PCIe interface, and its communication delay is the product of the stable transmission rate V ₁ and the source data amount A _o , expressed as T _Ao-t = V ₁ *A _o ; In the step S4, the FPGA is used as a coprocessor to perform source data preprocessing, and the entire process delay includes extracting source data communication delay, data preprocessing delay in FPGA, data network transmission delay after processing, and computing unit processing time Delay, represented by T _Fo-t , T _Fo-c , T _Ff-n and T _Ff-c respectively; source data FPGA communicates with ARM through AXI interface, and its communication delay is the stable transmission rate V and source The product of the amount of data A _o is expressed as T _Fo-t = (V+V ₁ )*A _o ; the time delay of data transmission in the network is determined by the current network speed N _v and the amount of transmitted data A _o+f , which is expressed as T _Ff-n , T _Ff-n =N _v *A _o+f ; when there is a source data processing request, the ARM processor parses the task message, so that the FPGA processor can perform the processing from the ARM through the AXI protocol interface Source data interaction, and then data preprocessing. After the source data preprocessing is completed, the processed data is directly sent to the computing node unit through the network through the integrated network card on the FPGA; the overall time overhead is represented by T _Fpga ; the formula is: T _Fpga = T _Fo-t + T _Fo-c + T _Af-n + T _Ff-c . 2. the time estimation collaborative processing method based on ARM-FPGA coprocessor heterogeneous platform according to claim 1, it is characterized in that, in described step S3, set up index node table with source data key value size, in knot In the process of establishing the point index table, the nodes are established based on frequently indexed data key values to ensure the accuracy of estimation; the underlying leaf nodes store the probability value of data A, which is represented by P _{i, j} at the node The probability value of A _i <A<A _j between the data; for the first leaf node P _0,4 in the index structure, it means the probability value of the node data less than A ₄ ; if the symmetric probability distribution is satisfied in the A<A ₄ interval, A certain probability value can be estimated based on the P _0,4 probability value. 3. the time estimation collaborative processing method based on ARM-FPGA coprocessor heterogeneous platform according to claim 1, is characterized in that, in described step S5, when two processors all have a task to be processing at present, so The required processing time is T _A-now and T _F-now respectively. If another task comes at this time, and the time for this task to use the ARM processor and the FPGA processor is T _Arm and T _Fpga respectively, then it can be judged that the ARM processor and the total time required by the FPGA processor to process tasks are T _A-all and T _F-all , where T _A-all = T _A-now + T _Arm , T _F-all = T _F-now + T _Fpga , according to the total time required for task completion, when T _A-all < T _F-all , select the ARM processor Perform task data processing, on the contrary, choose FPGA processor for task data processing.

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