CN111931442A

CN111931442A - FPGA embedded FLASH controller and electronic device

Info

Publication number: CN111931442A
Application number: CN202011012135.1A
Authority: CN
Inventors: 刘锴; 宋宁; 李秦飞; 马得尧; 杜金凤
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2020-11-13
Anticipated expiration: 2040-09-24
Also published as: CN111931442B

Abstract

The invention provides an FPGA embedded FLASH controller and an electronic device, wherein the FPGA embedded FLASH controller is realized based on logic resources of the FPGA and is provided with an interface module, a FLASH logic control module and a plurality of FLASH function modules, the interface module is connected with a main device, and the plurality of FLASH function modules are arranged in one-to-one correspondence with different types of FLASH memories and are connected with the corresponding types of FLASH memories. The technical scheme of the invention can utilize the characteristic that the FPGA can be repeatedly programmed to dynamically configure according to different application scenes so as to be compatible with different types of FLASH memories. The design improves the expansibility and the usability of the FPGA embedded or externally connected FLASH memory, reduces the complexity of the design and the application of the FPGA embedded or externally connected FLASH memory, improves the application flexibility of FPGA logic resources and FLASH storage resources, and improves the development efficiency and the development speed of products.

Description

FPGA embedded FLASH controller and electronic device

Technical Field

The invention relates to the technical field of design of an FPGA (field programmable gate array) embedded FLASH controller, in particular to an FPGA embedded FLASH controller and an electronic device.

Background

The random reading refers to that when the memory performs read-write operation, the required read operation time is irrelevant to the accessed address, the FLASH memory is a memory which can be randomly accessed to each storage unit through an address instruction, has the random reading characteristic, is not easy to lose when the data is powered off, supports the high-speed reading of the data of the storage unit, and can be generally used as a storage medium for permanently storing the data.

An FPGA (Field-Programmable Gate Array) is a circuit that can be programmed and modified by a user after being manufactured, and can be programmed by a hardware description language to accomplish a specific task. Meanwhile, the FPGA is widely applied due to high hardware parallelism degree and high verification efficiency. In practical application, different models of FPGAs produced by different manufacturers are different, and the models of the embedded or externally connected FLASH memories are also different, so that a lot of time is needed to be spent on knowing the models and the interface time sequence when the embedded or externally connected FLASH memories of the FPGAs are applied, thereby increasing the application complexity and greatly reducing the development efficiency and speed of products.

Disclosure of Invention

The invention aims to provide an FPGA embedded FLASH controller and an electronic device, which can improve the expansibility and the usability of an FPGA embedded or externally connected FLASH memory, reduce the complexity of the design and the application of the FPGA embedded or externally connected FLASH memory and improve the efficiency and the speed of the development of products.

In order to solve the above technical problem, the present invention provides an FPGA embedded FLASH controller, which includes:

the interface module is used for establishing communication connection with the main equipment, so that the main equipment can access and control the FLASH logic control module;

the FLASH memory management system comprises a plurality of FLASH functional modules, a plurality of FLASH storage units and a plurality of FLASH storage units, wherein the FLASH functional modules are arranged in a one-to-one correspondence with different types of FLASH memories and connected with the FLASH memories of corresponding types for realizing corresponding functional operation on the connected FLASH;

and the FLASH logic control module is connected with the interface module and the plurality of FLASH functional modules.

Optionally, the FLASH logic control module is configured to map the operation instruction sent by the host device to a relevant operation of a corresponding register, select and match the corresponding FLASH function module, and control the selected FLASH function module to perform a corresponding function operation on the connected FLASH memory according to the relevant operation of the register, so as to implement compatibility between different types of FLASH memories.

Optionally, the interface module is communicatively connected to the master device through a corresponding communication protocol bus, where the communication protocol bus is an AHB bus, an APB bus, an AXI bus, a WISHBONE bus, or an Avalon bus; or the interface module is connected with the register interface of the master device.

Optionally, the interface module is further configured to decode a storage address space of the host device, parse each register in the FLASH logic control module, and map each register into a different address region of the storage address space of the host device.

Optionally, the interface module comprises:

the address judging module is connected with the main equipment and used for judging whether an address signal sent by the main equipment is effective or not, if not, the interface module is not enabled, a FLASH memory connected with the FPGA embedded FLASH controller is maintained in an original state, and if so, the interface module is enabled to continue subsequent operation;

the operation judgment module is connected with the address judgment module and used for judging the operation instruction sent by the main equipment and outputting a corresponding judgment result;

the information transmission module is connected with the operation judgment module and used for transmitting the data signal and the operation signal sent by the main equipment to the FLASH signal generation module according to the judgment result of the operation judgment module;

and the FLASH signal generating module is connected with the information transmission module and the FLASH logic control module and is used for enabling under the control of the information transmission module, converting the operation signal transmitted by the information transmission module into a standard operation signal required for operating the FLASH logic control module and converting the data signal transmitted by the information transmission module into a standard data signal required by the FLASH logic control module.

Optionally, when the main device is connected to the interface module through an AHB bus, the operation determination module is further configured to perform operation mode determination on an operation instruction sent by the main device, where the information transmission module includes a basic mode transmission module, a Burst mode transmission module, and a first-in-first-out queue buffer; when the operation judging module judges that the operation mode is a basic transmission mode, enabling the basic mode transmission module, wherein the basic mode transmission module is used for analyzing the data signal and the operation signal sent by the main equipment according to the basic transmission mode specified by an AHB communication protocol and generating the operation signal and the data signal required by the FLASH logic control module; and when the operation judging module judges that the operation mode is the Burst transmission mode, enabling the Burst mode transmission module, wherein the Burst mode transmission module is used for analyzing the data signal and the operation signal sent by the main equipment according to the Burst transmission mode specified by an AHB communication protocol to generate the operation signal and the data signal required by the FLASH logic control module.

Optionally, when the main device is connected to the interface module through a WISHBONE bus, the operation determining module is further configured to determine an operation instruction sent by the main device, and transmit a result of the determination to the FLASH signal generating module to generate a corresponding operation signal; the information transmission module comprises a data transmission module which is enabled under the control of the operation judgment module and is used for analyzing the data signal sent by the main equipment according to the WISHBONE communication protocol and generating the data signal required by the FLASH logic control module.

Optionally, the interface module is a universal bus interface module, which contains at least two communication protocols therein, so as to establish a corresponding communication protocol link with different types of master devices or different types of communication protocol buses of the same master device; the embedded FLASH controller of the FPGA also comprises a bus interface arbitration enabling module and a bus type module which are connected with the main equipment, wherein,

the bus interface arbitration enabling module is connected with the main equipment and the interface module, is driven and enabled by the bus type module, and is used for selecting a corresponding communication protocol link from the interface module by analyzing the type of a communication protocol bus of the main equipment so as to establish communication connection between the interface module and the main equipment;

the bus type module is connected with the main equipment and the bus interface arbitration enabling module, correspondingly marks different types of communication protocol buses, and is used for obtaining type information of the communication protocol buses of the main equipment and enabling the interface module according to the type information so as to establish a corresponding communication protocol link between the interface module and the main equipment.

Optionally, the bus interface arbitration enabling module comprises a multiplexer.

Optionally, the FLASH logic control module includes at least one general register set, and each general register set includes a control register, a status register, a read-write data register, an erase data register, and a FLASH type selection register; and each register in the general register group is connected with a corresponding pin of each FLASH functional module.

Optionally, the FLASH function module includes a FLASH internal interface and a FLASH operation module, the FLASH internal interface is used for implementing interaction between the FLASH function module and the FLASH logic control module, and the FLASH operation module is connected to the corresponding FLASH memory and is used for implementing random reading, writing, erasing or controlling of the connected FLASH memory.

Optionally, the pin of the internal interface of the FLASH includes: the device comprises a clock pin, a reset pin, a control pin, a state pin, a read-write data pin, an erasing data pin and a FLASH type selection pin; the clock pin is connected with a clock signal on a communication protocol bus in an external mode, the reset pin is connected with a reset signal on the communication protocol bus in an external mode, the control pin is connected with the control register, the state pin is connected with the state register, the read-write data pin is connected with the read-write data register, the erasing data pin is connected with the erasing data register, and the FLASH type selection pin is connected with the FLASH type selection register.

Optionally, when the master device is simultaneously connected to a plurality of FLASH memories through the FLASH controller embedded in the FPGA, the FLASH logic control module further includes a combinational logic circuit, and the combinational logic circuit is connected to the control register and the status register, and is configured to map the interrupt signal of each FLASH function module into an interrupt vector table of the master device according to a specified priority, so as to implement priority control of the master device on each FLASH memory.

Optionally, the master device is connected to one FLASH memory through the FPGA embedded FLASH controller, or the master device is simultaneously connected to a plurality of FLASH memories through the FPGA embedded FLASH controller, and at least two of the plurality of FLASH memories are different in type.

Optionally, the FLASH memory and the FPGA embedded FLASH controller are embedded in the same FPGA, or the FLASH memory is arranged outside the FPGA where the FPGA embedded FLASH controller is located; the main equipment is embedded in the FPGA where the FPGA embedded FLASH controller is located, or the main equipment is arranged outside the FPGA where the FPGA embedded FLASH controller is located.

Based on the same inventive concept, the invention also provides an electronic device, which comprises the FPGA embedded FLASH controller, and main equipment and at least one FLASH memory which are in communication connection with the FPGA embedded FLASH controller.

Compared with the prior art, the technical scheme of the invention has one of the following technical effects:

the embedded FLASH controller of the FPGA is realized based on the logic resources of the FPGA, and can be dynamically configured according to different application scenes by utilizing the characteristic of repeatable programming of the FPGA so as to be compatible with different types of FLASH memories. The design improves the expansibility and the usability of the FPGA embedded or externally connected FLASH memory, reduces the complexity of the design and the application of the FPGA embedded or externally connected FLASH memory, improves the application flexibility of FPGA logic resources and FLASH storage resources, and improves the development efficiency and the development speed of products.

Furthermore, the bus type of the master device can be identified to support multiple communication protocols, so that the master device is compatible with different types of master devices, and the master device with multiple different types of communication protocol buses is compatible, and the application flexibility of master device resources is improved.

Drawings

Fig. 1 is a schematic diagram of a system architecture of a FLASH controller embedded in an FPGA according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a system architecture of an interface module of the FPGA embedded FLASH controller shown in fig. 1.

Fig. 3 is a schematic diagram of a system architecture of a FLASH logic control module and a FLASH function module in the FPGA embedded FLASH controller shown in fig. 1.

Fig. 4 is a system architecture diagram of an application example one of the FPGA embedded FLASH controller shown in fig. 1 (applied to the case where the master device and the FLASH transmit data through an AHB bus).

Fig. 5 is a system architecture diagram of the AHB interface module in fig. 4.

Fig. 6 is a schematic diagram of the working flow of the FPGA embedded FLASH controller shown in fig. 4.

Fig. 7 is a system architecture diagram of a second application example of the FPGA embedded FLASH controller shown in fig. 1 (applied to the case where the host device and the FLASH transmit data through the WISHBONE bus).

Fig. 8 is a schematic diagram of the system architecture of the WISHBONE interface module in fig. 7.

Fig. 9 is a schematic diagram of the working flow of the FPGA embedded FLASH controller shown in fig. 7.

Fig. 10 is a system architecture diagram of an application example three of the FPGA embedded FLASH controller shown in fig. 1 (applied to the case where the host device and the FLASH transmit data through a register interface).

Fig. 11 is a schematic diagram of an architecture of an FPGA embedded FLASH controller according to another embodiment of the present invention.

Fig. 12 is a schematic flow chart of the operation of the FPGA embedded FLASH controller shown in fig. 11.

Fig. 13 is a schematic diagram of an architecture of a system on chip having an FPGA embedded FLASH controller according to an embodiment of the present invention.

Fig. 14 is a schematic diagram of an architecture of a system on chip having an FPGA embedded FLASH controller according to another embodiment of the present invention.

Fig. 15 is a schematic diagram of an architecture of a system on chip having an FPGA embedded FLASH controller according to another embodiment of the present invention.

Detailed Description

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 1, an embodiment of the present invention provides an FPGA embedded FLASH controller 10, where the FPGA embedded FLASH controller 10 is implemented based on a logic resource inside an FPGA (not shown), that is, the FPGA embedded FLASH controller 10 is embedded in the FPGA. Logic resources inside the FPGA mainly include Logic Control Block (LCB) resources, clock network resources, clock processing resources, Block random access memory (Block RAM), digital signal processing resources (DSP core), and interface resources. The logic control block resources include display look-up tables, adders, multipliers, dividers, registers, multiplexers, and the like.

In this embodiment, the FPGA embedded FLASH controller 10 includes an interface module 11, a FLASH logic control module 12, and n FLASH function modules 101 to 10n, where n is not less than 2.

The interface module 11 is connected and matched with the main device 20 through a logic connection line of the FPGA, and is configured to establish a communication connection with the main device 20, so that the main device 20 can access and control the FLASH logic control module 12. Specifically, the interface module 11 and the master device 20 may be communicatively connected through a corresponding main flow communication protocol bus, where the main flow communication protocol bus is an AHB bus, an APB bus, an AXI bus, a WISHBONE bus, or an Avalon bus, and the like, or the interface module 11 and the register of the master device 20 are interfaced. The interface module 11 performs address segmentation on the storage address space of the main device 20 according to the address depth of the register in the FLASH logic control module 12 and the storage capacity allocation condition of the FLASH memory connected to each FLASH function module 101-10 n, forms a mapping relationship between the address segmentation and the register address of the register, and further sends the mapping relationship to the main device 20, so that the main device 20 can generate a corresponding storage address signal according to the mapping relationship, and further analyzes information in a FLASH type selection register in the FLASH logic control module 12 by decoding the storage address space of the main device 20, thereby realizing support for different types of FLASH. In short, the interface module 11 can decode the storage address space of the host device 20, analyze each register in the FLASH logic control module 12, and map each register to a different address area of the storage address space of the host device 20; further analyzing the FLASH type selection register in the FLASH logic control module 12, and further controlling the FLASH logic control module 12 to select the corresponding FLASH function module, so as to realize the support for different types of FLASH memories.

The master device 20 may be any device capable of generating operation timing, operation instructions, and the like, such as a part of logic resources (e.g., DSP cores, logic control blocks) in an MCU or an FPGA. As an example, referring to fig. 13, the master device 20 may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10 is located, that is, the master device 20 and the FPGA embedded FLASH controller 10 are located on the same FPGA. As another example, referring to fig. 14, the master device 20 may be disposed outside an FPGA where the FLASH controller 10 is embedded in the FPGA, and implemented based on an MCU, and optionally, the MCU and the FPGA are integrated in the same system on chip. As yet another example, referring to fig. 15, the host device 20 may be provided outside of the system on chip in which the FPGA embedded FLASH controller 10 is located.

The n FLASH function modules 101-10 n are correspondingly arranged and connected with the n FLASH memories 31-3 n one by one, the types of the n FLASH memories 31-3 n are different, the n FLASH memories 31-3 n can not be simultaneously connected to the embedded FLASH controller 10 of the FPGA, and at the moment, the FLASH function modules which are not connected with the FLASH memories are idle. Each FLASH functional module is used for implementing corresponding functional operations, such as reading data, writing data, erasing data or other control operations, on the FLASH memory connected with the FLASH functional module. The FLASH logic control module 12 is connected to the interface module 11 and each of the FLASH function modules 101 to 10n, and is configured to map an operation instruction sent by the main device 20 to a relevant operation of a corresponding register therein, select and match a corresponding FLASH function module from the FLASH function modules 101 to 10n, and control the selected FLASH function module to perform a corresponding function operation on the connected FLASH memory according to the relevant operation of the register, so as to implement compatibility of different types of FLASH memories.

It should be noted that each FLASH memory may be a storage resource inside the FPGA or may be a storage resource outside the FPGA. As an example, referring to fig. 13, the main device 20 and each of the FLASH memories 31 to 3n may be implemented based on a logic resource of an FPGA where the FPGA embedded FLASH controller 10 is located, that is, at this time, the main device 20, each of the FLASH memories 31 to 3n and the FPGA embedded FLASH controller 10 are located on the same FPGA. As another example, referring to fig. 14, the main device 20 may be disposed outside an FPGA where the FPGA embedded FLASH controller 10 is located, and implemented based on an MCU, where each of the FLASH memories 31 to 3n is implemented based on a logic resource of the FPGA where the FPGA embedded FLASH controller 10 is located, that is, at this time, each of the FLASH memories 31 to 3n and the FPGA embedded FLASH controller 10 are located on the same FPGA, and the MCU and the FPGA are integrated in the same system on a chip. As yet another example, referring to FIG. 15, the host device 20 and each of the FLASH memories 31-3 n are disposed outside of the system on chip in which the FPGA embedded FLASH controller 10 is located.

In addition, after the main device 20 is connected to the interface module 11, the interface module 11 can analyze whether the operation instruction of the main device 20 is to read data, write data, or perform an erasing operation or other operations on the data, if the operation instruction of the data is sent by the main device 20, the interface module 11 selects a corresponding register in the FLASH logic control module 12 according to an address signal sent by the main device 20, and the FLASH logic control module 12 selects a corresponding FLASH function module from the FLASH function modules 101 to 10n to execute the instruction, and reads out the data from a FLASH memory connected to the FLASH logic control module; if the main device 20 sends a write data operation instruction, the interface module 11 selects a corresponding register in the FLASH logic control module 12 according to an address signal sent by the main device 20, and the FLASH logic control module 12 selects a corresponding FLASH function module from the FLASH function modules 101 to 10n to execute the instruction, and writes corresponding data into a FLASH memory connected to the FLASH logic control module. For the erasing operation, the interface module 11 selects the corresponding register in the FLASH logic control module 12 according to the address signal sent by the host device 20, and further performs the data erasing operation on the corresponding FLASH memory.

As an example, referring to fig. 2, the interface module 11 includes: an address judging module 110, an operation judging module 111, an information transmitting module 112 and a FLASH signal generating module 113.

The address determining module 110 is connected to the main device 20 and the operation determining module 111, and is configured to determine whether an address signal sent by the main device 20 is valid, if not, the interface module 11 is disabled, each FLASH memory connected to the FPGA embedded FLASH controller 10 is maintained as it is, and if so, the interface module 11 is enabled, and continues subsequent operations.

The operation determining module 111 is connected to the address determining module 110 and the information transmitting module 112, and the operation determining module 111 is configured to determine an operation instruction sent by the host device 20 and output a corresponding determination result.

The information transmission module 112 is connected to the operation judgment module 111 and the FLASH signal generation module 113, and the information transmission module 112 is configured to transmit the data signal and the operation signal sent by the main device 20 to the FLASH signal generation module 113 according to the judgment result of the operation judgment module 111.

The FLASH signal generating module 113 is connected to the information transmitting module 112 and the FLASH logic control module 12, and the FLASH signal generating module 113 is configured to enable under the control of the information transmitting module 112, convert the operation signal transmitted by the information transmitting module 112 into a standard operation signal required for operating the FLASH logic control module 12, and convert the data signal transmitted by the information transmitting module 112 into a standard data signal required by the FLASH logic control module 12.

As an example, referring to fig. 3, the FLASH logic control module 12 includes at least one general register set, each of which includes a control register 121, a status register 122, a read-write data register 123, an erasure data register 124, and a FLASH type selection register 125; and each register in the general register set is connected with a corresponding pin of each FLASH functional module 101-10 n. Each of the FLASH function modules 101 to 10n includes a FLASH internal interface (not shown) for implementing interaction between the FLASH function module and the FLASH logic control module 12, and a FLASH operation module (not shown) connected to the corresponding FLASH memory for implementing random reading, writing, erasing, or controlling of the connected FLASH memory. Optionally, the pin of the internal interface of the FLASH includes: the device comprises a clock pin, a reset pin, a control pin, a state pin, a read-write data pin, an erasing data pin and a FLASH type selection pin; the clock pin is connected with a clock signal on a communication protocol bus, the reset pin is connected with a reset signal on the communication protocol bus, the control pin is connected with the control register 121, the state pin is connected with the state register 122, the read-write data pin is connected with the read-write data register 123, the erasing data pin is connected with the erasing data register 124, and the FLASH type selection pin is connected with the FLASH type selection register 125.

Optionally, please refer to fig. 3, when the main device 20 is simultaneously connected to not less than 2 FLASH memories through the FPGA embedded FLASH controller 10, the FLASH logic control module 12 further includes a combinational logic circuit 126, and the combinational logic circuit 126 is connected to the control register 121 and the state register 122, and is configured to map the interrupt signals of the FLASH function modules 101 to 10n into an interrupt vector table of the main device 20 according to a specified priority, so as to implement priority control of the main device 20 on the FLASH memories.

It should be noted that only one general register set is shown in fig. 3, and each of the FLASH function modules 101 to 10n shares the same general register set, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the FLASH logic control module 12 may include n general register sets, and the n general register sets and the FLASH function modules 101 to 10n are disposed and connected in a one-to-one correspondence.

The embedded FLASH controller of the FPGA of the embodiment is realized based on the logic resources of the FPGA, and can be dynamically configured according to different application scenes by utilizing the characteristic that the FPGA can be repeatedly programmed so as to be compatible with different types of FLASH memories. The design improves the expansibility and the usability of the FPGA embedded or externally connected FLASH memory, reduces the complexity of the design and the application of the FPGA embedded or externally connected FLASH memory, improves the application flexibility of FPGA logic resources and FLASH storage resources, and finally improves the development efficiency and the development speed of products. The FLASH controller embedded in the FPGA of this embodiment can be applied to a case where the host device communicates with the FLASH memory through a fixed communication protocol, and a case where the host device communicates with the FLASH memory through the register interface. In order to better understand the design scheme of the FPGA embedded FLASH controller 10 of the present embodiment, the following description is made in detail with reference to three application examples and fig. 3 to 10.

Application example-FPGA embedded FLASH controller applied to AHB communication protocol

Referring to fig. 4, the FPGA embedded FLASH controller 10 of the first application example is applied to an AHB communication protocol, which is denoted as an FPGA embedded FLASH controller 10A, the master device 20 is an AHB master device, which is denoted as an AHB master device 20A, and a system bus thereof is an AHB bus under the AHB communication protocol, and when the AHB bus is also implemented based on a logic connection inside the FPGA. The embedded FLASH controller 10A of the FPGA can be simultaneously connected with n FLASH memories 31-3 n. With reference to fig. 13 to 15, the AHB master 20A and each FLASH memory 31 to 3n may be implemented based on a logic resource of an FPGA where the FPGA embedded FLASH controller 10A is located, respectively, that is, at this time, the AHB master 20A, each FLASH memory 31 to 3n, and the FPGA embedded FLASH controller 10A are located on the same FPGA; or, the AHB master device 20A may be disposed outside the FPGA where the FPGA embedded FLASH controller 10A is located, and implemented based on the MCU, and optionally, the MCU and the FPGA are integrated in the same system on a chip, at this time, each FLASH memory 31 to 3n may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10A is located, that is, located on the same FPGA as the FPGA embedded FLASH controller 10A; or the AHB main equipment 20A and each FLASH memory 31-3 n are arranged outside the system on chip where the FPGA embedded FLASH controller 10A is arranged.

The FPGA embedded FLASH controller 10A comprises an AHB interface module 11A, FLASH logic control module 12 and n FLASH function modules 101-10 n.

The AHB interface module 11A is connected to the AHB interface of the AHB master 20A through the AHB bus, establishes communication connection with the AHB interface, and transmits data on the AHB bus to the FLASH logic control module 12 by analyzing the data. The specific functions include: decoding the storage address space of the AHB main equipment 20A, analyzing each register in the FLASH logic control module 12, selecting the register 125 according to the analyzed FLASH type, and mapping the corresponding FLASH functional module in different address areas of the storage address space of the AHB main equipment 20A, thereby realizing the support of different types of FLASH memories 31-3 n.

Referring to fig. 3, the FLASH logic control module 12 is connected to the AHB interface module 11A and each of the FLASH function modules 101 to 10n, and maps the FLASH function in each of the FLASH function modules 101 to 10n into the control register 121, the status register 122, the read-write data register 123, the erase data register 124, and the FLASH type selection register 125. Each register is mapped to the storage address space of the AHB master device 20 through the AHB interface module 11A, so that the AHB master device 20A can perform operations such as reading, writing, erasing, and controlling of different types of FLASH memories connected to the FLASH function modules 101 to 10 n. And by setting the FLASH type selection register 125, selecting the corresponding FLASH functional module from the FLASH functional modules 101-10 n, and completing the compatibility of different types of FLASH memories.

Each of the FLASH function modules 101 to 10n implements function control of random access, erasure, and the like of the FLASH based on FPGA logic resources, and includes a FLASH internal interface (not shown) and a FLASH operation module (not shown). The FLASH internal interface module realizes the interaction between the FLASH operation module and the FLASH logic control module 12, and is an on-chip data interaction interface between the AHB main device 20A and the FLASH function module. The FLASH operation module realizes the function operations of random reading, writing, erasing, controlling and the like of the connected FLASH memory, and is used as a data storage control module of the AHB main device 20A.

Referring to fig. 5, the AHB interface module 11A includes an address determining module 110, an operation determining module 111, an information transmitting module 112A, and a FLASH signal generating module 113. The information transmission module 112A includes a basic mode transmission module 1121, a Burst mode transmission module 1122, and a FIFO (first in first out queue) buffer 1123. The FLASH signal generating module 113 includes a FLASH operation signal generating module 1131 and a FLASH exchange data generating module 1132.

The address determination module 110 performs logic determination on the address signal sent by the AHB master 20A, analyzes whether the address sent by the AHB master 20A matches the address of the corresponding register or FLASH, and if the address sent by the AHB master 20A does not match the address of FLASH, the address sent by the AHB master 20A is an invalid address, and the AHB interface module 11A is not enabled. If a match is determined, the address sent by the AHB master 20A is an effective address, and the AHB interface module 11A is enabled for the next operation.

After the AHB interface module 11A is enabled, the operation determining module 111 identifies a data transmission mode of the AHB interface module 11A, that is, determines an operation mode of an operation instruction sent by the master device. If the transmission mode is the basic transmission mode, the basic mode transmission module 1121 will be enabled, and the basic mode transmission module 1121 analyzes the data signal and the operation signal (including a read data signal, a write data signal, an erase data signal, a control signal, and the like) sent by the AHB master device 20A according to the basic transmission mode specified by the AHB communication protocol, so as to generate the operation signal and the data signal required by the FLASH logic control module 12. If the transmission mode is BURST transmission mode, the BURST mode transmission module 1122 is enabled, and the BURST mode transmission module 1122 analyzes the data signal and the operation signal sent by the AHB master device 20A according to the BURST transmission mode specified by the AHB communication protocol, so as to generate the operation signal and the data signal required by the FLASH logic control module 12. The signal generated by the Burst mode transmission module 1122 is written into the subsequent FIFO buffer 1123 for buffering. Since BURST transfer mode is faster for the AHB bus than the basic transfer mode, and each clock generates one data, the speed of the FPGA embedded FLASH controller 10A needs to match the FLASH memory to which it is connected, however, the read/write speed of the FLASH memory is slower than that of the AHB master 20A, so that the FIFO buffer 1123 is needed for buffering.

The FLASH operation signal generating module 1131 and the FLASH exchange data generating module 1132 are configured to convert the signal generated by the basic mode transmission module 1121 or the Burst mode transmission module 1122 into a standard signal for operating a register in the FLASH logic control module 12, and transmit the standard signal to the FLASH logic control module 12.

Referring to fig. 3, fig. 4 and fig. 6, the working flow of the FPGA embedded FLASH controller 10A in the first application example is as follows:

when the AHB master 20A is connected to the AHB interface module 11A, the AHB interface module 11A analyzes the commands of the AHB master 20A, such as read data, write data, and erase data. If the AHB master device 20A issues a read data instruction, the AHB interface module 11A selects a read data register in the FLASH logic control module 12 according to the corresponding address signal, and executes a read data operation. If the AHB master device 20A issues a write data instruction, the AHB interface module 11A selects a write data register in the FLASH logic control module 12 according to the corresponding address signal, and performs a write data operation. If the AHB master device 20A issues an erase data instruction, the AHB interface module 11A selects an erase data register in the FLASH logic control module 12 according to the corresponding address, and executes an erase data operation.

The FPGA embedded FLASH controller provided by the first application example can build a communication bridge between an AHB interface of the AHB main equipment and a FLASH memory, the design inherits the characteristics of FPGA programming, and has good expansibility and usability, a user can be dynamically compatible with different types of FLASH memories, the expansibility and the usability of the FPGA embedded or externally connected FLASH memory are improved, the complexity of design and application of the FPGA embedded or externally connected FLASH memory is reduced, and the application flexibility of the storage resources of an AHB interface MCU and an FPGA on-chip system is improved.

Application example two-FPGA embedded FLASH controller applied to WISHBONE communication protocol

Referring to fig. 7, the FPGA embedded FLASH controller 10 of the second application example is applied to the WISHBONE communication protocol, which is referred to as the FPGA embedded FLASH controller 10B, the master device 20 is a WISHBONE master device, which is referred to as a WISHBONE master device 20B, and the system bus is a WISHBONE bus under the WISHBONE communication protocol, and when the WISHBONE bus is also implemented based on the logic connection inside the FPGA. The FPGA embedded FLASH controller 10B can be simultaneously connected with n FLASH memories 31-3 n. In addition, referring to fig. 13 to fig. 15, the WISHBONE master device 20B and each of the FLASH memories 31 to 3n may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10B is located, that is, the WISHBONE master device 20B, each of the FLASH memories 31 to 3n, and the FPGA embedded FLASH controller 10B are located on the same FPGA; or the WISHBONE master device 20B may be disposed outside the FPGA where the FPGA embedded FLASH controller 10B is located, and implemented based on the MCU, and optionally, the MCU and the FPGA are integrated in the same system on chip, at this time, each of the FLASH memories 31 to 3n may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10B is located, that is, on the same FPGA as the FPGA embedded FLASH controller 10B; or the WISHBONE master device 20B and each FLASH memory 31-3 n are arranged outside the system on chip where the FLASH controller 10B embedded in the FPGA is located.

The FPGA embedded FLASH controller 10B comprises an AHB interface module 11B, FLASH logic control module 12 and n FLASH function modules 101-10 n.

The WISHBONE interface module 11B is connected to the WISHBONE interface of the WISHBONE master 20B via a WISHBONE bus, establishes a communication link with the WISHBONE interface, and transmits data on the WISHBONE bus to the FLASH logic control module 12 by parsing the data on the WISHBONE bus. The specific functions include: decoding the storage address space of the WISHBONE master device 20B, analyzing each register in the FLASH logic control module 12, selecting the register 125 according to the analyzed FLASH type, and mapping the corresponding FLASH function module in different address areas of the storage address space of the WISHBONE master device 20B, so as to realize the support of different types of FLASH memories 31-3 n.

Referring to fig. 3, the FLASH logic control module 12 is connected to the WISHBONE interface module 11B and each of the FLASH function modules 101 to 10n, and maps the FLASH function in each of the FLASH function modules 101 to 10n into the control register 121, the status register 122, the read-write data register 123, the erase data register 124, and the FLASH type selection register 125. Each register is mapped to the storage address space of the WISHBONE master device 20B through the WISHBONE interface module 11B, so that the WISHBONE master device 20B can read, write, erase, control and the like different types of FLASH memories connected with each FLASH function module 101-10 n. And by setting the FLASH type selection register 125, selecting the corresponding FLASH functional module from the FLASH functional modules 101-10 n, and completing the compatibility of different types of FLASH memories.

Each of the FLASH function modules 101 to 10n implements function control of random access, erasure, and the like of the corresponding FLASH memory based on FPGA logic resources, and includes a FLASH internal interface (not shown) and a FLASH operation module (not shown). The FLASH internal interface module realizes the interaction between the FLASH operation module and the FLASH logic control module 12, and is an in-chip data interaction interface between the WISHBONE main device 20B and the FLASH function module. The FLASH operation module realizes the function operations of random reading, writing, erasing, controlling and the like of the connected FLASH memory, and is used as a data storage control module of the WISHBONE master device 20B.

Referring to fig. 8, the WISHBONE interface module 11B includes an address determining module 110, an operation determining module 111, an information transmitting module 112B, and a FLASH signal generating module 113. The information transmission module 112B includes a data transmission module 1124. The FLASH signal generating module 113 includes a FLASH operation signal generating module 1131 and a FLASH exchange data generating module 1132.

The address determination module 110 performs logic determination on the address signal sent by the WISHBONE master device 20B, analyzes whether the address sent by the WISHBONE master device 20B matches the address of the corresponding register or FLASH memory, and if the determination is not matched, the address sent by the WISHBONE master device 20B is an invalid address, and the WISHBONE interface module 11B is not enabled. If the match is determined, the address sent by the WISHBONE master device 20B is a valid address, the WISHBONE interface module 11B is enabled and the next operation is performed.

After the WISHBONE interface module 11B is enabled, the operation determining module 111 determines the operation instructions such as read, write, erase, etc. sent by the WISHBONE master device 20B, and transmits the determined result to the FLASH operation signal generating module 1131 to generate the operation signal of the FLASH logic control module 12.

The data transfer module 1124 converts data on the WISHBONE bus into data information that the FLASH logic control module 12 is able to receive, while enabling the FLASH exchange data generation module 1132. To output data transmitted by the WISHBONE bus.

The FLASH operation signal generating module 1131 is configured to generate an operation signal of the FLASH logic control module 12 according to the judgment result of the operation judging module 111; the FLASH exchange data generating module 1132 is configured to analyze, according to the WISHBONE communication protocol, the signal generated by the data transmitting module 1124 (i.e., the data signal sent by the WISHBONE master device 20B), convert the signal into a standard signal for operating a register in the FLASH logic control module 12, and transmit the standard signal to the FLASH logic control module 12. That is, the FLASH signal generation module 113 can transmit the address signal on the WISHBONE bus and the data signal that needs to be read, written or erased to the FLASH logic control module 12, and complete the control and data transmission to the FLASH logic control module 12.

Referring to fig. 3, fig. 7 and fig. 9, the working flow of the FPGA embedded FLASH controller 10B of the second application example is as follows:

when the WISHBONE master device 20B is connected to the WISHBONE interface module 11B, the WISHBONE interface module 11B analyzes the operating instructions of the WISHBONE master device 20B, such as read data, write data, erase data, etc. If the WISHBONE master device 20B issues a read data instruction, the WISHBONE interface module 11B selects a read data register in the FLASH logic control module 12 according to the corresponding address signal to perform a read data operation. If the WISHBONE master device 20B issues a write data instruction, the WISHBONE interface module 11B selects a write data register in the FLASH logic control module 12 according to the corresponding address signal, and performs a write data operation. If the WISHBONE master device 20B issues an erase data instruction, the WISHBONE interface module 11B selects an erase data register in the FLASH logic control module 12 according to the corresponding address signal to perform an erase data operation.

The FPGA embedded FLASH controller provided by the second application example can build a communication link between the WISHBONE interface of the main device and the FLASH memory, the design inherits the characteristics of FPGA programmability, has good expansibility and usability, and a user can be dynamically compatible with different types of FLASH memories, so that the expansibility and usability of the FPGA embedded or externally connected FLASH memory under the WISHBONE protocol are improved, the complexity of design and application of the FPGA embedded or externally connected FLASH memory under the WISHBONE protocol is reduced, and the application flexibility of MCU and FPGA on-chip system storage resources under the WISHBONE protocol is improved.

Register interface for connecting embedded FLASH controllers of three FPGA of application example with main equipment

Referring to fig. 10, the FPGA embedded FLASH controller 10C of the third application example is connected between the Register master device 20C and the FLASH memories 31 to 3n, where n is equal to or greater than 1. With reference to fig. 13 to 15, the Register master device 20C and each FLASH memory 31 to 3n may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10C is located, that is, the Register master device 20C, each FLASH memory 31 to 3n, and the FPGA embedded FLASH controller 10C are located on the same FPGA; or, the Register master device 20C may be disposed outside the FPGA where the FPGA embedded FLASH controller 10C is located, and implemented based on the MCU, and optionally, the MCU and the FPGA are integrated in the same system on a chip, at this time, each of the FLASH memories 31 to 3n may be implemented based on the logic resource of the FPGA where the FPGA embedded FLASH controller 10C is located, that is, located on the same FPGA as the FPGA embedded FLASH controller 10C; or the Register main device 20C and each FLASH memory 31-3 n are arranged outside the system on chip where the FLASH controller 10C embedded in the FPGA is located.

The FPGA embedded FLASH controller 10B comprises a Register interface module 11C, FLASH logic control module 12 and n FLASH function modules 101-10 n.

The Register interface module 11C is connected to the Register interface of the Register master device 20C through the FPGA logical connection line, establishes communication connection with the Register interface, and transmits data on the system bus to the FLASH logical control module 12 by analyzing the data on the system bus. The specific functions include: decoding the storage address space of the Register main device 20C, analyzing each Register in the FLASH logic control module 12, selecting the Register 125 according to the analyzed FLASH type, and mapping the corresponding FLASH functional module in different address areas of the storage address space of the Register main device 20C to realize the support of different types of FLASH memories 31-3 n.

Referring to fig. 3, the FLASH logic control module 12 is connected to the Register interface module 11C and each of the FLASH function modules 101 to 10n, and maps the FLASH function in each of the FLASH function modules 101 to 10n into a control Register 121, a status Register 122, a read-write data Register 123, an erase data Register 124, and a FLASH type selection Register 125. Each Register is mapped to the storage address space of the Register master device 20C through the Register interface module 11C, and the operations of reading, writing, erasing, controlling and the like of the Register master device 20C on different types of FLASH connected to each FLASH function module 101-10 n are realized. And by setting the FLASH type selection register 125, selecting the corresponding FLASH functional module from the FLASH functional modules 101-10 n, and completing the compatibility of different types of FLASH memories.

Each of the FLASH function modules 101 to 10n implements function control of random access, erasure, and the like of the corresponding FLASH memory based on FPGA logic resources, and includes a FLASH internal interface (not shown) and a FLASH operation module (not shown). The FLASH internal interface module realizes the interaction between the FLASH operation module and the FLASH logic control module 12, and is an on-chip data interaction interface between the Register main device 20C and the FLASH function module. The FLASH operation module realizes the function operations of random reading, writing, erasing, controlling and the like of the connected FLASH memory, and is used as a data storage control module of the Register main device 20C.

Referring to fig. 3 and fig. 10, the working flow of the FPGA embedded FLASH controller 10C of the third application example is as follows:

when the Register master device 20C is connected to the Register interface module 11C, the Register interface module 11C analyzes operation instructions of the Register master device 20C such as read data, write data, erase data, and the like. If the Register master device 20C issues a read data instruction, the Register interface module 11C selects a read data Register in the FLASH logic control module 12 according to the corresponding address signal, and executes a read data operation. If the Register master device 20C issues a write data instruction, the Register interface module 11C selects a write data Register in the FLASH logic control module 12 according to the corresponding address signal, and performs a write data operation. If the Register master device 20C issues an erase data instruction, the Register interface module 11C selects an erase data Register in the FLASH logic control module 12 according to the corresponding address signal, and performs an erase data operation. After the Register master device 20C sends the corresponding operation instruction, the Register interface module 11C returns the state of successful operation through the state identification signal, and simultaneously enables the state identification signal of the Register interface module 11C, and feeds back the state information to the Register master device 20C, and the Register master device 20C performs the next operation.

The FPGA embedded FLASH controller provided by the third application example can build a communication link between the Register interface of the main device and the FLASH memory, and the design inherits FPGA programmability and has good compatibility and expansibility. The user can dynamically configure the FLASH memories compatible with different types, so that the application complexity and difficulty are reduced, the usability of the FPGA embedded or externally connected FLASH memory connected with the Register interface of the main device is improved, and the application flexibility of the FPGA embedded or externally connected FLASH memory is improved.

Referring to fig. 11, another embodiment of the present invention further provides an FPGA embedded FLASH controller, which can support multiple communication protocols (also referred to as bus protocols), and can identify a bus type (also referred to as a system bus type) of a communication protocol of a host device. The FPGA embedded FLASH controller 10 specifically comprises a bus interface arbitration enabling module 14, a bus type module 13, an interface module 11, a FLASH logic control module 12 and n FLASH function modules 101-10 n, wherein n is not less than 1.

The structure and function of the FLASH logic control module 12 and the n FLASH function modules 101 to 10n are the same as those in the above embodiment, and reference may be made to the above description of the FLASH logic control module 12 and the n FLASH function modules 101 to 10n, which is not described herein again.

The bus interface arbitration enabling module 14 is connected with the host device 20, the interface module 11 and the bus type module 13 through FPAG logical connection for connecting the host device 20 and the interface module 11, the bus interface arbitration enabling module 14 is driven and enabled by the bus type module 13, and can select a corresponding communication protocol link from the interface module 11 by analyzing the type of the communication protocol bus of the host device 20 to establish a communication connection between the interface module 11 and the host device 20, so that the connection of different system bus interfaces of the same host device 20 and the connection of host devices of different communication protocol types can be supported. The bus interface arbitration enabling module 14 may be implemented based on a multiplexer inside the FPGA.

The bus type module 13 is connected to the master device 20 and the bus interface arbitration enabling module 14, and is mainly used for indicating the type of the master device system bus interface. Generally, the system bus interface of the master device can be generally classified into bus interfaces such as AHB, APB, AXI, WISHBONE, Avalon, etc., so the bus type module 13 has corresponding labels for different types of system bus interfaces, and also has corresponding serial numbers for different types of communication protocol buses (i.e., system buses), and the bus type module 13 can obtain the type information of the communication protocol bus of the master device 20, and enable the interface module 11 according to the type information, so as to establish a corresponding communication protocol link between the interface module 11 and the master device 20. Specifically, the bus type module 13 can control the bus interface arbitration enabling module 14 to switch the corresponding communication link by obtaining the type information of the communication protocol bus, so that the communication connection can be established between the interface module 11 and the master device 20 under the corresponding communication protocol, and the data transmission between the two conforms to the specifications of the corresponding communication protocol.

The interface module 11 is a general bus interface module, and can support multiple communication protocols (i.e. bus protocols), for example, can support the mainstream bus protocols such as AHB, APB, AXI, WISHBONE, Avalon, etc., through the output of the bus type module 13, the bus interface arbitration enabling module 14 can control the interface module 11 to select a bus protocol matching with the communication protocol bus type of the system bus interface of the host device 10 from the inside, so as to support the communication protocol bus of the host device, further enable the host device 20 to access the register inside the FLASH logic control module 12 through the system bus, map the register inside the FLASH logic control module 12 to the memory area (i.e. the address area in the storage address space) corresponding to the host device 20, implement the control of the FLASH logic control module 12 by the host device 20, further select the corresponding FLASH function module through the FLASH logic control module 12, finally, the operations and controls of reading, writing, erasing and the like of the FLASH memories of the corresponding types are achieved.

Referring to fig. 11 and fig. 12, the working flow of the FLASH controller embedded in the FPGA of the present embodiment is as follows: the type of the communication protocol bus of the system bus interface of the connected master device 20 is first determined, and a communication protocol link under a corresponding communication protocol is established according to the determination result. The interface module 11 analyzes operation instructions of the host device 20 such as read data, write data, erase data, and the like. If the main device 20C issues a read data instruction, the interface module 11 selects a read data register in the FLASH logic control module 12 according to the corresponding address signal, and performs a read data operation. If the master device 20 issues a write data command, the interface module 11 selects a write data register in the FLASH logic control module 12 according to the corresponding address signal, and performs a write data operation. If the main device 20 issues a data erasing command, the interface module 11 selects an data erasing register in the FLASH logic control module 12 according to the corresponding address signal, and performs a data erasing operation.

The FPGA embedded FLASH controller of the embodiment can inherit the programmable characteristic of the FPGA, dynamically configure different types of FLASH memories, and identify the bus types of the main equipment to support various communication protocols, so that the FPGA embedded FLASH controller is compatible with different types of main equipment and the main equipment with various different types of communication protocol buses, thereby improving the application flexibility of the main equipment resources, simultaneously improving the usability and flexibility of the FPGA embedded or externally connected FLASH memories, and finally improving the development efficiency and speed of products.

Based on the same inventive concept, referring to fig. 1 to 15, an embodiment of the present invention further provides an electronic device, including an FPGA embedded FLASH controller 10 according to any embodiment of the present invention, and a main device 20 and n FLASH memories 31 to 3n in communication connection with the FPGA embedded FLASH controller 10, where n is greater than or equal to 1.

Optionally, the master device is connected to one FLASH memory through the FPGA embedded FLASH controller 10, or the master device is connected to a plurality of FLASH memories through the FPGA embedded FLASH controller 10 at the same time, and at least two of the plurality of FLASH memories are different in type.

Optionally, referring to fig. 13 to fig. 15, in the electronic device, each FLASH memory is embedded in the FPGA or is disposed outside the FPGA; the main device 20 is embedded in the FPGA or is disposed outside the FPGA. The electronic device can be an FPGA chip, and can also be a system on chip with an MCU and an FPGA integrated together.

In addition, it should be noted that the terms "first", "second", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for representing a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

It is to be further understood that the present invention is not limited to the particular methodology, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims

1. The utility model provides an embedded FLASH controller of FPGA which characterized in that, embedded FLASH controller of FPGA includes:

the FLASH memory management system comprises a plurality of FLASH functional modules, a plurality of FLASH memory management modules and a plurality of FLASH memory management modules, wherein the FLASH functional modules are arranged in a one-to-one correspondence manner with different types of FLASH memories and are connected with the FLASH memories of corresponding types for realizing corresponding functional operation on the connected FLASH memories;

2. The FPGA embedded FLASH controller of claim 1, wherein the FLASH logic control module is configured to map an operation instruction sent by the host device to a relevant operation of a corresponding register, select and match the corresponding FLASH function module, and control the selected FLASH function module to perform a corresponding function operation on the connected FLASH memory according to the relevant operation of the register, so as to implement compatibility of different types of FLASH memories.

3. The FPGA embedded FLASH controller of claim 1 wherein said interface module is communicatively coupled to said master device via a corresponding communication protocol bus, said communication protocol bus being an AHB bus, an APB bus, an AXI bus, a WISHBONE bus, or an Avalon bus; or the interface module is connected with the register interface of the master device.

4. The FPGA embedded FLASH controller of claim 1 wherein said interface module is further configured to decode a memory address space of said host device, parse each register in said FLASH logic control module, and map each of said registers into a different address region of said memory address space of said host device.

5. The FPGA embedded FLASH controller of claim 1 wherein said interface module comprises:

6. The embedded FLASH controller of FPGA of claim 5, wherein when said host device is connected to said interface module via AHB bus, said operation judgment module is further configured to make an operation mode judgment on an operation instruction sent by said host device, said information transmission module comprises a basic mode transmission module, a Burst mode transmission module and a FIFO queue buffer; when the operation judging module judges that the operation mode is a basic transmission mode, enabling the basic mode transmission module, wherein the basic mode transmission module is used for analyzing the data signal and the operation signal sent by the main equipment according to the basic transmission mode specified by an AHB communication protocol and generating the operation signal and the data signal required by the FLASH logic control module; and when the operation judging module judges that the operation mode is the Burst transmission mode, enabling the Burst mode transmission module, wherein the Burst mode transmission module is used for analyzing the data signal and the operation signal sent by the main equipment according to the Burst transmission mode specified by an AHB communication protocol to generate the operation signal and the data signal required by the FLASH logic control module.

7. The embedded FLASH controller of FPGA according to claim 5, wherein when the main device is connected to the interface module via a WISHBONE bus, the operation judgment module is further configured to judge an operation instruction sent by the main device, and transmit a judgment result to the FLASH signal generation module to generate a corresponding operation signal; the information transmission module comprises a data transmission module which is enabled under the control of the operation judgment module and is used for analyzing the data signal sent by the main equipment according to the WISHBONE communication protocol and generating the data signal required by the FLASH logic control module.

8. The FPGA embedded FLASH controller according to any one of claims 1 to 7, wherein the interface module is a universal bus interface module, which contains at least two communication protocols therein, so as to establish a corresponding communication protocol link with different types of master devices or different types of communication protocol buses of the same master device; the embedded FLASH controller of the FPGA also comprises a bus interface arbitration enabling module and a bus type module which are connected with the main equipment, wherein,

9. The FPGA embedded FLASH controller of claim 8 wherein said bus interface arbitration enabling module comprises a multiplexer.

10. The FPGA embedded FLASH controller of claim 1 wherein said FLASH logic control module comprises at least one general purpose register set, each said general purpose register set comprising a control register, a status register, a read-write data register, an erase data register, and a FLASH type select register; and each register in the general register group is connected with a corresponding pin of each FLASH functional module.

11. The embedded FLASH controller of claim 10, wherein the FLASH function module comprises a FLASH internal interface and a FLASH operation module, the FLASH internal interface is used for implementing interaction between the FLASH function module and the FLASH logic control module, and the FLASH operation module is connected to a corresponding FLASH memory for implementing random reading, writing, erasing or controlling of the connected FLASH memory.

12. The FPGA embedded FLASH controller of claim 11 wherein said FLASH internal interface pins comprise: the device comprises a clock pin, a reset pin, a control pin, a state pin, a read-write data pin, an erasing data pin and a FLASH type selection pin; the clock pin is connected with a clock signal on a communication protocol bus in an external mode, the reset pin is connected with a reset signal on the communication protocol bus in an external mode, the control pin is connected with the control register, the state pin is connected with the state register, the read-write data pin is connected with the read-write data register, the erasing data pin is connected with the erasing data register, and the FLASH type selection pin is connected with the FLASH type selection register.

13. The FPGA embedded FLASH controller of claim 10 wherein when said master device is connected to a plurality of FLASH memories simultaneously through said FPGA embedded FLASH controller, said FLASH logic control module further comprises a combinational logic circuit, said combinational logic circuit being connected to said control register and said status register for mapping interrupt signals of each of said FLASH function modules into an interrupt vector table of said master device according to a specified priority, so as to implement priority control of each of said FLASH memories by said master device.

14. The FPGA embedded FLASH controller of claim 1, wherein said master device is connected to one FLASH memory through said FPGA embedded FLASH controller, or wherein said master device is connected to a plurality of FLASH memories simultaneously through said FPGA embedded FLASH controller, and wherein at least two of said plurality of FLASH memories are of different types.

15. The FPGA embedded FLASH controller of claim 14, wherein said FLASH memory is embedded in the same FPGA as said FPGA embedded FLASH controller, or wherein said FLASH memory is disposed outside of the FPGA in which said FPGA embedded FLASH controller is located; the main equipment is embedded in the FPGA where the FPGA embedded FLASH controller is located, or the main equipment is arranged outside the FPGA where the FPGA embedded FLASH controller is located.

16. An electronic apparatus comprising an FPGA-embedded FLASH controller of any one of claims 1-15, and a host device and at least one FLASH memory communicatively connected to the FPGA-embedded FLASH controller.