CN111930167A

CN111930167A - Output stage bleeder circuit applied to ultralow quiescent current LDO

Info

Publication number: CN111930167A
Application number: CN202010645487.4A
Authority: CN
Inventors: 项骏; 冯光涛
Original assignee: Elownipmicroelectronics Beijing Co ltd
Current assignee: Elownipmicroelectronics Beijing Co ltd
Priority date: 2020-07-07
Filing date: 2020-07-07
Publication date: 2020-11-13

Abstract

The invention provides an output stage bleeder circuit applied to an ultralow quiescent current LDO (low dropout regulator), which comprises an operational Amplifier (AMP), a PMOS (P-channel metal oxide semiconductor) power tube (MP), a pair of PMOS tubes (MP 1), an NMOS (N-channel metal oxide semiconductor) tube (MN 1) and an MN2, wherein the inverting input end of the operational Amplifier (AMP) is connected with a reference voltage Vref, the non-inverting input end of the operational Amplifier (AMP) is connected with a voltage feedback Vfb, the grid electrode of the power tube (MP) is connected with the output end of the operational Amplifier (AMP), and the drain electrode of the power tube; according to the scheme, the bleeder circuit with high matching degree can realize the leakage problem of the output stage MP of the ultralow quiescent current LDO at different process angles, temperatures and voltages, and can realize the ultralow quiescent current of the output stage.

Description

Output stage bleeder circuit applied to ultralow quiescent current LDO

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to an output stage bleeder circuit applied to an ultra-low static current LDO (low dropout regulator).

Background

The LDO (linear regulator) is a general regulator, and has the advantages of small jitter ripple and high PSRR compared to the switching regulator, and as shown in fig. 1, the operational amplifiers AMP and MP, R1, and R2 form a closed circuit loop, and the output Vout of the LDO is VREF (R2+ R1)/R2. In some applications with extremely low power consumption, such as systems of internet of things, handheld devices, and the like, the static power consumption of the LDO itself may increase the static power consumption of the systems, and reduce the use efficiency of energy. In the whole loop, both AMP and output stage MP contribute to quiescent current, and if the quiescent current of LDO is to be small, the quiescent current of AMP and MP must be reduced. However, MP itself has leakage current, and this leakage current is easily influenced by technology, voltage, and temperature, and when the leakage current of MP is greater than the quiescent current that flows in R1 and R2, the whole LDO loop cannot be stable, and when the LDO is idle in corresponding actual use, the LDO output voltage is unstable.

Referring to fig. 2, an authorized publication of chinese utility model with CN208819106U, entitled "LDO circuit with ultra-low static power consumption and LDO circuit with ultra-low static power consumption driving a large load" is to hang a backward diode D1 on the load of LDO to absorb the leakage current of MP, which has a disadvantage that it is difficult to minimize the static current because the diode D1 and MP are different devices and are not well matched under different processes, temperatures, and voltages. Although they all achieve leakage current absorption of the LDO output stage MP with low static power consumption, they still have the above drawbacks.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide an output stage bleeder circuit applied to an ultra-low static current LDO, and the output stage bleeder circuit solves the problem of unstable output voltage generated by the output stage MP leakage current of the ultra-low static current LDO when the LDO is in no-load.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

the output stage bleeder circuit comprises an operational Amplifier (AMP), a PMOS power tube (MP), a pair of PMOS tubes (MP 1), an NMOS tube (MN 1) and an MN2, wherein the inverting input end of the operational Amplifier (AMP) is connected with a reference voltage Vref, the non-inverting input end of the operational Amplifier (AMP) is connected with a voltage feedback (Vfb), the grid electrode of the power tube (MP) is connected with the output end of the operational Amplifier (AMP), the drain electrode of the power tube (MP) is connected with a working voltage Vdd, and the width-length ratio of each PMOS tube (MP 1) to the power tube (MP) is set in proportion.

In some embodiments, the drains and gates of a pair of PMOS transistors MP1 are respectively and correspondingly connected, the source of one PMOS transistor is respectively connected to the source and gate of NMOS transistor MN2, the drain of NMOS transistor MN2 is connected to the source of another PMOS transistor through a set bias current I b, the drain of NMOS transistor MN2 is connected to the drain of NMOS transistor MN1, the drain of NMOS transistor MN1 is grounded, the gates of NMOS transistor MN1 and MN2 are connected, and the source of NMOS transistor MN1 is connected to the source of PMOS transistor MP.

In some embodiments, the width-to-length ratio between the NMOS transistors MN1 and NM2 is proportionally set.

In some embodiments, the source of the power transistor MP is connected to the non-inverting input terminal of the operational amplifier AMP via a resistor Rf1, and the source of the power transistor MP is connected to the external load Vout.

In some embodiments, the source of the MOS transistor MP is grounded via resistors Rf1 and Rf2, wherein the non-inverting input terminal of the operational amplifier AMP is connected between the resistors Rf1 and Rf 2.

Compared with the traditional technical scheme, the technical scheme has the beneficial effects that: according to the scheme, the bleeder circuit with high matching degree can realize the leakage problem of the output stage MP of the ultralow quiescent current LDO at different process angles, temperatures and voltages, and can realize the ultralow quiescent current of the output stage.

Drawings

Fig. 1 is a circuit configuration diagram of a conventional linear voltage regulator circuit (LDO).

Fig. 2 is a circuit configuration diagram of a conventional linear voltage regulator circuit (LDO).

Fig. 3 is a circuit diagram of an output stage bleeder circuit applied to an ultra-low quiescent current LDO in the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the detailed description.

The invention aims at the problem that the existing ultralow static current LDO circuit is not stable in no-load caused by the leakage current of an output stage MP, so that the problem of nA-level static power consumption is difficult to achieve, and further provides an output stage bleeder circuit applied to the ultralow static current LDO.

Referring to fig. 3, the output stage bleeder circuit applied to the ultra-low quiescent current LDO in this embodiment includes an operational amplifier AMP, a PMOS power transistor MP, a pair of PMOS transistors MP1, an NMOS transistor MN1 and an NMOS 2, wherein an inverting input terminal of the operational amplifier AMP is connected to a reference voltage Vref, a non-inverting input terminal of the operational amplifier AMP is connected to a voltage feedback Vfb, a gate of the power transistor MP is connected to an output terminal of the operational amplifier AMP, a drain of the power transistor MP is connected to a working voltage Vdd, a width-to-length ratio of each PMOS transistor MP1 and the power transistor MP is set in proportion, a drain and a gate between the pair of PMOS transistors MP1 are respectively connected correspondingly, a source of one PMOS transistor is connected to a source and a gate of an NMOS transistor MN2, a drain of an NMOS transistor MN2 and a source of the other PMOS transistor are connected to a bias current Ib, a drain of the NMOS transistor MN2 is connected to a drain of the NMOS transistor MN1, and a drain of the NMOS transistor MN1 is grounded, the gate of MN1 and MN2 of NMOS transistor are connected, the source of MN1 of NMOS transistor is connected with the source of PMOS transistor MP, and the width-to-length ratio between MN1 and NM2 of NMOS transistor is proportionally set.

In one embodiment, the source of the MOS transistor MP is grounded through the resistors Rf1 and Rf2, wherein the non-inverting input terminal of the operational amplifier AMP is connected between the resistors Rf1 and Rf2, and the source of the power transistor MP is connected to the external load Vout.

The following description is made on the working principle of the output stage bleeder circuit:

MP1 is two identical PMOS devices that are matched to the LDO output stage power transistor MP, and the width-to-length ratio is proportional, which can be determined by different designs. The bias current Ib of MP1 is the bias current of the whole low power LDO, and is a tiny current source in the nA level. MN1 and MN2 are also a stack of matched NMOS devices, and the aspect ratio between them is also proportional and can be determined according to different designs. MN2 will mirror the leakage current of Ib and MP1 through MN1 to the current branch where MP is located. When Vout of the LDO is idle, if MP has a leakage current to ground, MP1 also generates a leakage current to ground due to matching of MP1 and MP, so that the leakage current of MP can be discharged through NM1, and the stability of the LDO is not affected.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. The output stage bleeder circuit is characterized by comprising an operational amplifier AMP, a PMOS power tube MP, a pair of PMOS tubes MP1, an NMOS tube MN1 and an MN2, wherein the inverting input end of the operational amplifier AMP is connected with a reference voltage Vref, the non-inverting input end of the operational amplifier AMP is connected with a voltage feedback Vfb, the grid electrode of the power tube MP is connected with the output end of the operational amplifier AMP, the drain electrode of the power tube MP is connected with a working voltage Vdd, and the width-length ratio of each PMOS tube MP1 to the power tube MP is set in proportion.

2. The output stage bleeder circuit applied to an ultra-low quiescent current LDO according to claim 1, wherein a drain and a gate between a pair of said PMOS transistors MP1 are respectively and correspondingly connected, a source of one said PMOS transistor is respectively connected with a source and a gate of an NMOS transistor MN2, a drain of an NMOS transistor MN2 is connected with a source of another PMOS transistor through a bias current Ib, a drain of an NMOS transistor MN2 is connected with a drain of an NMOS transistor MN1, a drain of an NMOS transistor MN1 is grounded, gates of an NMOS transistor MN1 and an MN2 are connected, and a source of an NMOS transistor MN1 is connected with a source of the PMOS transistor MP.

3. The output stage bleeder circuit applied to an ultra-low static current LDO as claimed in claim 2, wherein the width-to-length ratio between the NMOS transistors MN1 and NM2 is proportionally set.

4. The output stage bleeder circuit as claimed in claim 1, wherein the source of the power transistor MP is connected to the non-inverting input terminal of the operational amplifier AMP via a resistor Rf1, and the source of the power transistor MP is connected to the external load Vout.

5. The output stage bleeder circuit applied to an ultra-low quiescent current LDO according to claim 2, wherein the source of the MOS transistor MP is grounded via resistors Rf1 and Rf2, and wherein the non-inverting input terminal of the operational amplifier AMP is connected between the resistors Rf1 and Rf 2.