CN111936949A - Driver circuit and related chips - Google Patents

Abstract

The application discloses a driving circuit (200) and a related chip. The driving circuit comprises a logic circuit (110), a push-pull circuit (120) and a control circuit (210), wherein the logic circuit is used for generating a data signal; the push-pull circuit includes: a first transistor (M1) for, when the data signal transitions from a first logic state to a second logic state, transitioning the potential of the output terminal of the driving circuit from a first potential corresponding to the first logic state to a second potential corresponding to the second logic state during the first transition; the control circuit is coupled to the push-pull circuit and used for controlling the current flowing through the first transistor to be a first constant current (ics1) before the potential of the output end reaches the second potential during the first transition state.

Description

Driver circuit and related chips

technical field

The present application relates to a circuit, and in particular, to a drive circuit and related chips.

Background technique

The interface of the integrated circuit usually needs to comply with some design specifications of electronic components, for example, the general-purpose input/output interface (general-purpose input/output) needs to comply with the electromagnetic interference (electromagnetic interference, EMI) design specifications. Therefore, an innovative design is needed to reduce the EMI of existing interfaces.

SUMMARY OF THE INVENTION

One of the objectives of the present application is to disclose a circuit, especially a driving circuit and related chips, to solve the above problems.

An embodiment of the present application discloses a driving circuit, including a logic circuit, a push-pull circuit, and a control circuit, wherein the logic circuit is used to generate a data signal; the push-pull circuit includes: a first transistor, used for When the data signal transitions from the first logic state to the second logic state, transition the potential of the output terminal of the driving circuit from the first potential corresponding to the first logic state to the corresponding potential during the first transition period a second potential of the second logic state; the control circuit, coupled to the push-pull circuit, is used for, during the first transition period, before the potential of the output terminal reaches the second potential, The current flowing through the first transistor is controlled to be a first constant current.

An embodiment of the present application discloses a chip including the aforementioned driving circuit.

The driving circuit disclosed in the present application can control the current flowing through the turned-on pull-up transistor or the turned-on pull-down transistor to be a constant current. Accordingly, the slew rate of the pull-up transistor and the pull-down transistor can be controlled to improve the EMI problem during each on-period.

Description of drawings

The circuit diagram of FIG. 1A illustrates the charging operation of the drive circuit.

The voltage waveform diagram of FIG. 1B illustrates the relationship between the voltage and time of the output terminal of the driving circuit under the operation of charging the equivalent capacitor.

The circuit diagram of FIG. 1C illustrates the discharge operation of the drive circuit.

The voltage waveform diagram of FIG. 1D illustrates the relationship between the voltage and time of the output terminal of the driving circuit under the operation of discharging the equivalent capacitor.

The circuit diagram of FIG. 2A illustrates the charging operation of the driver circuit of the present application.

The voltage waveform diagram of FIG. 2B illustrates the relationship between the voltage and time of the output terminal of the driving circuit of FIG. 2A under the operation of charging the equivalent capacitor.

The circuit diagram of FIG. 2C illustrates the discharge operation of the driver circuit of the present application.

The voltage waveform diagram of FIG. 2D illustrates the variation of the voltage with respect to time at the output terminal of the driving circuit of FIG. 2C under the operation of discharging the equivalent capacitor.

FIG. 3 is a circuit diagram of yet another embodiment of the driving circuit of the present application.

FIG. 4 is a circuit diagram of yet another embodiment of the driving circuit of the present application.

FIG. 5 is a circuit diagram of yet another embodiment of the driving circuit of the present application.

Detailed ways

The following disclosure provides various implementations, or illustrations, that can be used to implement various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. As can be appreciated, these descriptions are exemplary only, and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments in which the first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms, such as "below", "below", "below", "above", "above" and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature. These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broader scope of the application are approximations, the numerical values set forth in the specific examples have been reported as precisely as possible. Any numerical value, however, inherently contains the standard deviation resulting from individual testing methods. As used herein, "same" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "same" means that the actual value lies within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that all ranges, quantities, numerical values and percentages used herein (for example, to describe material amounts, time durations, temperatures, operating conditions, quantity ratios and other similar) are modified by "same". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying claims are approximate numerical values and may be changed as required. At a minimum, these numerical parameters should be construed to mean the number of significant digits indicated and the numerical values obtained by applying ordinary rounding. Numerical ranges are expressed herein as from one endpoint to the other or between the endpoints; unless otherwise indicated, the numerical ranges recited herein are inclusive of the endpoints.

In general, input/output interfaces, such as general-purpose input/output (GPIO), are usually composed of transistors. During operation, the transistor charges or discharges the equivalent capacitance seen from the output end of the input/output interface, so that the input/output interface outputs a high potential or a low potential. For example, the circuit diagrams of FIGS. 1A and 1C illustrate charging and discharging operations of the drive circuit 100 , respectively.

Referring to FIG. 1A , the driving circuit 100 includes a logic circuit 110 and a push-pull circuit 120 . The push-pull circuit 120 includes a P-type transistor M1 and an N-type transistor M2, which are connected in series between a specific voltage VDD and VSS. Specifically, the source and drain of the transistor M1 are respectively coupled to a specific voltage VDD and the drain of the transistor M2, and the source of the transistor M2 is coupled to a specific voltage VSS. In some embodiments, the specific voltages VDD and VSS are the same in magnitude and opposite in polarity. In some embodiments, the specific voltage VSS is referenced to ground.

The logic circuit 110 is coupled to the transistors M1 and M2, and is used to turn on only one of the transistors M1 and M2 at any time according to the enable signal EN and the data signal D (ie, the transistors M1 and M2 are not turned on at the same time). Logic Circuit 110 For example, the logic circuit 110 includes a NOT gate 112 , a NAND gate 114 and a NOR gate 116 . The data signal D is transmitted to the gates of the transistors M1 and M2 through the NAND gate 114 and the NOR gate 116, respectively. Specifically, based on the enable signal EN of logic 1, the NAND gate 114 inverts the logic state of the received data signal D, and then outputs the inverted data signal D to the gate of the transistor M1. Based on the enable signal EN of logic 1, the NOR gate 116 inverts the logic state of the received data signal D, and then outputs the inverted data signal D to the gate of the transistor M2.

The drains of the transistor M1 and M2 form the output terminal OUT. In FIG. 1A, the transistor M2 is non-conducting and the transistor M1 is conducting. The transistor M1 uses a specific voltage VDD to charge the equivalent capacitance CL seen by the output terminal OUT to output the output The potential of the terminal OUT transitions from a first potential (about VSS, corresponding to a logic 0) to a second potential (about VDD, corresponding to a logic 1) during the rising transition period. It should be noted that the rising transition period refers to a period during which the potential continues to rise, and does not include a period during which the potential reaches the second potential and remains at the second potential without further rising. In FIG. 1C , when the transistor M1 is not turned on and the transistor M2 is turned on, the transistor M2 discharges the equivalent capacitor CL with a specific voltage VSS, so as to reduce the potential of the output terminal OUT from the second potential (about VDD) during the falling transition period. ) transitions to the first potential (approximately VSS). The falling transition period refers to a period during which the potential continues to drop, and does not include a period during which the potential reaches the first potential and remains at the first potential without further falling.

The voltage waveform diagrams of FIG. 1B and FIG. 1D respectively illustrate the relationship between the voltage and time of the output terminal OUT of the driving circuit 100 under the charging operation and the discharging operation of the equivalent capacitor CL. In FIGS. 1B and 1D , the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 100 , and the horizontal axis represents time. Referring to FIG. 1B , observing the curve change of the waveform 130 , the potential of the output terminal OUT rapidly climbs to Vr with a steep slope at the initial stage of charging (period dTr), resulting in a large change in the drain-source voltage of the transistor M1 in a short time, that is, The slew rate is too large; similarly, observe the curve change of the waveform 135 in FIG. 1D , the potential of the output terminal OUT decreases rapidly to Vf with a steep slope at the initial stage of discharge (dTf), which will also cause the slew rate of the transistor M2 is too big. Since the greater the slew rate, the greater the EMI, the subsequent embodiments will improve the EMI problem by controlling the slew rate of the transistors M1 and M2 of the push-pull circuit 120 .

<Example 1>

The circuit diagrams of FIGS. 2A and 2C illustrate charging and discharging operations of the drive circuit 200, respectively. Referring to FIG. 2A , the driving circuit 200 is similar to the driving circuit 100 of FIG. 1A , the difference is that the driving circuit 200 further includes a control circuit 210 , and the control circuit 210 is coupled to the push-pull circuit 120 . In this embodiment, the control circuit 210 includes a current source Ir and a current sink Ik.

The current source Ir receives a specific voltage VDD and is coupled to the source of the transistor M1. In FIG. 2A , the transistor M2 is turned off and the transistor M1 is turned on, and the current source Ir is used to continuously provide a constant current ics1 through the transistor M1 to the output terminal OUT during the on period of the transistor M1 to charge the equivalent capacitor CL. In short, the current source Ir controls the current flowing through the transistor M1 to be a constant current ics1. In this embodiment, the constant current means that the magnitude of the current does not change with time.

In some embodiments, the current source Ir can be implemented as a single P-type transistor, wherein the source of the P-type transistor receives a specific voltage VDD, the gate is controlled by the control voltage, and the drain is coupled to the source of the transistor M1 pole.

The current sink Ik receives a specific voltage VSS and is coupled to the source of the transistor M2. In FIG. 2C , the transistor M1 is turned off and the transistor M2 is turned on, and the current sink Ik is used to continuously draw the constant current ics2 from the output terminal OUT through the transistor M2 to discharge the equivalent capacitance CL during the conduction period of the transistor M2 . In short, the current sink Ik controls the current flowing through the transistor M2 to be a constant current ics2.

In some embodiments, the current sink Ik can be implemented as a single N-type transistor, wherein the source of the N-type transistor receives a specific voltage VSS, the gate is controlled by another control voltage, and the drain is coupled to transistor M2 the source.

The voltage waveform diagrams of FIGS. 2B and 2D respectively illustrate the relationship between the voltage and time of the output terminal OUT of the driving circuit 200 when the equivalent capacitor CL is charged and discharged. In FIGS. 2B and 2D , the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 200 , and the horizontal axis represents time.

For the convenience of comparison, in FIG. 2B , the waveform 130 of FIG. 1B is shown. Comparing the waveforms 230 and 130, it can be observed that the potential of the output terminal OUT indicated by the waveform 230 climbs to Vr at a relatively small absolute value and a substantially constant slope at the initial stage of charging (period dTr) compared to the waveform 130 of FIG. 1B . This means that the transistor M1 of FIG. 2A is smaller in the slew rate of the drain-source voltage than the transistor M1 of FIG. 1A in the early stage of charging.

Likewise, for the convenience of comparison, in FIG. 2D , the waveform 135 of FIG. 1D is shown. Comparing the waveforms 235 and 135, it can be observed that the potential of the output terminal OUT indicated by the waveform 235 decreases to Vr with a relatively small absolute value and a substantially constant slope at the initial stage of discharge (period dTf) compared to the waveform C135 of FIG. 1D. This means that the transistor M2 of FIG. 2C is smaller in the slew rate of the drain-source voltage than the transistor M2 of FIG. 1C in the initial stage of discharge.

Since the slew rate of each of the transistors M1 and M2 can be controlled, the problem of EMI in the initial stage of discharge and initial stage of charging can be improved, and the EMI can be complied with the specification.

<Example 2>

FIG. 3 is a circuit diagram of an embodiment of the driving circuit 300 of the present application. Referring to FIG. 3 , the driving circuit 300 is similar to the driving circuit 200 of FIG. 2A , the difference is that, compared with the control circuit 210 of FIG. 2A , the control circuit 310 of the driving circuit 300 further includes: a reference current source Iref and transistors M3 , M4 , M5 , M6 and M7.

Transistors M3 and M4 form a current mirror. Since this current mirror receives a constant current iref (which may be referred to as a reference constant current where appropriate) from a reference current source Iref, this current mirror may be referred to as a source current mirror where appropriate, and transistors M3 and M4 may be referred to as a reference where appropriate transistor. In detail, the gate and drain of the transistor M3 are short-circuited, and the gate of the transistor M4 is short-circuited. The source current mirror replicates the constant current iref received by transistor M3 and outputs the constant current icof (which may be referred to as a replicated constant current where appropriate) through transistor M4. In addition to the source current mirror, the driving circuit 300 also includes other current mirrors, which are described in detail as follows.

Transistor M3 also forms a current mirror with transistor M7, which may be referred to as a first current mirror where appropriate. Specifically, the gate of the transistor M3 is further short-circuited to the gate of the transistor M7. The first current mirror replicates the constant current iref received by the transistor M3 and outputs the constant current ic1 through the transistor M7. Since transistor M7 provides the function of a current sink, it may also be referred to as a current sink transistor where appropriate.

Transistors M5 and M6 form a current mirror, which may be referred to as a second current mirror where appropriate. Specifically, the gate and drain of the transistor M5 are short-circuited, and the gate of the transistor M6 is short-circuited. The second current mirror replicates the constant current icof received by the transistor M5 and outputs the constant current ic2 through the transistor M6. Since transistor M6 provides the function of a current source, it may also be referred to as a current source transistor where appropriate.

In the charging operation, since the transistors M1 and M6 are connected in series, when the transistor M1 is turned on, the transistor M6 continues to provide the constant current ic2 to the output terminal OUT through the transistor M1 .

In the discharge operation, since the transistors M2 and M7 are connected in series, when the transistor M2 is turned on, the transistor M7 continues to draw the constant current ic1 from the output terminal OUT through the transistor M2 .

Based on the same reason as described in the first embodiment, since the respective slew rates of the transistors M1 and M2 can be controlled, the driving circuit 300 of the present application can improve the EMI problem in the initial stage of discharge and initial stage of charging, and make the EMI meet the specifications.

<Example 3>

FIG. 4 is a circuit diagram of an embodiment of the driving circuit 400 of the present application. Referring to FIG. 4 , the driving circuit 400 is similar to the driving circuit 300 of FIG. 3 , except that the control circuit 410 of the driving circuit 400 further includes transistors M8 , M9 and M10 , and transistors M3 and M5 compared with the control circuit 310 of FIG. 3 . The respective connection methods are different from the respective connection methods of the transistors M3 and M5 of the control circuit 310 . In this embodiment, each of the transistors M8, M9 and M10 can be used as a resistor, and the detailed description is as follows.

The circuit operator can change the current level of the reference current source Iref as necessary to adjust the size of the constant current iref, thereby allowing the charging and discharging time of the parasitic capacitor CL to meet the specification requirements. In order to accurately adjust the charging and discharging time of the parasitic capacitance CL, it is necessary to accurately adjust the magnitudes of the constant currents ic1 and ic2.

In order to achieve the above-mentioned purpose, a feasible way is to make the changes of the constant current iref and ic1 as equal as possible to each other, and to make the changes of the constant current iref and ic2 as equal as possible to each other. Incidentally, since the constant current ic2 is directly copied from the constant current icof and indirectly copied from the constant current iref, the changes between the constant current iref, icof and ic2 are also equal.

One possible way to achieve this is to (1) make the equivalent circuits through which the constant currents iref and ic1 flow as equal as possible to each other; and, (2) make the equivalent circuits through which the constant currents iref, icof and ic2 flow as equal as possible to each other .

Regarding the above (1), the equivalent circuit through which the constant current ic1 flows is constituted by the transistors M2 and M7 connected in series, and the transistor M2 receives a voltage equivalent to the specific voltage VDD. Accordingly, a transistor M8 is added, and the transistor M8 and M3 are connected in series. Also, in order for transistor M8 to emulate the behavior when transistor M2 is turned on, the gate of transistor M8 is made to receive a specific voltage VDD. In this way, the equivalent circuits through which the constant currents ic1 and iref flow are as equal as possible to each other.

For the above (2), the equivalent circuit through which the constant current ic2 flows is constituted by the transistors M1 and M6 connected in series, and the transistor M1 receives a voltage equivalent to the specific voltage VSS. Accordingly, a transistor M10 is added, and the transistors M10 and M5 are connected in series. Also, in order for transistor M10 to emulate the behavior of transistor M1 when it is turned on, the gate of transistor M10 is made to receive a specific voltage VSS. In this way, the equivalent circuits through which the constant currents ic2 and icof flow are as equal as possible to each other. In addition, the equivalent circuit through which the constant current iref flows is constituted by the series-connected transistors M3 and M8, and the transistor M8 receives a specific voltage VDD. Accordingly, a transistor M9 is added, and the transistor M9 and M4 are connected in series. Also, in order for the transistor M9 to emulate the behavior when the transistor M8 is turned on, the gate of the transistor M9 is also made to receive a certain voltage VDD. In this way, the equivalent circuits through which the constant currents icof and iref flow are as equal as possible to each other. To sum up, the equivalent circuits through which the constant currents iref, icof and ic2 flow are as equal as possible to each other.

In addition to viewing from the viewpoint of the equivalent circuit, it can also be viewed from the viewpoint of the equivalent impedance. In short, let the resistance value with respect to the drain of transistor M3 be the same as the resistance value with respect to the drain of transistor M7 as much as possible. Therefore, transistor M8 is added in series with the stack of transistor M3. Accordingly, transistor M8 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of transistor M3 is related to the on-resistance of transistor M8, and the resistance value with respect to the drain of transistor M7 is related to the on-resistance of transistor M2. That is, the transistor M8 can be used as a resistor.

Similarly, let the resistance value relative to the drain of the transistor M5 be the same as the resistance value relative to the drain of the transistor M6 as much as possible. Therefore, the transistor M10 is added to be stacked in series with the transistor M5. Accordingly, transistor M10 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of transistor M5 is related to the on-resistance of transistor M10, and the resistance value with respect to the drain of transistor M6 is related to the on-resistance of transistor M1. That is, the transistor M10 can be used as a resistor.

In addition, the resistance value with respect to the drain of the transistor M4 is made the same as the resistance value with respect to the drain of the transistor M3 as much as possible. Therefore, transistor M9 is added to be stacked in series with transistor M4. Accordingly, transistor M9 may be referred to as a stacked transistor where appropriate. Further, the resistance value with respect to the drain of transistor M4 is related to the on-resistance of transistor M9, and the resistance value with respect to the drain of transistor M3 is related to the on-resistance of transistor M8. That is, the transistor M9 can be used as a resistor.

To sum up, the driving circuit 400 of the present application can not only improve the EMI problem in the initial stage of discharge and initial stage of charging, but also can accurately adjust the magnitudes of the constant currents ic1 and ic2 .

<Example 4>

FIG. 5 is a circuit diagram of an embodiment of a driving circuit 500 of the present application. Referring to FIG. 5 , the driving circuit 500 is similar to the driving circuit 400 in FIG. 4 , the main difference is that the stacking manner of the transistor M1 of the push-pull circuit 120 and the transistor M6 of the control circuit 510 is opposite to the stacking manner of FIG. The vertical direction of the transistor M2 of the pull circuit 120 and the transistor M7 of the control circuit 510 is opposite to that of FIG. 4 .

In detail, the transistor M1 becomes stacked above the transistor M6, that is, the transistor M1 is coupled between the source of the transistor M6 and the specific voltage VDD. The transistor M2 becomes stacked under the transistor M7, that is, coupled between the source of the transistor M7 and the specific voltage VSS.

In order to accurately adjust the magnitudes of the constant currents ic1 and ic2, based on the same reason as in the embodiment of FIG. 4, in response to the stacking changes of the transistors M1 and M6, the transistor M10 becomes stacked above the transistor M5 and is coupled to the transistor M5 between the source and a specific voltage VDD. Also, in order for transistor M10 to emulate the behavior of transistor M1 when it is turned on, the gate of transistor M10 is made to receive a specific voltage VSS. In addition, in order to form a current mirror, the drain and gate of the transistor M5 are short-circuited to each other, and the drain of the transistor M5 is also short-circuited to the gate of the transistor M6. Overall, the transistors M5, M6 and M10 form the aforementioned second current mirror.

Similarly, in response to the stacking changes of the transistors M2 and M7, the transistor M3 becomes stacked above the transistor M8, coupled between the reference current source Iref and the drain of the transistor M8. Also, in order for transistor M8 to emulate the behavior when transistor M2 is turned on, the gate of transistor M8 is made to receive a specific voltage VDD. To form a current mirror, the drain and gate of transistor M3 are short-circuited to each other, and the drain of transistor M3 is also short-circuited to the gate of transistor M7. Overall, the transistors M3, M7 and M8 form the aforementioned first current mirror.

Similarly, in response to the stacking changes of transistors M3 and M8, transistor M4 becomes stacked above transistor M9, coupled between the drain of transistor M9 and the drain of transistor M5. Also, in order for transistor M9 to emulate the behavior when transistor M8 is turned on, the gate of transistor M9 is made to receive a specific voltage VDD. To form a current mirror, the gate of transistor M4 is coupled to the gate of transistor M3. Overall, the transistors M3, M4, M8 and M9 form the aforementioned source current mirror.

To sum up, the driving circuit 500 of the present application can not only improve the EMI problem in the initial stage of discharge and initial stage of charging, but also can accurately adjust the magnitudes of the constant currents ic1 and ic2 .

The present application also provides a chip, which includes the driving circuit 200 , 300 , 400 or 500 , for example, the chip can be a semiconductor chip realized by different processes.

The foregoing description briefly sets forth features of certain embodiments of the application, so that those skilled in the art to which this application pertains can more fully understand the various aspects of the present disclosure. It should be apparent to those skilled in the art to which this application pertains that they can readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and/or of the embodiments described herein achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit of the present disclosure. with scope.

Claims (22)

1. A drive circuit comprises a logic circuit, a push-pull circuit and a control circuit, wherein

The logic circuit is used for generating a data signal;

the push-pull circuit includes: a first transistor for switching a potential of an output terminal of the driving circuit from a first potential corresponding to a first logic state to a second potential corresponding to a second logic state during a first transition when the data signal transitions from the first logic state to the second logic state;

the control circuit is coupled to the push-pull circuit and used for controlling the current flowing through the first transistor to be a first constant current before the potential of the output end reaches the second potential during the first transition state.

2. The drive circuit of claim 1, wherein the push-pull circuit further comprises:

a second transistor for switching a potential of the output terminal from the second potential to the first potential during a second transition when turned on,

wherein the first transistor and the second transistor are not turned on at the same time.

3. The driving circuit as claimed in claim 2, wherein the control circuit is configured to control the current flowing through the second transistor to be a second constant current during the second transition.

4. The drive circuit of claim 3, wherein the first constant current is the same as the second constant current.

5. The drive circuit of claim 3, wherein the control circuit comprises:

a current source for continuously providing the first constant current to the output terminal via the first transistor during a conduction period of the first transistor.

6. The drive circuit of claim 5, wherein the control circuit further comprises:

a current sink for continuously drawing the second constant current from the output terminal through the second transistor during a turn-on period of the second transistor.

7. The drive circuit of claim 6, wherein the control circuit further comprises:

a source current mirror for receiving a reference constant current and outputting a replica constant current by replicating the reference constant current; and

a second reference transistor coupled to the source current mirror to receive the replica constant current, wherein the second reference transistor and the current source form a second current mirror.

8. The drive circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink form a first current mirror, the first reference transistor receiving the reference constant current, wherein a gate and a drain of the first reference transistor are short-circuited.

9. The driving circuit of claim 8, wherein the gate and drain of the second reference transistor are short-circuited.

10. The drive circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink form a first current mirror, wherein the current sink comprises:

a current sink transistor connected in series with the second transistor and having a gate short-circuited to a gate of the first reference transistor,

wherein the equivalent impedance to the current sink transistor is the same as the equivalent impedance to the first reference transistor.

11. The drive circuit of claim 10, wherein the source current mirror further comprises:

a first stacked transistor connected in series with the first reference transistor,

wherein the equivalent impedance with respect to the first reference transistor is related to the on-resistance of the first stacked transistor.

12. The drive circuit of claim 11, wherein the current source comprises:

a current source transistor connected in series with the first transistor and having a gate short-circuited to a gate of the second reference transistor,

wherein the equivalent impedance with respect to the current source transistor is the same as the equivalent impedance with respect to the second reference transistor.

13. The drive circuit of claim 12, wherein the second current mirror further comprises:

a second stacked transistor connected in series with the second reference transistor,

wherein the equivalent impedance with respect to the second reference transistor is related to the on-resistance of the second stacked transistor.

14. The drive circuit of claim 13, wherein the source current mirror further comprises:

a third reference transistor having a gate short-circuited to the gate of the first reference transistor; and

and the third stacked transistor is connected with the third reference transistor in series, and the grid electrode of the third stacked transistor is in short circuit connection with the grid electrode of the first stacked transistor.

15. The driving circuit as claimed in claim 14, wherein the gate of the first stacked transistor is for receiving a first supply voltage.

16. The driver circuit of claim 15, wherein the gate of the second stacked transistor is to receive a second supply voltage, different from the first supply voltage.

17. The drive circuit of claim 16, wherein the drain of the first stack transistor, the gate of the first reference transistor, and the gate of the current sink transistor are short-circuited to each other.

18. The driving circuit as claimed in claim 17, wherein the drain of the second stacked transistor, the gate of the second reference transistor, and the gate of the current source transistor are short-circuited to each other.

19. The drive circuit of claim 16, wherein the drain and gate of the first reference transistor are shorted with the gate of the current sink transistor.

20. The driving circuit as claimed in claim 19, wherein the drain and gate of the second reference transistor and the gate of the current source transistor are short-circuited to each other.

21. The driving circuit according to claim 2, wherein the first transistor and the second transistor have different polarities, and the digital signals received by the gates of the respective transistors have the same logic state.

22. A chip, wherein the chip comprises:

a driver circuit as claimed in any one of claims 1 to 21.

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