CN111934537A - Anti-interference method for driving signal of cascade converter - Google Patents

Abstract

The invention belongs to the technical field of multi-level converters, and discloses an anti-interference method for driving signals of cascaded converters. An FPGA encodes a PWM driving signal generated by internal carrier modulation according to a specific form, and adds a start code and a stop to the encoding. The CPLD receives the encoded signal and compares and decodes it one by one. When the received start code, PWM signal encoding and stop code are all correct, the PWM drive signal output by the CPLD is updated to The currently received logic level; otherwise, the output PWM drive signal level state remains unchanged. The invention avoids the direct long-line transmission of the PWM driving signal and is affected by the high-frequency electromagnetic interference generated in the switching process of the power device, improves the anti-interference ability of the PWM driving signal for long-line transmission; at the same time, it can also automatically filter out the PWM generated by the high-frequency modulation. Narrow pulse signal, reduce the switching loss of high-power switching devices.

Description

A kind of anti-interference method of cascade converter drive signal

technical field

The invention belongs to the technical field of multi-level converters, and in particular relates to an anti-interference method for driving signals of cascaded converters.

Background technique

At present, multilevel converters are widely used in medium and low-voltage devices due to their large number of output levels, good voltage/current harmonic characteristics, small voltage stress of switching devices, small electromagnetic interference, and the ability to use low-voltage devices to achieve high-voltage output. High voltage and high power occasions.

Among them, the cascaded multi-level circuit is a typical multi-level topology. Each phase is formed by stacking several single-phase full-bridge circuits in series. Compared with the clamp type and flying capacitor type multi-level circuits, there is no need to consider complex capacitance The problem of voltage balance, and a large number of clamping diodes and flying capacitors are omitted. At the same time, it also has the advantages of high equivalent switching frequency and easy expansion of modularization. Therefore, it is used in high-voltage motor drives, photovoltaic new energy grid-connected power generation/battery energy storage systems and static synchronous compensators are widely used. In practical application of this circuit topology, each H-bridge arm needs to provide four-way drive signals, and since there are several H-bridges in each phase, the entire circuit needs more PWM drive signals. Therefore, in order to meet the needs of cascaded multi-level circuits and multiple PWM drive signals, and to take into account the purpose of modular control and management of power units.

Under the realistic condition that it is difficult for a single digital signal processor (DSP) to provide multi-channel driving signals, the required multi-channel PWM driving signals are usually generated by the combination of multiple processors, and the modules of the power unit are realized at the same time. control and management.

Through the above analysis, the existing problems and defects in the prior art are as follows: (1) The multi-processor combination method in the prior art also causes the PWM drive signal to be transmitted through a long line before it can act on the target switching device. In medium-high-voltage and high-power industrial applications, the switching process of power devices will generate strong high-frequency electromagnetic interference, which can easily cause the PWM drive signal transmitted through long lines to be affected by high-frequency electromagnetic interference, resulting in abnormal pulses in the drive signal. These abnormal interference pulses may cause the power switching devices to malfunction, and then cause the system control effect to deteriorate, or even fail to work normally, which will eventually pose a threat to the reliable, safe and stable operation of the power electronic system.

(2) The PWM drive signal generated by high-frequency modulation has narrow pulses. In high-voltage and high-power applications, due to the relatively long response time of the switching process of the power device, when a very narrow drive pulse acts on the switching device, the conduction pole of the switching device will appear. The phenomenon of turning off immediately after a short period of time, or turning off immediately after it is not completely turned on, makes the ratio of the switching process time to the actual on-time time very large, thus resulting in a significant increase in switching loss, which in turn puts forward more requirements for the cooling system of power electronic devices. For high requirements, it may be necessary to replace the heat dissipation method, and the natural cooling may be changed to forced air cooling, or even forced air cooling may be changed to water cooling to meet the requirements, which will place higher requirements on the entire cooling system, and the system structure will be more complex.

The significance of solving the above problems and defects: eliminating abnormal pulses caused by high-frequency electromagnetic interference can ensure more reliable, safer and more stable operation of power electronic systems; automatically filter out narrow pulses in PWM signals and reduce the switching of high-power switching devices. loss, thereby reducing the requirements for the cooling system of the power electronic device.

SUMMARY OF THE INVENTION

Aiming at the problems existing in the prior art, the present invention provides an anti-interference method for driving signals of cascaded converters.

The present invention provides an anti-interference method for a PWM drive signal of a cascaded converter. The FPGA sends the PWM drive signal in a specific encoding form, and then the CPLD receives and decodes the encoded signal to obtain the PWM drive signal, which avoids the direct long line of the drive signal. The transmission is easily affected by high-frequency electromagnetic interference, and the anti-interference ability of the PWM drive signal is improved, thereby ensuring the reliable, safe and stable operation of the power electronic system; at the same time, this method can automatically filter out the PWM narrow pulse signal generated by high-frequency modulation, reduce Switching losses of high power switching devices.

Further, FIG. 2 is a system block diagram. In order to improve the anti-interference ability in the process of PWM drive signal transmission, the encoding method of FIG. 3 and the decoding method corresponding to FIG. 4 are adopted.

Further, the coding method of PWM drive signal anti-jamming in accompanying drawing 3, concrete execution steps are as follows:

Step S1, the FPGA in the main controller sends the initial code v ₁ v ₂ v ₃ "011" of the PWM encoded signal bit by bit according to the set baud rate;

Step S2, after the start code is sent, immediately read in the PWM signal level value generated by the internal carrier modulation of the FPGA, if the level value is "1", the signal code v ₄ v ₅ v ₆ takes "101", if the power If the average value is "0", then the signal code v ₄ v ₅ v ₆ takes "010", and at the same time adds a stop code v ₇ at the end of the encoding, and always takes "1";

Step S3, continue to send the codes v ₄ v ₅ v ₆ v ₇ generated in step S2 bit by bit according to the baud rate of step S1;

Further, the decoding method of PWM drive signal anti-jamming in accompanying drawing 4, concrete execution steps are as follows:

In step S1, the CPLD in the IGBT driver samples the input PWM coded signal in real time according to the baud rate of step S1 of claim 3, and the CPLD receives and compares the starting code v ₁ v ₂ v ₃ bit by bit. If the bit by bit comparison is exactly the same, continue Receive subsequent codes; otherwise, end the current round of sampling immediately, while the current output drive signal level of the CPLD remains unchanged;

Step S2, if the start codes are exactly the same bit-by-bit comparison, continue to receive the subsequent four-bit codes v ₄ v ₅ v ₆ v ₇ , and do not need to consider the specific logic level values of the four-bit codes in this process;

Step S3, after receiving the subsequent four-bit codes, immediately compare the last code _v7 with "1", and if they are the same, then decode the drive signal; remain unchanged;

Step S4, if the stop codes are the same, then judge the codes v ₄ v ₅ v ₆ , if the value is "101", the CPLD output drive signal is a high level "1", if the value is "010", then the CPLD The output drive signal is a low level "0", otherwise, the drive signal level output by the CPLD remains unchanged.

Further, the PWM drive signal can be prevented from being affected by high-frequency electromagnetic interference generated by the power switching device after being transmitted through a long line, and the anti-interference ability of the PWM drive signal can be improved, thereby ensuring the reliable, safe and stable operation of the power electronic system.

Further, as long as the PWM narrow pulse signal generated by high-frequency modulation does not appear at the time of reading the level value of the PWM signal after the start code is sent, the anti-interference coding method of the PWM drive signal in Figure 3 can automatically filter out the PWM signal. Narrow pulse, reducing switching loss of high-power switching devices.

Another object of the present invention is to provide a computer device, the computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the following steps :

The FPGA encodes the PWM drive signal generated by the internal carrier, adds a start code and a stop code to the code, and sends it at a certain baud rate;

CPLD receives the encoded signal and compares and decodes one by one;

When the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level remains unchanged.

Another object of the present invention is to provide a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, causes the processor to perform the following steps:

The FPGA encodes the PWM drive signal generated by the internal carrier, adds a start code and a stop code to the code, and sends it at a certain baud rate;

CPLD receives the encoded signal and compares and decodes one by one;

When the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level remains unchanged.

The method of the invention has wide applicability, and is not only suitable for cascaded multi-level power electronic systems, but also for other types of multi-level converter control systems, such as diode clamping five-level, seven-level or higher level circuit, and MMC.

Combined with all the above-mentioned technical solutions, the advantages and positive effects possessed by the present invention are:

The present invention encodes the PWM drive signal generated by the internal carrier through the FPGA. In order to ensure the reliability of the transmission encoding, a start code and a stop code are added to the encoding and sent according to a certain baud rate; the CPLD receives the encoded signal and compares them one by one. Decoding, only when the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level remains unchanged . The method can avoid the direct long-line transmission of the PWM drive signal and be affected by the high-frequency electromagnetic interference generated during the switching process of the power device, and improve the anti-interference ability of the PWM drive signal in the long-line transmission; at the same time, the method can automatically filter out the high-frequency modulation The PWM narrow pulse signal can reduce the switching loss of high-power switching devices.

The FPGA of the present invention does not directly output the PWM drive signal, but sends it in a specific encoding form, and the CPLD receives and decodes the encoded signal to obtain the PWM drive signal, which avoids the direct long-line transmission of the PWM drive signal being susceptible to high-frequency electromagnetic interference. The anti-interference ability of the PWM drive signal is improved, thereby ensuring the reliable, safe and stable operation of the power electronic system; at the same time, the method can automatically filter out the PWM narrow pulse signal generated by high-frequency modulation and reduce the switching loss of high-power switching devices.

Description of drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following will briefly introduce the drawings that need to be used in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a flowchart of an anti-interference method for a driving signal of a cascaded converter according to an embodiment of the present invention.

2 is a structural block diagram of a cascaded five-level converter control system provided by an embodiment of the present invention;

FIG. 3 is a flowchart of an anti-interference encoding method for a PWM drive signal of a cascaded converter according to Embodiment 1 of the present invention.

FIG. 4 is a flowchart of the method for decoding anti-interference of PWM drive signals of cascaded converters according to Embodiment 1 of the present invention.

5(a)-(e) are schematic diagrams when the anti-interference method for the PWM drive signal of the cascaded converter according to Embodiment 1 of the present invention works normally;

6(a)-(e) are schematic diagrams of processing when the initial encoding of the PWM encoded signal according to Embodiment 2 of the present invention is disturbed;

7(a)-(e) are schematic diagrams of processing when the PWM signal encoding is disturbed in the PWM encoded signal according to Embodiment 3 of the present invention.

8(a)-(e) are schematic diagrams of processing when the stop code in the PWM encoded signal is disturbed according to Embodiment 4 of the present invention.

9(a)-(d) are experimental waveforms when the anti-interference method for the PWM drive signal of the cascaded converter according to Embodiment 1 of the present invention works normally.

FIG. 10 is an experimental waveform of automatically filtering out the PWM narrow pulse signal by the anti-interference method for the PWM drive signal of the cascaded converter according to Embodiment 1 of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Aiming at the problems existing in the prior art, the present invention provides an anti-interference method for a driving signal of a cascaded converter. The present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , the present invention provides an anti-interference method for driving signals of cascaded converters, including:

S101, the PWM drive signal generated by the FPGA carrier modulation is encoded, and a start code and a stop code are added to the encoding, and sent according to a certain baud rate.

S102, the CPLD receives the encoded signals and compares and decodes them one by one.

S103, when the received start code, PWM signal code and stop code are all correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the level state of the output PWM drive signal remains unchanged.

A person skilled in the art of the anti-interference method for a driving signal of a cascaded converter provided by the present invention may also implement other steps. FIG. 1 is only a specific embodiment provided by the present invention.

The present invention will be further described below in conjunction with specific embodiments.

Example 1

The embodiment of the present invention provides an anti-interference method for a PWM drive signal of a cascaded converter. Taking the cascaded five-level converter as an example, the system structure diagram of the cascaded five-level converter is shown in Figure 2. The system mainly includes a main controller, an interface and sampling circuit, an IGBT driver and a H Bridge power unit, where the power unit has three phases A, B and C. Each phase is composed of two H bridges in series, and the cascaded five-level converter has a total of twenty-four IGBTs, requiring twenty-four PWM drive signals; in order to meet the multi-channel PWM drive signals required by the system, while taking into account For the modular design requirements of the cascaded five-level converter, the three processors of DSP, FPGA and CPLD in Figure 2 are used. Signal conditioning in Figure 2 indicates that the sampled current and voltage signals are processed to meet the DSP input requirements. It should be noted that since the generation methods of the PWM drive signals of the three-phase circuits of A, B and C are completely the same, only phase A is used as an example in FIG. 2 .

The DSP generates the A-phase reference voltage signal according to the control command, the sampled current and voltage signals and the controlled object model. The signal is transmitted to the FPGA to complete the modulation, and generates the required two groups of 0°, 180° and 90° and 270°. Four-way phase-shifted PWM signals, of which the 0° and 180° groups are sent to the A-phase H-bridge 1, and the 0° PWM signal is the drive signal of the left bridge arm, and the 180° PWM signal is the drive signal of the right bridge arm; 90° and 270° The group is sent to the A-phase H-bridge 2, and the 90° PWM signal is the drive signal of the left bridge arm, and the 270° PWM signal is the drive signal of the right bridge arm;

In order to provide the four PWM signals required by each H bridge, the CPLD in the IGBT driver needs to generate the complementary upper and lower bridge arms according to the input two PWM drive signals (0° and 180° or 90° and 270°), and Four-way drive signal with dead zone, namely CPLD generates two PWM signals with a certain dead zone time from 0° (or 90°) PWM signal to drive T ₁ and T ₂ of A-phase H bridge 1 (or 2) respectively; The 180° (or 270°) PWM signal generates two PWM signals with a certain dead time to drive T ₃ and T ₄ of the A-phase H-bridge 1 (or 2) respectively.

FIG. 3 is a flow chart of the method for anti-jamming coding of the PWM drive signal of the cascaded converters, and FIG. 4 is a flow chart of the method for anti-jamming decoding of the PWM drive signal of the cascaded converters.

Specifically include the following steps:

Step S1, the FPGA in the main controller sends the initial code v ₁ v ₂ v ₃ "011" of the PWM encoded signal bit by bit according to the set baud rate;

Step S2, after the start code is sent, immediately read in the PWM signal level value generated by the internal carrier modulation of the FPGA, if the level value is "1", the signal code v ₄ v ₅ v ₆ takes "101", if the power If the average value is "0", then the signal code v ₄ v ₅ v ₆ takes "010", and at the same time adds a stop code v ₇ at the end of the encoding, and always takes "1";

Step S3, continue to send the codes v ₄ v ₅ v ₆ v ₇ generated in step S2 bit by bit according to the baud rate of step S1;

In step S4, the CPLD in the IGBT driver samples the input PWM encoded signal in real time according to the baud rate in step S1, and the CPLD receives the comparison start code v ₁ v ₂ v ₃ bit by bit, if the bit-by-bit comparison is exactly the same, continue to receive subsequent codes , otherwise the current round of sampling ends immediately, and the current level of the drive signal output by the CPLD remains unchanged;

Step S5, if the start codes are exactly the same bit-by-bit comparison, continue to receive the subsequent four-bit codes v ₄ v ₅ v ₆ v ₇ , and do not need to consider the specific logic level values of the four-bit codes in this process;

Step S6, after receiving the subsequent four-bit codes, immediately compare the last code _v7 with "1", if the same, then decode the drive signal; otherwise, end the current round of sampling immediately, and the drive signal output by the CPLD The flat state remains unchanged;

Step S7, if the stop codes are the same, then judge the codes v ₄ v ₅ v ₆ , if the value is "101", the CPLD output drive signal is a high level "1", if the value is "010", then the CPLD The output drive signal is low level "0"; otherwise, the level state of the drive signal output by the CPLD remains unchanged;

5(a)-(e) are schematic diagrams of waveforms when the anti-interference encoding and decoding method of the PWM drive signal of the cascaded converter works normally. Figure 5 (c) is the PWM encoded signal output by the FPGA, and Figure 5 (d) is the PWM encoded signal received by the CPLD. Since the start code, PWM signal encoding and stop code are all correct, the decoded signal in Figure 5(e), v ₄ v ₅ v ₆ before time t ₁ is encoded as "101", so the time t ₁ in Figure 5 (e) Output high level; before time _t2 , v ₄ v ₅ v ₆ is coded as "010", so in Figure 5(e), output low level at time t ₂ .

Example 2

The embodiment of the present invention is a processing mechanism when the initial coding of the PWM coding signal is disturbed, and the cascaded five-level converter is also taken as an example. Figures 6(a)-(e) are schematic diagrams of waveforms when the initial coding of the PWM encoded signal is disturbed. Due to high-frequency electromagnetic interference, the PWM encoded signal output by the FPGA in Figure 6(c) becomes the one shown in Figure 6(d). The waveform, that is, the initial code received by the CPLD, is in error. In _Fig . 6(e), the start code v1 sampled by the CPLD before time _t1 is wrong, so the output PWM drive signal remains at high level at time _t1 , and the current round of sampling ends immediately; in Fig. 6(e), _t2 The start code v ₂ sampled by the CPLD before time is wrong, so the output PWM drive signal at time t ₂ remains low, and the current round of sampling ends immediately.

Example 3

The embodiment of the present invention is a processing mechanism when the PWM signal code in the PWM code signal is disturbed, and the cascaded five-level converter is also taken as an example. Figures 7(a)-(e) are schematic diagrams of waveforms when the PWM signal encoding in the PWM encoded signal is disturbed. Due to the high-frequency electromagnetic interference, the PWM encoded signal output by the FPGA in Figure 7(c) becomes the one shown in Figure 7(d). The displayed waveform, that is, the signal code v ₄ v ₅ v ₆ received by the CPLD is wrong. In Fig. 7(e), the signal code _v6 sampled by the CPLD before time _t1 is wrong, so the output PWM drive signal is kept at a high level at time _t1 , and the current round of sampling ends; in Fig. 7(e), before time _t2 The signal code _v5 sampled by CPLD is wrong, so the output PWM drive signal is kept at low level at time _t2 , and the current round of sampling is ended.

Example 4

The embodiment of the present invention is a processing mechanism when a stop code in a PWM encoded signal is disturbed, and a cascaded five-level converter is also taken as an example. Figures 8(a)-(e) are schematic diagrams of waveforms when the stop code of the PWM encoded signal is disturbed. Due to high-frequency electromagnetic interference, the stop code output by the FPGA in Figure 8(c) becomes the waveform shown in Figure 8(d). That is, the stop code _v7 received by the CPLD becomes "0". In Figure 8(e), the stop code _v7 sampled by the CPLD before time _t1 is wrong, so the output PWM drive signal remains at high level at time _t1 , and the current round of sampling ends immediately.

The present invention will be further described below in conjunction with the effects.

The invention discloses an anti-interference method for a PWM drive signal of a cascaded converter. The FPGA does not directly output the PWM drive signal generated by the internal carrier modulation, but encodes the drive signal in a specific form. The encoding includes the start code, PWM signal encoding and stop code, and then the FPGA sends it according to the set baud rate. , and the encoded signal is received and decoded by the CPLD. Only when the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level state remains unchanged.

The technical scheme of the present invention adopts the encoding method to transmit the PWM driving signal, avoids the direct long-line transmission of the PWM driving signal being easily affected by high-frequency electromagnetic interference, improves the anti-interference ability of the PWM driving signal, and thus ensures the reliability and safety of the power electronic system At the same time, the technical scheme of the present invention can also automatically filter out the PWM narrow pulse signal generated by the high-frequency modulation, thereby reducing the switching loss of the high-power switching device. The scheme is simple, only implemented by software, and does not increase the cost of system hardware; the invention is not only suitable for cascaded multi-level power electronic systems, but also for other types of multi-level converter control systems, such as: diode-clamped five-level , seven-level or higher circuits, and MMC.

The present invention will be further described below in conjunction with specific experiments.

Figure 9(a)-(d) The experimental waveforms of the anti-interference coding and decoding method of the PWM drive signal of the cascaded converters when the method works normally; wherein, channel 3 is the PWM signal output by the FPGA carrier modulation, and channel 1 is the PWM output by the FPGA The signal corresponds to the encoded signal; channel 2 is the encoded signal received by the CPLD, and channel 4 is the PWM signal decoded and output by the CPLD.

In Figure 9(a), the PWM signal output by FPGA carrier modulation is low level, and the encoded signal received by CPLD is exactly the same as the encoded signal output by FPGA, so the PWM signal output by CPLD decoding corresponds to low level. Similarly, when the PWM signal output by the FPGA carrier modulation in Fig. 9(b) is at a high level, the conclusion is the same as that in Fig. 9(a).

In Figure 9(c), the PWM signal output by the FPGA carrier modulation changes from low level to high level. During the whole process, the encoded signal received by the CPLD is always the same as the encoded signal output by the FPGA. The PWM signal output by CPLD decoding also changes from low level to high level after a small delay. Similarly, when the PWM signal output by FPGA carrier modulation changes from high level to low level in Figure 9(d), the conclusion is the same as that in Figure 9(c).

10 is the experimental waveform of the PWM drive signal anti-interference method of the cascaded converter according to the embodiment of the present invention automatically filtering out the PWM narrow pulse signal; wherein, the channel 3 is the PWM signal output by the FPGA carrier modulation, and the channel 1 is the FPGA The output PWM signal corresponds to the encoded signal; channel 2 is the encoded signal received by the CPLD, and channel 4 is the PWM signal decoded and output by the CPLD. When the PWM signal generated by the high-frequency carrier modulation in the FPGA is a narrow pulse, as shown in Figure 10, the extremely narrow pulse is 320ns, and the narrow pulse generated by the high-frequency modulation does not appear at the time of reading the level value of the PWM signal after the start code is sent. , so that the PWM narrow pulse signal cannot be encoded, the encoded signal output by the FPGA and the encoded signal received by the CPLD are always encoded as low-level signals, so the PWM signal output by the CPLD decoding is low-level, realizing automatic filtering of PWM narrow pulses. function of the pulse signal.

In the description of the present invention, unless otherwise stated, "plurality" means two or more; the terms "upper", "lower", "left", "right", "inner", "outer" The orientation or positional relationship indicated by , "front end", "rear end", "head", "tail", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, not An indication or implication that the referred device or element must have a particular orientation, be constructed and operate in a particular orientation, is not to be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc. are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

It should be noted that the embodiments of the present invention may be implemented by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using special purpose logic; the software portion may be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer-executable instructions and/or embodied in processor control code, for example on a carrier medium such as a disk, CD or DVD-ROM, such as a read-only memory Such code is provided on a programmable memory (firmware) or a data carrier such as an optical or electronic signal carrier. The device and its modules of the present invention can be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., It can also be implemented by software executed by various types of processors, or by a combination of the above-mentioned hardware circuits and software, such as firmware.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art is within the technical scope disclosed by the present invention, and all within the spirit and principle of the present invention Any modifications, equivalent replacements and improvements made within the scope of the present invention should be included within the protection scope of the present invention.

Claims (7)

1. A method for anti-interference of the driving signal of a cascaded converter, wherein the method for anti-interference of the driving signal of the cascaded converter comprises: The FPGA encodes the PWM drive signal generated by the internal carrier modulation, adds a start code and a stop code to the code, and sends it continuously according to a certain baud rate; CPLD receives the encoded signal and compares and decodes one by one; When the received start code, PWM signal encoding and stop code are all correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output level of the PWM drive signal remains unchanged. 2. The anti-interference method for cascaded converter drive signals as claimed in claim 1, wherein the method for encoding the PWM drive signals generated by the internal carrier modulation by the FPGA comprises: S1. The FPGA in the main controller sends the start code v ₁ v ₂ v ₃ "011" of the PWM encoded signal bit by bit according to the set baud rate; S2. After the start code is sent, immediately read the level value of the PWM signal generated by the internal carrier modulation of the FPGA. If the level value is "1", the signal code v ₄ v ₅ v ₆ takes "101", if the level is "1" If the value is "0", the signal code v ₄ v ₅ v ₆ takes "010", and at the same time adds a stop code v ₇ at the end of the encoding, and always takes "1"; S3. Continue to send the codes v ₄ v ₅ v ₆ v ₇ generated in step S2 bit by bit according to the baud rate of step S1. 3. The anti-interference method for driving signals of cascaded converters as claimed in claim 1, wherein the method for receiving the encoded signal by the CPLD and comparing and decoding one by one comprises: Step 1. The CPLD in the IGBT driver samples the input PWM coded signal in real time according to the baud rate of step S1, and the CPLD receives the comparison start code v ₁ v ₂ v ₃ bit by bit. If the bit-by-bit comparison is exactly the same, continue to receive subsequent codes , otherwise the current round of sampling ends immediately, and the current output drive signal level of the CPLD remains unchanged; Step 2. If the start codes are exactly the same bit by bit, continue to receive the subsequent four-bit codes v ₄ v ₅ v ₆ v ₇ ; Step 3. After receiving the subsequent four-bit codes, compare the last code v ₇ with "1", and if they are the same, then decode the drive signal; otherwise, end the current round of sampling immediately, and at the same time the drive signal level output by the CPLD constant; Step 4. If the stop codes are the same, then judge the code v ₄ v ₅ v ₆ , if the value is "101", the CPLD output drive signal is a high level "1", if the value is "010", then the CPLD The output drive signal is a low level "0"; otherwise, the drive signal level output by the CPLD remains unchanged. 4. A computer device, characterized in that the computer device comprises a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor is caused to perform the following steps: The FPGA encodes the PWM drive signal generated by the internal carrier, adds a start code and a stop code to the code, and sends it at a certain baud rate; CPLD receives the encoded signal and compares and decodes one by one; When the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level remains unchanged. 5. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the following steps: The FPGA encodes the PWM drive signal generated by the internal carrier, adds a start code and a stop code to the code, and sends it at a certain baud rate; CPLD receives the encoded signal and compares and decodes one by one; When the received start code, PWM signal encoding and stop code are correct, the PWM drive signal output by the CPLD is updated to the currently received logic level; otherwise, the output PWM drive signal level remains unchanged. 6. A cascaded converter for implementing the anti-interference method for driving signals of cascaded converters according to any one of claims 1 to 3. 7. A diode-clamped five-level, seven-level or higher-level circuit and an MMC multi-level converter control system for implementing the anti-interference method for driving signals of cascaded converters according to any one of claims 1 to 3.

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