CN111900209A - A trench structure silicon carbide oxide field effect transistor and its preparation method - Google Patents

Abstract

The invention relates to a trench structure silicon carbide oxide field effect transistor and a preparation method thereof. The double-layer epitaxy process is adopted in a double trench gate MOSFET device to disperse the electric field strength of the gate insulating film, and the bottom of the trench A highly doped p+ type body layer is formed to protect the insulating film on the bottom surface of the gate region. In addition, the method of oxidizing the insulating layer with N2O gas at high temperature directly by LPCVD on the trench sidewalls reduces defects and fixes the thickness, thereby improving performance and producing highly reliable devices.

Description

A trench structure silicon carbide oxide field effect transistor and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a trench structure silicon carbide oxide field effect transistor and a preparation method thereof.

Background technique

Compared with the currently commonly used silicon power semiconductors, SiC power semiconductors have excellent material properties, so they are widely used in hybrid (HV) and electric vehicles (EV), consumer electronics and industrial inverters, solar inverters, intermittent In high-current switching devices such as power supplies (UPS), especially in the motor joint control device in the field of electric vehicles, high-frequency, low-noise, small and light inverters can be expected.

As shown in Figure 1, the conventional general conventional SiC channel MOSFET device firstly grows the active region n-type SiC layer 2' and p-type bulk SiC layer 4' on the n+-type SiC substrate 1', as a high concentration of doping, The source region 5' and the ground region 6' are sequentially formed to form the source electrode 7'. In addition, after the gate insulating film trench gate oxide (insulation) layer 9' is formed on the sidewall and the bottom surface of the trench gate region, the trench is filled with: n+ polycrystalline electrode 10', and then the drain electrode 14' is grown Structure and form gate 11'. There is a big problem in the reliability of this device structure, because the internal electric field is concentrated on the bottom surface of the trench, and the current density is high, which becomes a vulnerable area.

SUMMARY OF THE INVENTION

In view of the problems existing in the prior art, the purpose of the present invention is to provide a trench structure silicon carbide oxide field effect transistor and a preparation method thereof, which can solve the problem of easy damage caused by strong electric fields and improve the reliability of the field effect transistor.

For achieving the above object, the technical scheme adopted in the present invention is:

A trench-structured silicon carbide oxide field effect transistor is provided with an n+ type SiC substrate, an n- type SiC layer, an n-type SiC layer, and an insulating layer in sequence from bottom to top;

The lower end face of the n+ type SiC substrate is provided with a drain metal electrode;

A p+-type buried layer is provided at the position of the n-type SiC layer close to the n-type SiC layer;

A p-type epitaxial layer and a guard ring type junction are arranged on the n-type SiC layer, p+ grounding, n+ source and gate trenches are arranged on the p-type epitaxial layer, and a gate trench is arranged in the gate trench Bottom insulating layer, trench gate oxide insulating layer and n+ polycrystalline electrode;

A source metal electrode and a gate metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n+ polycrystalline electrode.

The insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.

A preparation method of a trench structure silicon carbide oxide field effect transistor, which comprises the following steps:

Step 1. Sequentially grow an n-type SiC epitaxial layer and an oxide film on the n+-type SiC substrate wafer, cover the oxide film with a layer of photoresist, and photoetch the position of the p+-type buried layer; Inject a high concentration of aluminum at the location;

Step 2. Remove the oxide film that was shielded in the previous step, then grow an n-type SiC epitaxial layer on the n-type SiC epitaxial layer, and then grow an oxide film on the n-type SiC epitaxial layer; then cover with a layer of photoresist, photoetch out Protect the area, and then inject aluminum dopant into the protected area at high temperature;

Step 3. Remove the shielded oxide film of the previous step, re-cover the oxide film and photoresist, photoetch out the defined position of the p-type epitaxial layer, and then inject aluminum dopant into the photoetched position at high temperature .

Step 4. After completing the previous step, continue to cover the photoresist, and then photoetch out the defined position of the n+ source, and inject N nitrogen dopant into the defined position of the n+ source at a high temperature;

Remove the oxide film shielded by the previous step, re-cover the oxide film and photoresist, photoetch out the defined position of p+ grounding, and then inject aluminum dopant into the defined position of p+ grounding;

Step 5. Remove the shielded oxide film of the previous step, re-cover with a layer of photoresist, activate the impurities doped in steps 1-4, and form a p+ type buried layer, a guard ring type junction, a p type epitaxial layer, an n+ type The source and p+ are grounded, and the photoresist is graphitized to form a graphite layer;

Step 6, remove the graphite layer of the previous step, then grow the first oxide film, polysilicon, and second oxide film in turn by CVD method, and then etch out the U-shaped gate trench of the gate region; in the U-shaped gate trench An oxide layer is coated in the groove and thermal hardening is performed to form an oxide film at the bottom of the groove, and its thickness is maintained at 0.5μm-1μm;

Step 7. Grow a 50-100nm trench gate oxide insulating layer in the U-shaped gate trench by gas growth, and then pass a mixed gas of N2O and N2 at high temperature to make the original defect of the SiC/SiO2 contact surface mouth, through which mixed nitrogen gas is formed to form a nitride film; then, the nitride film on the surface is washed off with phosphoric acid, and the polysilicon and the second oxide film are removed; n+ polycrystalline electrode is grown on the U-shaped gate trench;

Step 8. Grow a BPSG film on the first oxide film, and then pass nitrogen gas under an atmospheric pressure of 900° C. to form an ILD insulating layer, and then cover the ILD insulating layer with photoresist protection;

Alternately stack oxide films and polysilicon on the lower surface of the n+-type SiC substrate wafer to the desired thickness; then polish and plated with nickel metal, and then perform RTP process at 1000°C under an argon atmosphere under atmospheric pressure to form Ohmic contact;

Step 9. Define the position of the upper source metal electrode on the IDL insulating layer, and etch out the source region; alternately stack the oxide film and polysilicon to the required thickness, plated with nickel metal, and then at 1000 ℃, atmospheric pressure Under the argon atmosphere, the RTP process is performed to form an ohmic contact;

Step 10, cleaning the upper surface of the ILD insulating layer, and plating a thick film of TiW/AlSi alloy; and then photoetching the required gate metal electrode and source metal electrode;

At 450°C and atmospheric pressure, the lower surface of the n+-type SiC substrate is cleaned, and the Ti/Ag film is plated with electron beams to form the drain metal electrode, and then heat treatment is performed to complete the metal electrode arrangement.

After adopting the above scheme, the present invention adopts the double-layer epitaxy process in the double trench gate MOSFET device to disperse the electrical field strength of the gate insulating film, and form a high-concentration doped p+ type body layer at the bottom of the trench to protect the gate region insulating film on the bottom surface. In addition, the method of oxidizing the insulating layer with N2O gas at high temperature directly by LPCVD on the trench sidewalls reduces defects and fixes the thickness, thereby improving performance and producing highly reliable devices.

Description of drawings

1 is a schematic structural diagram of a field effect transistor in the prior art;

2 is a schematic structural diagram of a field effect transistor of the present invention;

FIG. 3-FIG. 10 are the flow charts of the fabrication of the field effect transistor of the present invention.

Detailed ways

As shown in FIG. 2, the present invention discloses a trench structure silicon carbide oxide field effect transistor, which is provided with an n+ type SiC substrate 1, an n- type SiC layer 2, an n type SiC layer 3, and Insulation;

The lower end surface of the n+ type SiC substrate 1 is provided with a drain metal electrode 14;

The n-type SiC layer 2 is provided with a p+-type buried layer 15 at a position close to the n-type SiC layer 3;

The n-type SiC layer 3 is provided with a p-type epitaxial layer 4 and a guard ring type junction 13, and a p+ ground 6, an n+ source 5 and a gate trench 8 are provided on the p-type epitaxial layer 4. A gate bottom insulating layer 12, a trench gate oxide insulating layer 9 and an n+ polycrystalline electrode 10 are arranged in the pole trench 8;

A source metal electrode 7 and a gate metal electrode 11 are provided on the insulating layer, and the source metal electrode 7 is in contact with the n+ polycrystalline electrode 10 .

As shown in FIG. 3 to FIG. 10 , the present invention also discloses a method for preparing a trench structure silicon carbide oxide field effect transistor, which includes the following steps:

Step 1. Grow an n-type SiC layer 2 on an n+-type SiC substrate 1, and then deposit an oxide film by CVD (chemical deposition) method to cover the n-type SiC layer 2; then cover a layer of photoresist, photolithography The position of the p+-type buried layer 15 is removed, and 5um of SiC is etched; finally, a high concentration of aluminum (Al) is implanted into the photoetched position at a temperature of 600°C.

Step 2, remove the oxide film shielded in the previous step, then grow an n-type SiC layer 3 on the n-type SiC layer 2 by a CVD method at a high temperature, and then use the CVD method again to grow an oxide film on the n-type SiC layer 3; then A layer of photoresist is covered, a protection area is photoetched, and aluminum dopant is injected into the protection area at a high temperature.

Step 3. After removing the shielded oxide film in the previous step, cover the oxide film and photoresist again, photoetch out the defined position of the p-type epitaxial layer 4, and then inject it into the photoetched position at a temperature of 600°C. Aluminum dopant.

Step 4: After the previous step is completed, the photoresist is covered again, and then the defined position of the n+ source 5 is photo-etched, and N nitrogen dopant is implanted into the defined position of the n+ source 5 at a temperature of 600°C. Remove the oxide film shielded in the previous step, re-cover the oxide film and photoresist, photoetch out the defined position of p+ ground 6, and then inject aluminum dopant into the defined position of p+ ground 6 at a temperature of 600°C.

Step 5. Remove the shielded oxide film of the previous step, re-cover with a layer of photoresist, and heat at 1600-1700 ° C for 30 minutes to 1 hour to activate the impurities doped in steps 1-4 to form a p+-type buried layer 15. The guard ring junction 13 (at the guard area), the p-type epitaxial layer 4 , the n+ source 5 and the p+ ground 6 . At high temperatures, the photoresist will graphitize (burn); the graphite that coats the surface prevents sublimation of the silicon carbide on the surface.

Step 6. After removing the graphite layer in the previous step by using O2 plasma and oxidation reaction, the oxide film, polysilicon and oxide film are formed in turn by CVD method, the position of the trench gate region is defined, and the photolithography of this position is further removed by wet etching. Then, the trench 8 in the gate region is etched to a level of 1.5 to 2.0um, and the U-shaped trench 8 is etched and sacrificial oxidation. The oxide layer is further coated with LPCVD (Low Pressure Chemical Vapor Deposition), and then thermally hardened at 1100°C under atmospheric pressure with nitrogen (N2), the oxide film at the bottom of the trench (that is, the bottom of the gate) The thickness of the insulating layer 12) is kept at 500nm-1μm.

Step 7. Grow a 50-100nm trench gate oxide insulating layer 9 on the U-shaped gate trench 8 by gas growth, and then pass a mixture of N2O (10%) and N2 at 1250°C, so that the original SiC/ The defect port of the SiO2 interface, through which mixed nitrogen gas passes to form oxynitride, which ensures that the interface defect (Dit) is less than 5x10 ¹¹ . After the nitride film on the surface is washed with phosphoric acid, CMP (chemical mechanical polishing) and RIE (reactive ion etching) are performed to remove the oxide film on the surface; the n+ polycrystalline electrode 10 is grown.

Step 8, using LPCVD and HTO (High Temperature Oxidation, high temperature oxidation) to grow a BPSG film, and then passing nitrogen (N2) under an atmospheric pressure of 900° C. to grow an ILD insulating layer. Then, the ILD insulating layer is covered with photoresist protection; the oxide film and polysilicon are alternately stacked on the lower surface of the n+-type SiC substrate 1 to the required thickness; then polished by CMP, plated with nickel metal, and then heated at 1000°C under atmospheric pressure argon Under the atmosphere, a 3-minute RTP (rapid thermal treatment) process was performed to form an ohmic contact.

Step 9. Define the position of the upper source metal electrode 7, and dry and wet etch the source region of the ILD insulating layer. The oxide film and polysilicon are alternately stacked to the desired thickness, nickel metal is plated, and then an RTP (rapid heat treatment) process is performed at 1000°C under an atmospheric pressure argon atmosphere for 3 minutes to form an ohmic contact.

Step 10, cleaning the upper surface with hydrofluoric acid, and plating a thick film of TiW/AlSi alloy; At 450°C and atmospheric pressure through H2/N2, the lower surface of the n+-type SiC substrate 1 is cleaned with hydrofluoric acid, and a Ti/Ag film is plated with electron beams to form the drain metal electrode 14, and then heat treatment is performed to complete the metal electrode arrangement.

The present invention adopts the double-layer epitaxy process in the double trench gate MOSFET device, disperses the electric field strength of the gate insulating film, and forms a high-concentration doped p+ type body layer at the bottom of the trench to protect the insulation on the bottom surface of the gate region. membrane. In addition, the method of oxidizing the insulating layer with N2O gas at high temperature directly by LPCVD on the trench sidewalls reduces defects and fixes the thickness, thereby improving performance and producing highly reliable devices.

The above are only the embodiments of the present invention and do not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still belong to the present invention. within the scope of the technical solution.

Claims (3)

1. A silicon carbide oxide field effect transistor with a groove structure is characterized in that: an n + type SiC substrate, an n-type SiC layer and an insulating layer are sequentially arranged from bottom to top;

a drain electrode metal electrode is arranged on the lower end face of the n + type SiC substrate;

a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer;

the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove;

and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode.

2. The silicon carbide oxide field effect transistor with a trench structure of claim 1, wherein: the insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.

3. A preparation method of a silicon carbide oxide field effect transistor with a groove structure is characterized by comprising the following steps: the method comprises the following steps:

step 1, sequentially growing an n-type SiC epitaxial layer and an oxide film on an n + type SiC substrate wafer, covering a layer of photoresist on the oxide film, and photoetching the position of a p + type buried layer; injecting high-concentration aluminum into the photoetching position at high temperature;

step 2, removing the oxide film shielded in the previous step, growing an n-type SiC epitaxial layer on the n-type SiC epitaxial layer, and growing an oxide film on the n-type SiC epitaxial layer; covering a layer of photoresist, photoetching a protection region, and injecting aluminum doping substances into the protection region at high temperature;

step 3, removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p-type body epitaxial layer, and injecting aluminum dopant into the photoetching position at high temperature;

step 4, after the previous step is completed, continuing covering the photoresist, photoetching the defined position of the N + source, and injecting N-nitrogen doping substances into the defined position of the N + source at high temperature;

removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching a p + grounding defined position, and injecting aluminum dopant into the p + grounding defined position;

step 5, removing the oxide film shielded in the previous step, covering a layer of photoresist again, activating the impurities doped in the steps 1-4 to form a p + type buried layer, a protective ring type junction, a p type epitaxial layer, an n + source and a p + grounding layer, and graphitizing the photoresist to form a graphite layer;

step 6, removing the graphite layer in the previous step, then sequentially generating a first oxide film, polycrystalline silicon and a second oxide film by a CVD method, and etching a U-shaped grid groove of a grid region; coating an oxide layer in the U-shaped grid groove and carrying out a thermal hardening treatment, thereby forming an oxide film at the bottom of the groove, wherein the thickness of the oxide film is kept between 0.5 and 1 mu m;

step 7, growing a 50-100nm groove gate oxide insulating layer in the U-shaped gate groove by adopting a gas growth mode, and then introducing mixed gas of N2O and N2 at high temperature to enable the defect opening of the SiC/SiO2 contact surface to exist originally, and forming a nitride film by mixed nitrogen gas; then, cleaning the nitride film on the surface by phosphoric acid, and removing the polysilicon and the second oxide film; growing n + polycrystalline state electrodes on the U-shaped grid grooves;

step 8, growing a BPSG film on the first oxide film, introducing nitrogen at the atmospheric pressure of 900 ℃ to form an ILD insulating layer, and covering the ILD insulating layer with photoresist for protection;

alternately stacking an oxide film and polycrystalline silicon on the lower surface of the n + type SiC substrate wafer to a required thickness; polishing and plating nickel metal, and then performing RTP process treatment at 1000 ℃ under the argon atmosphere under the atmospheric pressure to form ohmic contact;

step 9, defining the position of an upper source electrode metal electrode on the IDL insulating layer, and etching a source region; sequentially and alternately stacking the oxide film and the polycrystalline silicon to the required thickness, plating nickel metal, and then carrying out RTP (real time processing) process treatment at 1000 ℃ under the atmosphere of atmospheric pressure argon to form ohmic contact;

step 10, cleaning the upper surface of the ILD insulating layer, and plating a TiW/AlSi alloy thick film; photoetching a needed grid metal electrode and a needed source metal electrode;

and (3) introducing H2/N2 at the atmospheric pressure at 450 ℃, cleaning the lower surface of the N + type SiC substrate, plating a Ti/Ag film by using electron beams to form a drain metal electrode, and then carrying out heat treatment to complete the arrangement of the metal electrode.

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