CN111900156B

CN111900156B - High current, low switching loss SiC power module

Info

Publication number: CN111900156B
Application number: CN202010857239.6A
Authority: CN
Inventors: 姆里纳尔·K·达斯; 亨利·林; 马塞洛·舒普巴赫; 约翰·威廉斯·帕尔穆尔
Original assignee: Wofu Semiconductor Co ltd
Current assignee: Wofu Semiconductor Co ltd
Priority date: 2014-05-15
Filing date: 2015-05-14
Publication date: 2025-02-14
Anticipated expiration: 2035-05-14
Also published as: CN111900156A; CN106537586B; JP7000022B2; WO2015175820A1; DE112015002272B4; DE112015002272T5; JP2020098921A; CN106537586A; JP2017516312A; JP7056836B2

Abstract

The invention discloses a high-current and low-switching-loss SiC power module. A power module includes a housing having an interior chamber and a plurality of switching modules mounted within the interior chamber of the housing. The switching modules are interconnected and configured to facilitate switching power to a load. Each of the switching modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed of a wide bandgap material system, such as silicon carbide (SiC), allowing the power module to operate at high frequencies and with lower switching losses when compared to conventional power modules.

Description

High-current low-switching-loss SiC power module

The application relates to a divisional application, the application number of the main application is 2015800376807, the application date is 5-month 14 in 2015, and the application is named as a high-current and low-switching-loss SiC power module.

RELATED APPLICATIONS

The present application is a partial continuation-in-process of U.S. patent application Ser. No. 13/893,998, filed 5/14/2013, which is a partial continuation-in-process of U.S. patent application Ser. No. 13/588,329, filed 8/17/2012, which claims the benefit of U.S. provisional patent application Ser. No. 61/533,254, filed 11/9/2011, the entire disclosure of which is incorporated herein by reference.

Technical Field

The present disclosure relates to a power module for controlling power delivery to a load.

Background

As power costs continue to grow and environmental impact problems grow, the demand for power devices with improved performance and efficiency continues to grow. One way to provide the performance and efficiency of power devices is by using silicon carbide (SiC) to fabricate the device. Power devices made of silicon carbide (SiC) are expected to exhibit great advantages in switching speed, power handling capability, and temperature handling capability over conventional silicon power devices. In particular, the high critical field and wide bandgap of SiC devices allow for an increase in both performance and efficiency when compared to conventional silicon devices.

Due to performance limitations inherent in silicon, conventional power devices may require bipolar structures, such as Insulated Gate Bipolar Transistors (IGBTs), when blocking high voltages (e.g., voltages greater than 5 kV). While utilizing a bipolar structure substantially reduces the resistance of the drift layer due to its conductivity modulation, bipolar structures also suffer from relatively slow switching times. As will be clear to those skilled in the art, the reverse recovery time of the bipolar structure (due to the relatively slow diffusion of minority carriers) limits its maximum switching time, making silicon devices generally unsuitable for high voltage and high frequency applications.

Due to the performance enhancements described above with respect to SiC power devices, unipolar SiC power devices may be used to block voltages up to 10kV or greater. The majority carrier nature of such unipolar SiC power devices effectively eliminates the reverse recovery time of the device, allowing very high switching speeds (e.g., less than 100ns for double Diffused Metal Oxide Semiconductor Field Effect Transistors (DMOSFET) having 10kV blocking capability and a specific on-resistance of about 100mΩ cm ²).

Power devices are often interconnected and integrated into power modules that operate to dynamically switch large amounts of power through various components such as motors, converters, generators, and the like. As discussed above, due to the continuing growth of power costs and environmental impact issues, there is a continuing need for smaller, cheaper to manufacture, and more efficient power modules that provide similar or better performance than their conventional counterparts.

Disclosure of Invention

The present disclosure relates to a power module for controlling power delivery to a load. According to one embodiment, a power module includes a housing having an interior chamber and a plurality of switching modules mounted within the interior chamber of the housing. The switching modules are interconnected and configured to facilitate switching power (power) to a load. Each of the switching modules includes at least one transistor and at least one diode. At the same time, the switching module is capable of blocking 1200 volts, conducting 300 amps and having a switching loss of less than 20 millijoules. By including the switching module in the power module such that the power module has a switching loss of less than 20 millijoules for a 1200V/300A rating, the performance of the power module is significantly improved when compared to conventional power modules.

According to one embodiment, a power module includes a housing having an interior chamber, at least one power substrate (power substrate) within the interior chamber, and a gate connector. The power substrate includes a switching module on a first surface of the power substrate for facilitating switching power to a load. The switching module includes at least one transistor and at least one diode. The gate connector is coupled to the gate contact of the at least one transistor via a signal path that includes a first conductive trace on the first surface of the power substrate. Connecting the gate connector to the gate of the at least one transistor using a conductive trace on the first surface of the power substrate reduces interference in the power module and increases connection reliability between the gate connector and the gate contact of the at least one transistor.

According to one embodiment, a power module includes a housing having an interior chamber, a pair of output contacts (contacts), and a plurality of switching modules. A plurality of switching modules are mounted within the interior chamber of the housing and are interconnected to facilitate switching power from a power source coupled between the output contacts to the load. The pair of output contacts are arranged such that an area of at least 150mm ² of each of the output contacts is located less than 1.5mm from the other output contact. Providing an area of each output contact of at least 150mm ² less than 1.5mm from another output contact reduces leakage inductance between the output contacts, thereby increasing performance of the power module.

The scope of the present disclosure and the realization of additional aspects thereof will be apparent to those skilled in the art from a reading of the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Drawings

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate various aspects of the present disclosure along with a description to explain the principles of the disclosure.

Fig. 1 is a schematic diagram illustrating details of a power module according to one embodiment of the present disclosure.

Fig. 2 is a graph showing various signals generated by the power module shown in fig. 1.

Fig. 3 is a schematic diagram showing details of a switching module in the power module shown in fig. 1.

Fig. 4 is a block diagram illustrating details of the power module shown in fig. 1 according to one embodiment of the present disclosure.

Fig. 5 is a plan view illustrating details of the power module shown in fig. 1 according to one embodiment of the present disclosure.

Fig. 6 is a plan view illustrating additional details of the power module shown in fig. 1 according to one embodiment of the present disclosure.

Fig. 7 is a plan view illustrating an outer case of the power module shown in fig. 1 according to one embodiment of the present disclosure.

Fig. 8 is a plan view illustrating an outer housing detail of the power module shown in fig. 1 according to one embodiment of the present disclosure.

Fig. 9 is a block diagram illustrating details of a power substrate in the power module shown in fig. 4 according to one embodiment of the present disclosure.

Detailed Description

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending" directly onto "another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extend directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending" directly over "another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates an exemplary power module 10 according to one embodiment of the present disclosure. The power module 10 comprises two switching modules SM1 and SM2 controlled by a control system 12 to deliver power from a power source (dc+/DC-) to a load 14 in a controlled manner. As will be appreciated by those skilled in the art, the switching modules SM1 and SM2 form a half-bridge, the details of which are discussed below. Each of the switching modules SM1 and SM2 comprises at least a first transistor in anti-parallel with a first diode. Specifically, the first switching module SM1 includes a first transistor Q1 in antiparallel with a first diode D1, and the second switching module SM2 includes a second transistor Q2 in antiparallel with a second diode D2. In one embodiment, the first transistor Q1 and the second transistor Q2 are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). However, it will be apparent to those skilled in the art that any suitable switching device, such as, for example, insulated Gate Bipolar Transistors (IGBTs), field Effect Transistors (FETs), junction Field Effect Transistors (JFETs), high Electron Mobility Transistors (HEMTs), etc., may be used in the switching modules SM1 and SM2 without departing from the principles of the present disclosure. The first diode D1 and the second diode D2 may be schottky diodes, and in particular junction barrier schottky diodes. Again, it will be apparent to those skilled in the art that any suitable diode device, such as P-N diodes and PiN diodes, may be used for the switching modules SM1 and SM2 without departing from the principles of the present disclosure. In one embodiment, the second diode D1 and the second diode D2 are omitted and their functions are replaced by internal body diodes (internal body diode) of the first transistor Q1 and the second transistor Q2, respectively. The use of the internal body diodes of the first and second transistors Q1 and Q2 in place of the first and second diodes D1 and D2 may save space and cost in the power module 10.

The gate contact G of the first transistor Q1 and the source contact S of the first transistor Q1 are coupled to the control system 12. Similarly, the gate contact G and the source contact S of the second transistor Q2 are also coupled to the control system 12. Notably, the connection from the gate contacts G of the first transistor Q1 and the second transistor Q2 to the control system 12 can be achieved via relatively low power gate connectors G1 and G2, respectively. Similarly, the connection from the source contacts S of the first and second transistors Q1 and Q2 to the control system 12 may be implemented via low power return connections (low-power source return connection) S1 and S2 for measuring one or more operating parameters of the first and second transistors Q1 and Q2, respectively. The drain contact D of the first transistor Q1 is coupled to the positive power supply terminal dc+. The drain contact D of the second transistor Q2 is coupled to the output terminal OUT. The source contact S of the first transistor Q1 is also coupled to the output terminal OUT. The source contact S of the second transistor Q2 is coupled to the negative supply terminal DC-. Finally, a load 14 is coupled between the output terminal OUT and the negative DC power supply terminal DC-.

The first transistor Q1, the first diode D1, the second transistor Q2, and the second diode D2 may each be a majority carrier device. Most carrier devices generally include FETs such as MOSFET, HEMT, JFET and the like, but do not include thyristors, bipolar transistors, and Insulated Gate Bipolar Transistors (IGBTs). Thus, the power module 10 may be capable of operating at high switching speeds and suffer from lower switching losses when compared to conventional power modules employing bipolar devices. In one embodiment, the first transistor Q1, the first diode D1, the second transistor Q2, and the second diode D2 are wide band-gap devices (wide band-GAP DEVICE). For purposes of this disclosure, wide bandgap devices are semiconductor devices having a bandgap greater than or equal to 3.0 electron volts (eV). For example, the first transistor Q1, the first diode D1, the second transistor Q2, and the second diode D2 may be silicon carbide (SiC) devices or gallium nitride (GaN) devices. For reference purposes, si has a bandgap of about 1.1eV, while SiC has a bandgap of about 3.3 eV. As discussed above, the use of SiC for the first transistor Q1, the first diode D1, the second transistor Q2, and the second diode D1 significantly reduces the switching time of each device when compared to conventional silicon (Si) IGBT-based power modules, and additionally suffers from lower switching losses. For example, if the ratings of the power module 10 are 1200V and 300A, then the power module 10 may maintain switching losses of less than 25 millijoules (mJ), less than 20mJ, and even less than 15mJ while also providing a low on-state voltage drop when operating between-40 ℃ and 150 ℃. As will be appreciated by those skilled in the art, the switching loss of the power module 10 will not be below 1mJ. In further embodiments, the first transistor Q1, the first diode D1, the second transistor Q2, and the second diode D2 are majority carrier devices and wide bandgap devices.

In operation, the control system 12 operates the first and second switching modules SM1 and SM2 in a complementary manner so that when the first switching module SM1 is turned on, the second switching module SM2 is blocked and vice versa. A graph showing the voltage at the gate contact G of the first transistor Q1, the voltage at the gate contact G of the second transistor Q2, the voltage at the output terminal OUT and the current through the load 14 during a switching cycle of the power module 10 is shown in fig. 2. During the first period T1, the first switching module SM1 is turned on while the second switching module SM2 is blocked. Accordingly, the output terminal OUT is connected to the positive power supply terminal dc+ so as to supply the positive power supply voltage to the load 14 and cause a current to flow from the positive power supply terminal dc+ through the first transistor Q1 and into the load 14. In general, the load 14 is an inductive load such that the current through the load 14 increases slowly when the first switching module SM1 is switched on.

During the second period T2, the first switching module SM1 switches to the blocking mode. In addition, the second switching module SM2 maintains the blocking mode. During this time period, current continues to flow from the output terminal OUT to the load 14 due to the internal capacitance associated with each of the first and second switching modules SM1 and SM 2. Specifically, approximately half of the current through the load 14 is provided by the internal capacitance of each of the switching modules SM1 and SM 2. Thus, the voltage at the output terminal OUT transitions to ground at a given rate and the current through the load 14 gradually decreases.

When the second switching module SM2 switches to the on mode in the third period T3, the output terminal OUT is coupled to a negative supply terminal DC-, which may be grounded in some embodiments. Accordingly, a current flows through the second transistor Q2 and into the load 14 through the output terminal OUT, so that the current becomes more and more negative.

During the fourth period T4, the second switching module SM2 switches to the blocking mode. In addition, the first switching module SM1 is in blocking mode. In this period, negative current continues to flow from the output terminal OUT to the load due to the internal capacitance associated with each of the first and second switching modules SM1 and SM 2. Specifically, approximately half of the current through the load 14 is provided by the internal capacitance of each of the switching modules SM1 and SM 2. Thus, the voltage at the output terminal OUT is converted from ground to the positive supply voltage provided at the positive supply terminal dc+ and the current through the load 14 becomes increasingly positive. Finally, during the fifth period T5, the switching cycle is restarted such that the first switching module SM1 is in the on mode and the second switching module SM2 is in the off mode.

Fig. 3 shows details of the first switching module SM1 according to one embodiment of the present disclosure. The second switching module SM2 may be configured similarly to the first switching module SM2, but is not shown for simplicity. As shown in fig. 3, the first transistor Q1 and the first diode D1 of the first switching module SM1 may include a plurality of transistors Q1 _1-6 and a plurality of antiparallel diodes D1 _1-6 coupled in parallel. Specifically, the drain contacts D of each of the plurality of transistors Q1 _1-6 may be coupled together, the source contacts S of each of the transistors Q1 _1-6 may be coupled together, and the gate contacts G of each of the transistors Q1 _1-6 may be coupled together through the gate resistor R _G, respectively. Each of the transistors Q1 _1-6 includes an anti-parallel diode Q1 _1-6 coupled between a source contact S and a drain contact D thereof. Although six transistors Q1 _1-6 are shown coupled in parallel with six anti-parallel diodes D1 _1-6, any number of transistors and anti-parallel diodes may be used without departing from the principles of the present disclosure.

The inclusion of a plurality of parallel coupled transistors Q1 _1-6 and a plurality of anti-parallel diodes D1 _1-6 allows the first switching module SM1 to handle a greater amount of power than would otherwise be possible. For example, in one embodiment, each of the transistors Q1 _1-6 is rated to block 1.2kV and conduct 50A, thereby enabling the first switching module SM1 to conduct 300A. In other embodiments, each of the transistors Q1 _1-6 may be rated to block 1.2kV and pass to 40A, thereby enabling the first switching module SM1 to conduct 240A. In yet another embodiment, each of the transistors Q1 _1-6 may be rated to block 1.2kV and pass to 20A, thereby enabling the first switching module SM1 to conduct 120A.

The gate resistor R _G may be provided to suppress any undesired oscillations in the first switching module SM1 that may occur when the first switching module SM1 is driven at a relatively high transition speed (e.g. greater than 20V/ns). The resistance of the gate resistor R _G may vary depending on the current rating of each of the transistors Q1 _1-6 and thus all current ratings of the first switching module SM 1. In an embodiment in which the first switching module SM1 has a rated current of 120A, each of the gate resistors R _G has a resistance between about 1 Ω and 15 Ω. In a further embodiment, in which the first switching module SM1 has a rated current of 240A, each of the gate resistors R _G has a resistance between about 1 Ω and 15 Ω. In yet another embodiment, wherein the first switching module SM1 has a rated current of 300A, each of the gate resistors has a resistance between about 15 Ω and 20 Ω.

Fig. 4 shows details of the power module 10 according to one embodiment of the present disclosure. As shown in fig. 4, the power module 10 includes a housing 16 provided with an interior chamber 18 that holds one or more power substrates 20. Specifically, the interior chamber 18 of the housing 16 holds a first power substrate 20A, a second power substrate 20B, a third power substrate 20C, and a fourth power substrate 20D. It will be apparent to those skilled in the art that the interior chamber 18 of the housing 16 may house any number of power substrates 20 without departing from the principles of the present disclosure. Each of the power substrates 20 is shown to include a plurality of transistors Q, a plurality of diodes D, and a plurality of resistors R representing the main components of the first and second switching modules SM1 and SM 2. In one embodiment, the first switching module SM1 is provided by a first power substrate 20A and a second power substrate 20B, and the second switching module SM2 is provided by a third power substrate 20C and a fourth power substrate 20D, respectively. The necessary interconnections between the components on each of the power substrates 20 may be provided by metal traces (not shown) on the surface of the power substrate 20. In addition, bonding wires (not shown) may be provided to interconnect the different power substrates 20 and to connect the power substrates 20 to one or more external connectors (not shown). The power substrate 20 may be mounted to a mounting structure 22 that is attached to the housing 16. In one embodiment, the mounting structure 22 is a planar heat sink that also functions to dissipate heat generated by the first and second switching modules SM1 and SM 2.

As discussed above, the plurality of transistors Q and diodes D may be majority carrier devices, thereby reducing switching time and losses associated with each of the transistors Q and diodes D. Thus, the power module 10 may operate at a higher frequency and suffer less switching losses than conventional power modules. In addition, the transistor Q and the diode D may be wide band-gap devices (wide band-GAP DEVICE), such as SiC devices. As discussed above, the use of SiC for transistor Q and diode D significantly reduces the switching time and switching loss of transistor Q and diode D, thereby increasing the performance of power module 10.

Fig. 5 shows details of an exemplary mounting structure 22 and power substrate 20 according to one embodiment of the present disclosure. As shown in fig. 5, the first power substrate 20A, the second power substrate 20B, the third power substrate 20C, and the fourth power substrate 20D are disposed on the mounting structure 22. The first power substrate 20A includes three transistors Q1 _1-3 out of six transistors, three gate resistors R _G, and three anti-parallel diodes D1 _1-3 out of six anti-parallel diodes of the first switching module SM 1. The second power module includes the remaining transistor Q1 _4-6 of the first switching module SM1, the gate resistor R _G, and the anti-parallel diode D1 _4-6. similarly, the third power module 20C includes three transistors Q2 _1-3 out of the six transistors, three gate resistors R _G, and three antiparallel diodes D2 _1-3 out of the six antiparallel diodes of the second switching module SM 2. the fourth power substrate 20D includes the remaining transistor Q2 _4-6 of the second switching module SM2, the gate resistor R _G, and the anti-parallel diode D2 _4-6. Thicker black lines represent bonding wires between various components in the power module 10 and between various components of the power module 10 and the one or more output terminals 24. The output 24 of the power module 10 includes the first gate connector G1, the second gate connector G2, the first source return connector S1, and the second source return connector S2 as discussed above. Other connections between components on the power substrate 20 are provided with metal traces. Notably, the gate bus 26 is disposed on the power substrate 20 and runs between the gate contact G of the transistor Q2 _1-6 in the second switching module SM2 and the output 24 of the power module. In particular, the gate bus 26 runs between the gate contact G of the transistor Q2 _1-6 in the second switching module SM2 and the second gate connector G2 and may additionally provide a low power path from the source contact S of the transistor Q21-6 in the second switching module SM2 to the second source return connector S2. The gate bus 26 is a metal trace on each of the power substrates 20 that reduces interference of the power module 10 and increases the reliability of the connection between the gate contact of the transistor Q2 _1-6 in the second switching module SM2 and the output 24 of the power module 10, especially when compared to the "cross" gate connection used in conventional power modules. As shown, the mounting structure 22 may form all or a portion of a heat sink that functions to dissipate heat generated by the first and second switching modules SM1 and SM 2.

In one embodiment, the gate bus 26 may be replaced by one or more coaxial cables to connect the gate contact G of the transistor Q2 _1-6 in the second switching module and the output 24 of the power module 10. The use of coaxial cable to connect the output to the gate contact G of transistor Q2 _1-6 may provide improved isolation when compared to other solutions, thereby improving the performance of power module 10. In addition, although the outputs of the gate contacts G for both the switching module SM1 and the second switching module SM2 are provided on the same side of the housing 16 of the housing power module 10, in other embodiments they may be provided on opposite sides of the housing 16. Providing the output 24 of the gate contacts G of the first and second switching modules SM1, SM2 on opposite sides of the housing 16 may provide a shorter connection route to each of the gate contacts G of the second switching module SM2, thereby reducing interference and improving the durability of the power module 10. In addition, placing the output terminals 24 of the gate contacts G of the first and second switching modules SM1, SM2 on opposite sides of the housing 16 may reduce the required resistance of the gate resistor R _G of each of the transistors Q2 _1-6 in the second switching module SM2 because the shorter connection path between the gate contact G and the output terminal 24 reduces the amount of oscillation seen by the transistor Q2 _1-6.

Fig. 6 shows additional details of the housing 16, the output terminal OUT, the positive power terminal dc+ and the negative power terminal DC-according to one embodiment of the present disclosure. As shown in fig. 6, the housing 16 is substantially rectangular and includes cutouts for mounting holes M1-M4 for mounting the power module 10 to a platform. In addition, a positive power supply terminal dc+, a negative power supply terminal DC-, and an output terminal OUT are shown. As will be clear to those skilled in the art, stray inductances across the positive and negative power terminals dc+ and DC-can lead to reduced performance of the power module 10, especially at high frequency operation of the power module 10. Thus, the positive and negative power terminals dc+ and DC-are disposed close to each other, substantially spaced less than 1.5mm apart, so as to mitigate leakage inductance across the terminals. In addition, the terminals may be made wide, generally about 33.5mm wide, in order to maximize the area near the opposing terminals. Typically, the positive and negative power terminals dc+ and DC-will have an area between about 150mm ² and 200mm ² within 1.5mm of each other. In one embodiment, positive power terminal dc+ and negative power terminal DC-will have an area of about 187.31mm ² within 1.5mm of each other. As will be apparent to those skilled in the art, the capacitive effect created by placing a relatively large area of the positive power supply terminal dc+ in close proximity to a large area of the negative power supply terminal DC-reduces leakage inductance between the terminals, thereby improving the performance of the power module 10.

Fig. 7 illustrates additional details of the housing 16 according to one embodiment of the present disclosure. As shown in fig. 7, the housing 16 includes a power substrate 20, and provides output terminals for a positive power supply terminal dc+, a negative power supply terminal DC-, an output terminal OUT, and respective paths to connect the first and second switching modules SM1 and SM2 to the control system 12. Notably, the housing 16 and various output terminals are industry standard, allowing the power module 10 to be used as a built-in solution for the original platform. Further, a creepage separator (CREEPAGE DIVIDER) 28 is provided between each of the positive power supply terminal dc+, the negative power supply terminal DC-and the output terminal OUT, which increases the creepage distance between the respective terminals by about 50%. Thus, the power module 10 may be used in higher voltage applications without risk of short circuits or other damage.

As shown in fig. 7, one or more unused terminal locations 30 may be present in the housing 16. The unused terminal locations 30 may be used to provide a Kelvin (Kelvin) connection for one or more components of the power module 10 or may be used to provide a connection to an NTC temperature sensor module included in the power module 10 in various embodiments.

Fig. 8 illustrates a cut-out (cutaway) view of the power module 10 according to one embodiment of the present disclosure. Notably, an additional creepage divider 32 is provided between the positive and negative power terminals dc+ and DC-that separates the respective nodes from each other and thus protects against shorting under high voltage while at the same time allowing the power module 10 to utilize the reduction of leakage inductance between the nodes discussed above.

Fig. 9 shows details of the first power substrate 20A according to one embodiment of the present disclosure. The second, third, and fourth power substrates 20B, 20C, 20D may be configured similarly to the first power substrate 20A, but are not shown for simplicity. As shown in fig. 9, the first power substrate 20A is formed on a base plate (baseplate) 34 (which may be copper). Those skilled in the art will appreciate that there are many different materials for the bottom plate 34, all of which are contemplated herein. In one embodiment, the bottom plate 34 is aluminum silicon carbide (AlSiC), which may be lighter weight than copper and provide a better thermal match with one or more attached components. The bottom plate 34 may be shared between each of the power substrates 20 such that the first, second, third, and fourth power substrates 20A, 20B, 20C, and 20D are all formed on the bottom plate 34. A Direct Bonded Copper (DBC) substrate 36 may be disposed over the backplane 34. The DBC substrate 36 may include a first metal layer 38 on a surface of the base plate 34, an insulating layer 40 over the first metal layer 38, and a second metal layer 42 over the insulating layer 40 opposite the first metal layer 38. First metal layer 38 and second metal layer 42 may be, for example, copper. It will be apparent to those skilled in the art that there are many different suitable materials for first metal layer 38 and second metal layer 42, all of which are contemplated herein. The insulating layer 40 may be, for example, aluminum nitride (AlN). It will be apparent to those skilled in the art that there are many different suitable materials for insulating layer 40, such as aluminum oxide (Al ₂O₃) or silicon nitride (Si ₃N₄), all of which are contemplated herein.

The use of AlN for insulating layer 40 may provide a much higher thermal conductivity when compared to conventional aluminum oxide or silicon nitride (SiN) layers. The power module 10 may handle higher currents than conventional power modules in view of the relatively low resistance associated with SiC devices and the low thermal resistance of AlN. The thickness of the insulating layer 40 may be selected based on the target isolation voltage. Because of the advantages provided by the use of SiC components and AlN insulating layer 40, power module 10 is capable of handling greater power than conventional devices of the same size and/or may be reduced to smaller sizes than their conventional counterparts.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A power module, comprising:

a housing having an interior chamber;

first and second terminals, wherein a portion of the first and second terminals that are opposite to each other are arranged within 1.5 mm of each other to reduce at least a portion of a leakage inductance provided across the first and second terminals of the power module;

a creepage separator between the first terminal and the second terminal; and

A plurality of switching modules are mounted within the internal chamber between the first terminal and the second terminal and are interconnected to facilitate switching power to a load, wherein each of the plurality of switching modules includes at least one transistor and at least one diode.

2. The power module of claim 1, wherein the power module is capable of blocking at least 1200 volts and conducting at least 120 amperes, the power module having switching losses of less than 25 millijoules.

3 . The power module of claim 1 , wherein the at least one transistor and the at least one diode are silicon carbide devices.

4 . The power module of claim 3 , wherein the at least one transistor is a metal oxide semiconductor field effect transistor and the at least one diode is a Schottky diode.

5 . The power module of claim 3 , wherein the at least one transistor is coupled in anti-parallel to the at least one diode.

6 . The power module of claim 1 , wherein the first terminal and the second terminal comprise an area of at least 150 mm ² .

7 . The power module of claim 1 , wherein the at least one diode is an internal body diode of the at least one transistor.

8 . The power module of claim 1 , wherein at least one diode is external to the at least one transistor.

9. The power module according to claim 1, wherein:

The power module further includes a power substrate;

Each of the plurality of switching modules further comprises at least one gate resistor; and

The at least one gate resistor, the at least one transistor and the at least one diode of each of the plurality of switching modules are mounted on the power substrate so that a surface of the power substrate provides electrical connections between the at least one gate resistor, the at least one transistor and the at least one diode of each of the plurality of switching modules.

10. The power module of claim 9, wherein the power substrate comprises aluminum nitride.

11 . The power module of claim 10 , further comprising: a base plate, such that the power substrate is on the base plate, and the base plate comprises silicon aluminum nitride.

12 . The power module of claim 1 , wherein the creepage separator is a part of the housing.

13 . The power module of claim 1 , wherein the creepage separator provides electrical isolation between the first terminal and the second terminal.

14. A power module, comprising:

a housing having an interior chamber;

a first power substrate and a second power substrate within the interior chamber;

a plurality of transistors, the plurality of transistors comprising a first plurality of transistors, wherein the first plurality of transistors are on a surface of the first power substrate, the first plurality of transistors form a portion of a switching module, and the plurality of transistors further comprises a second plurality of transistors;

The second plurality of transistors are on a surface of the second power substrate; and

A gate connector is coupled to a gate contact of each of the first plurality of transistors via a gate connection bus comprising a gate bus conductive trace on a surface of the first power substrate extending between the first plurality of transistors and the second plurality of transistors.

15 . The power module of claim 14 , wherein the gate bus conductive trace runs between opposing sides of the first and second power substrates.

16. The power module according to claim 14,

Wherein, the plurality of transistors are silicon carbide devices.

17 . The power module of claim 16 , wherein the gate connector is coupled to the gate contact of each of the plurality of transistors via the gate connection bus and one or more coaxial cables.

18. The power module according to claim 16, further comprising:

a first terminal and a second terminal, the first terminal and the second terminal comprising an area of at least 150 ^mm2 ; and

A creepage separator is between the first terminal and the second terminal.

19. The power module of claim 16, wherein the power module is capable of blocking at least 1200 volts and conducting at least 120 amps, the power module having switching losses of less than 25 millijoules.

20. A power module, comprising:

a housing having an interior chamber;

a first terminal and a second terminal;

a creepage separator between the first terminal and the second terminal; and

a plurality of switching modules mounted within the interior chamber and interconnected to facilitate switching power to a load, wherein each of the plurality of switching modules includes at least one transistor configured to conduct current in a first direction via a channel in the at least one transistor and to conduct current in a second direction opposite to the first direction via an internal body diode in the at least one transistor,

A portion of the first terminals and a portion of the second terminals that are opposite to each other are arranged within 1.5 mm of each other to reduce at least a portion of the leakage inductance provided across the terminals.

21. The power module of claim 20, wherein the power module is capable of blocking 1200 volts and conducting at least 120 amps, the power module having switching losses of less than 25 millijoules.

22. The power module of claim 20, wherein the at least one transistor is a silicon carbide (SiC) device.

23. The power module of claim 20, wherein the first terminal and the second terminal comprise an area of at least 150 ^mm2 to reduce leakage inductance between the first terminal and the second terminal, and wherein the power module is configured to operate at a switching frequency of at least 50 kHz.