CN111900140A - High-efficiency heat-dissipation gallium nitride transistor based on diamond passivation structure and manufacturing method thereof - Google Patents
High-efficiency heat-dissipation gallium nitride transistor based on diamond passivation structure and manufacturing method thereof Download PDFInfo
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Abstract
Description
技术领域technical field
本发明属于新型半导体器件热管理技术研究领域,特别是涉及一种基于金刚石钝化结构的高效散热氮化镓晶体管及其制造方法。The invention belongs to the research field of thermal management technology of novel semiconductor devices, in particular to a high-efficiency heat dissipation gallium nitride transistor based on a diamond passivation structure and a manufacturing method thereof.
背景技术Background technique
以氮化镓为代表的第三代半导体功率器件已展现出其优异的大功率应用特性,在实际应用中的氮化镓器件的功率密度仅达到3-8W/mm,远低于于其理论值,氮化镓大功率的特性优势远未得到发挥。这主要是因为氮化镓器件在输出大功率的同时会产生大量热积累,功率越大热积累约严重,热积累导致氮化镓晶体管芯结温的升高,使器件性能和可靠性都急剧衰减。目前氮化镓基功率器件由于自身材料的导热能力无法满足器件大功率化的发展,散热问题严重限制了氮化镓器件的性能,因此进行氮化镓半导体器件的热管理开发成为了解决其大功率应用的主要技术瓶颈。因此,探索高导热材料与氮化镓器件近结区集成的热管理方法将是解决氮化镓器件热积累,适应其大功率化的主要途径和研究热点。The third-generation semiconductor power devices represented by gallium nitride have shown their excellent high-power application characteristics. The power density of gallium nitride devices in practical applications only reaches 3-8W/mm, which is far lower than its theoretical The high-power characteristic advantage of GaN is far from being brought into play. This is mainly because gallium nitride devices will generate a lot of heat accumulation while outputting high power. The greater the power, the more serious the heat accumulation will be. The heat accumulation will lead to an increase in the junction temperature of the gallium nitride transistor core, which will sharply increase the performance and reliability of the device. attenuation. At present, the thermal conductivity of GaN-based power devices cannot meet the development of high-power devices due to the thermal conductivity of their own materials, and the heat dissipation problem severely limits the performance of GaN-based devices. The main technical bottleneck of power application. Therefore, exploring the thermal management method for the integration of high thermal conductivity materials and GaN devices near the junction region will be the main way and research hotspot to solve the heat accumulation of GaN devices and adapt to its high power.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种基于金刚石钝化结构的高效散热氮化镓晶体管及其制造方法,解决氮化镓功率器件芯片有源区的热积累问题,进行芯片级热管理技术开发,提升氮化镓器件的输出特性和可靠性。The purpose of the present invention is to provide a high-efficiency heat dissipation gallium nitride transistor based on a diamond passivation structure and a manufacturing method thereof, to solve the problem of heat accumulation in the active area of gallium nitride power device chips, to develop chip-level thermal management technology, and to improve nitrogen output characteristics and reliability of GaN devices.
实现本发明目的的技术解决方案为:一种基于金刚石钝化结构的高效散热氮化镓晶体管,该结构设计自上而下依次包括金刚石钝化层、栅源漏功能层、势垒层、缓冲层及衬底,所述的金刚石钝化层为多层结构,包含势垒保护层、种子层和导热层。The technical solution to achieve the purpose of the present invention is: a high-efficiency heat dissipation gallium nitride transistor based on a diamond passivation structure, the structure design includes a diamond passivation layer, a gate-source-drain functional layer, a potential barrier layer, a buffer layer from top to bottom in order Layer and substrate, the diamond passivation layer is a multi-layer structure, including a barrier protection layer, a seed layer and a heat conduction layer.
进一步的,势垒保护层材料为厚度10-30纳米的SiN或AlN介质,种子层材料为厚度10-50纳米的碳基介质,导热层为厚度400-600纳米的金刚石介质。Further, the material of the barrier protection layer is SiN or AlN medium with a thickness of 10-30 nanometers, the material of the seed layer is a carbon-based medium with a thickness of 10-50 nanometers, and the thermal conductive layer is a diamond medium with a thickness of 400-600 nanometers.
进一步的,所述金刚石钝化层采用分步、低温生长过程,首先生长势垒保护层介质、再生长种子层材料、最后生长导热层材料。Further, the diamond passivation layer adopts a step-by-step, low-temperature growth process, firstly growing the barrier protective layer medium, then growing the seed layer material, and finally growing the thermal conductive layer material.
一种基于金刚石钝化结构的高效散热氮化镓晶体管制造方法,包括如下步骤:A method for manufacturing a high-efficiency heat dissipation gallium nitride transistor based on a diamond passivation structure, comprising the following steps:
1)源漏功能区制备:进行源和漏的功能区的生长;1) Preparation of source and drain functional regions: the growth of source and drain functional regions;
2)金刚石钝化制备:先采用CVD工艺进行势垒保护层的生长,势保护层厚度在10-30纳米,材料为SiN或AlN介质;其次进行种子层生长,种子层厚度为厚度10-50纳米的碳基介质;最后采用CVD技术进行金刚石导热层生长,导热层厚度在400-600纳米,生长温度不高于750℃;2) Diamond passivation preparation: First, the CVD process is used to grow the barrier protective layer, the thickness of the potential protective layer is 10-30 nanometers, and the material is SiN or AlN medium; secondly, the seed layer is grown, and the thickness of the seed layer is 10-50 nm. Nanometer carbon-based medium; finally, CVD technology is used to grow the diamond thermal conductive layer, the thickness of the thermal conductive layer is 400-600 nanometers, and the growth temperature is not higher than 750 °C;
3)栅区金刚石刻蚀:进行金刚石钝化层的刻蚀,实现氮化镓功能层栅区的制备;3) gate area diamond etching: carry out the etching of the diamond passivation layer to realize the preparation of the gate area of the gallium nitride functional layer;
4)栅金属生长:采用栅工艺生长,进行氮化镓功能层栅金属的制备,栅金属厚度比金刚石钝化层厚度大50-100纳米;4) Gate metal growth: The gate metal is grown by the gate process to prepare the gate metal of the gallium nitride functional layer. The thickness of the gate metal is 50-100 nanometers larger than that of the diamond passivation layer;
5)源漏区金刚石刻蚀:进行金刚石钝化层的刻蚀,实现氮化镓功能层源漏加厚互连区的制备;5) Diamond etching in the source and drain regions: etching the diamond passivation layer to realize the preparation of the source-drain thickening interconnection region of the gallium nitride functional layer;
6)源漏功能区互连制备:采用金蒸发生长工艺进行源和漏功能区的加厚互连,源漏总厚度金刚石钝化层厚度大50-100纳米;完成基于金刚石钝化结构的高效散热氮化镓晶体管制造。6) Interconnection preparation of source and drain functional regions: The thickening interconnection of source and drain functional regions is carried out by using gold evaporation growth process, and the total thickness of source and drain diamond passivation layer is 50-100 nanometers thick; Thermal GaN transistor fabrication.
进一步的,步骤3)和步骤5)中采用光刻和ICP工艺进行金刚石钝化层的刻蚀。Further, in step 3) and step 5), photolithography and ICP process are used to etch the diamond passivation layer.
本发明与现有技术相比,其显著优点为:本发明利用CVD技术对氮化镓晶体管进行金刚石钝化生长,并通过多步刻蚀技术实现金刚石栅区的制备,在氮化镓晶体管热源区上表面形成高导热金刚石散热层,近而实现氮化镓晶体管芯片级热管理新技术开发,提升氮化镓晶体管的近结区的散热能力,解决其热积累问题;(2)本发明将高导热金刚石材料集成至氮化镓芯片内部,提升了片内近结区的散热能力,相比传统的氮化镓器件,器件热阻可下降20%以上,解决了氮化镓器件有源区的热积累,极大提高了器件的可靠性。Compared with the prior art, the present invention has significant advantages as follows: the present invention utilizes CVD technology to conduct diamond passivation growth on gallium nitride transistors, and realizes the preparation of diamond gate regions by multi-step etching technology. A high thermal conductivity diamond heat dissipation layer is formed on the upper surface of the gallium nitride transistor, so as to realize the development of new technology of chip-level thermal management of gallium nitride transistors, improve the heat dissipation capability of the near junction area of gallium nitride transistors, and solve the problem of heat accumulation; (2) the present invention will The high thermal conductivity diamond material is integrated into the gallium nitride chip, which improves the heat dissipation capability of the near-junction area on the chip. Compared with the traditional gallium nitride device, the thermal resistance of the device can be reduced by more than 20%, which solves the problem of the active area of the gallium nitride device. The heat accumulation greatly improves the reliability of the device.
附图说明Description of drawings
图1是本发明基于金刚石钝化结构的高效散热氮化镓晶体管器件结构示意图。FIG. 1 is a schematic structural diagram of a high-efficiency heat dissipation gallium nitride transistor device based on a diamond passivation structure of the present invention.
图2包括图2a、图2b、图2c、图2d、图2e、图2f,是本发明提出的一种基于金刚石钝化结构的高效散热氮化镓晶体管设计和制造方法的工备流程示意图。2 includes FIG. 2a, FIG. 2b, FIG. 2c, FIG. 2d, FIG. 2e, and FIG. 2f, and is a schematic diagram of the process flow of the design and manufacturing method of a high-efficiency heat dissipation gallium nitride transistor based on a diamond passivation structure proposed by the present invention.
具体实施方式Detailed ways
下面结合附图和实施例对本发明的具体实施方式进一步进行详细说明。The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
参照图1,本发明提出的一种基于金刚石钝化结构的高效散热氮化镓晶体管及制造方法,其高效散热氮化镓晶体管结构设计自上而下依次包括金刚石钝化层3、源漏栅功能层1、2、4、势垒层5、缓冲层6及衬底7。所述金刚石钝化层3是多层结构,包含势垒保护层、种子层和导热层,具有高导热作用,有效降低氮化镓晶体管的结温。势垒保护层材料为厚度10-30纳米的SiN或AlN介质,种子层材料为厚度10-50纳米的碳基介质,导热层为厚度400-600纳米的金刚石介质。所述的高效散热氮化镓晶体管衬底7为Si、蓝宝石、SiC材料的任意一种,缓冲层6为GaN材料,势垒层为AlGaN材料;Referring to FIG. 1 , a high-efficiency heat-dissipating gallium nitride transistor based on a diamond passivation structure and a manufacturing method proposed by the present invention, the high-efficiency heat-dissipating gallium nitride transistor structure design includes a
参照图2,本发明的一种基于金刚石钝化结构的高效散热氮化镓晶体管制造方法,晶体管传统工艺与金刚石钝化生长的兼容性用以下步骤解决:Referring to FIG. 2 , a method for manufacturing a high-efficiency heat-dissipating gallium nitride transistor based on a diamond passivation structure of the present invention, the compatibility between the traditional process of the transistor and the diamond passivation growth is solved by the following steps:
1)源漏功能区制备:采用传统工艺进行源1-1和漏2-1的功能区的生长,如图2a所示;1) Preparation of source-drain functional regions: The functional regions of source 1-1 and drain 2-1 are grown using traditional processes, as shown in Figure 2a;
2)金刚石钝化制备:先采用CVD工艺进行势垒保护层3-1的生长,势保护层厚度在10-30纳米,材料为SiN或AlN介质;其次进行种子层3-2生长,种子层厚度为厚度10-50纳米的碳基介质;最后采用CVD技术进行金刚石导热层3-3生长,导热层厚度在400-600纳米,生长温度不高于750℃;如图2b所示;2) Diamond passivation preparation: firstly, the CVD process is used to grow the barrier protection layer 3-1, the thickness of the potential protection layer is 10-30 nanometers, and the material is SiN or AlN medium; secondly, the seed layer 3-2 is grown, and the seed layer is A carbon-based medium with a thickness of 10-50 nanometers; finally, CVD technology is used to grow the diamond thermal conductive layer 3-3, the thermal conductive layer thickness is 400-600 nanometers, and the growth temperature is not higher than 750 °C; as shown in Figure 2b;
3)栅区金刚石刻蚀:采用光刻和ICP等工艺进行金刚石钝化层的刻蚀,实现氮化镓功能层栅区4-1的制备,如图2c所示;3) gate area diamond etching: use photolithography, ICP and other processes to etch the diamond passivation layer to realize the preparation of the gate area 4-1 of the gallium nitride functional layer, as shown in Figure 2c;
4)栅金属生长:采用传统栅工艺生长,进行氮化镓功能层栅金属4的制备,栅金属厚度比金刚石钝化层厚度大50-100纳米,如图2d所示;4) Gate metal growth: The traditional gate process is used to grow, and the
5)源漏区金刚石刻蚀::采用光刻和ICP等工艺进行金刚石钝化层的刻蚀,实现氮化镓功能层源漏加厚互连区1-2、2-2的制备,如图2e所示;5) Diamond etching in the source and drain regions: The diamond passivation layer is etched by photolithography and ICP processes to realize the preparation of the source-drain thickening interconnection regions 1-2 and 2-2 of the gallium nitride functional layer, such as As shown in Figure 2e;
6)源漏功能区互连制备:采用传统金蒸发生长工艺进行源1和漏2功能区的加厚互连,源漏总厚度金刚石钝化层厚度大50-100纳米,如图2f所示;完成基于金刚石钝化结构的高效散热氮化镓晶体管制造。6) Interconnection preparation of source and drain functional regions: The traditional gold evaporation growth process is used to thicken the interconnection of
下面结合实施例对本发明进行详细说明。The present invention will be described in detail below with reference to the embodiments.
实施例Example
一种基于金刚石钝化结构的高效散热氮化镓晶体管设计和制造方法,具体包括:A method for designing and manufacturing a high-efficiency heat-dissipating gallium nitride transistor based on a diamond passivation structure, specifically comprising:
1)基于GaN外延材料,采用传统源、漏蒸发工艺进行源和漏功能区的生长,厚度为200纳米;1) Based on GaN epitaxial materials, the source and drain functional regions are grown by traditional source and drain evaporation processes, with a thickness of 200 nanometers;
2)先采用CVD工艺进行SiN势垒保护层的生长,SiN厚度为20纳米;其次进行纳米碳基种子层生长,厚度为20纳米;最后采用CVD技术进行金刚石导热层生长,生长厚度为460纳米,生长温度为740℃;2) First, the CVD process is used to grow the SiN barrier protection layer, and the thickness of SiN is 20 nanometers; secondly, the nanocarbon-based seed layer is grown with a thickness of 20 nanometers; finally, the CVD technology is used to grow the diamond thermal conductive layer, and the growth thickness is 460 nanometers. , the growth temperature is 740℃;
3)设计栅长为0.4微米,采用光刻和ICP等工艺进行金刚石钝化层的刻蚀,刻蚀气体采用氧气和氩气,完成氮化镓功能层栅区的制备;3) The designed gate length is 0.4 microns, and the diamond passivation layer is etched by photolithography and ICP, and the etching gas is oxygen and argon to complete the preparation of the gate region of the gallium nitride functional layer;
4)采用传统栅工艺生长,进行氮化镓功能层栅金属的制备,栅金属厚度为550纳米;4) The traditional gate process is used to grow, and the gate metal of the gallium nitride functional layer is prepared, and the thickness of the gate metal is 550 nanometers;
5)采用传统光刻和ICP等工艺对源漏上的金刚石钝化层进行刻蚀,刻蚀气体采用氧气和氩气,刻蚀区域和源漏尺寸一致,完成氮化镓功能层源漏加厚互连区的制备;5) The diamond passivation layer on the source and drain is etched by traditional lithography and ICP processes. The etching gas is oxygen and argon. The etching area is consistent with the size of the source and drain. Preparation of thick interconnect regions;
6)最后采用传统金蒸发生长工艺进行源和漏功能区的加厚互连,互连加厚的金属厚度为350纳米,源漏总厚度为550纳米;完成基于金刚石钝化结构的高效散热氮化镓晶体管制造。6) Finally, the traditional gold evaporation growth process is used to thicken the interconnection of the source and drain functional regions. The thickened metal thickness of the interconnection is 350 nanometers, and the total thickness of the source and drain is 550 nanometers; complete the high-efficiency heat dissipation nitrogen based on the diamond passivation structure GaN transistor fabrication.
本发明经反复试验验证,取得了满意的试用效果。本发明的金刚石钝化结构的氮化镓基器件具有高效散热的能力的优点,可用于超大功率微波功率器件。The present invention has been verified by repeated tests, and a satisfactory trial effect has been obtained. The gallium nitride-based device of the diamond passivation structure of the present invention has the advantages of efficient heat dissipation capability, and can be used for ultra-high power microwave power devices.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838816A (en) * | 2021-09-29 | 2021-12-24 | 太原理工大学 | Preparation method of gallium nitride-based diode device with diamond passivation layer |
| CN114005804A (en) * | 2021-09-30 | 2022-02-01 | 中国电子科技集团公司第五十五研究所 | Diamond passivated gallium nitride device multi-finger gate interconnection structure and preparation method thereof |
| CN115547953A (en) * | 2022-10-11 | 2022-12-30 | 天津市滨海新区微电子研究院 | Heat dissipation structure and manufacturing method of a power device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146186A1 (en) * | 2007-12-07 | 2009-06-11 | The Government of the United State of America, as represented by the Secretary of the Navy | Gate after Diamond Transistor |
| WO2011163318A2 (en) * | 2010-06-23 | 2011-12-29 | Cornell University | Gated iii-v semiconductor structure and method |
| CN110349924A (en) * | 2019-06-23 | 2019-10-18 | 中国电子科技集团公司第五十五研究所 | A kind of lifting tab is embedded in the process of diamond gallium nitride transistor thermotransport ability |
| CN110379782A (en) * | 2019-06-23 | 2019-10-25 | 中国电子科技集团公司第五十五研究所 | Diamond heat dissipation gallium nitride transistor and preparation method are embedded in based on the piece for etching and orienting extension |
| US20200203520A1 (en) * | 2018-12-20 | 2020-06-25 | Texas Instruments Incorporated | Gallium nitride devices including a tunnel barrier layer |
-
2020
- 2020-06-30 CN CN202010615260.5A patent/CN111900140A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146186A1 (en) * | 2007-12-07 | 2009-06-11 | The Government of the United State of America, as represented by the Secretary of the Navy | Gate after Diamond Transistor |
| WO2011163318A2 (en) * | 2010-06-23 | 2011-12-29 | Cornell University | Gated iii-v semiconductor structure and method |
| US20200203520A1 (en) * | 2018-12-20 | 2020-06-25 | Texas Instruments Incorporated | Gallium nitride devices including a tunnel barrier layer |
| CN110349924A (en) * | 2019-06-23 | 2019-10-18 | 中国电子科技集团公司第五十五研究所 | A kind of lifting tab is embedded in the process of diamond gallium nitride transistor thermotransport ability |
| CN110379782A (en) * | 2019-06-23 | 2019-10-25 | 中国电子科技集团公司第五十五研究所 | Diamond heat dissipation gallium nitride transistor and preparation method are embedded in based on the piece for etching and orienting extension |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838816A (en) * | 2021-09-29 | 2021-12-24 | 太原理工大学 | Preparation method of gallium nitride-based diode device with diamond passivation layer |
| CN113838816B (en) * | 2021-09-29 | 2024-02-02 | 太原理工大学 | A method for preparing a gallium nitride-based diode device with a diamond passivation layer |
| CN114005804A (en) * | 2021-09-30 | 2022-02-01 | 中国电子科技集团公司第五十五研究所 | Diamond passivated gallium nitride device multi-finger gate interconnection structure and preparation method thereof |
| CN115547953A (en) * | 2022-10-11 | 2022-12-30 | 天津市滨海新区微电子研究院 | Heat dissipation structure and manufacturing method of a power device |
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