CN111898254A - A second-order band-pass sampling clock jitter modeling method and compensation method - Google Patents

Abstract

The present invention proposes a clock jitter modeling method and compensation method for a second-order band-pass sampling system. The present invention first introduces a delay T _Δ between two sampling channels of the second-order band-pass sampling system, and then performs a The clock jitter modeling is based on the clock jitter, and the fixed part and the frequency-dependent part of the clock jitter are obtained. This part of the frequency-dependent part is the hardware error; based on the hardware error, the output signal of the second-order bandpass sampling is subjected to hardware error compensation, and then for the clock jitter Then, based on the phase adjustment filtering algorithm, an appropriate filter is designed to compensate the error of the fixed part of the clock jitter. The invention can be applied to the existing phase adjustment filtering algorithm, can eliminate the influence of clock jitter error on the system, make the fixed sampling delay introduced into the system more accurate, and improve the anti-aliasing performance of the phase adjustment filtering algorithm.

Description

A second-order band-pass sampling clock jitter modeling method and compensation method

technical field

The present invention relates to the technical field of radio band-pass sampling and software radio, in particular to a second-order band-pass sampling clock jitter modeling method and compensation method.

Background technique

As a method and means to realize wireless communication, software radio is widely used in wireless communication. In the process of realizing as many functions of software radio as possible through software algorithm, it is often necessary to study a sampling system with high flexibility and wide sampling range to sample the radio frequency signal in its working frequency band. However, in the process of band-pass sampling, aliasing problems after sampling of useful signals in different frequency bands and self-image aliasing problems of the signals are common, which affects the normal reception of multi-mode and multi-band signals on the same platform.

In order to improve the validity of the signal received by the receiver, it is necessary to analyze the signal aliasing problem in the sampling process, and gradually realize the optimal solution from the sampling frequency, sampling structure, sampling analog device and so on. The existing phase adjustment filtering algorithm is proposed to solve the problem of signal aliasing after band-pass sampling. The conditions for this algorithm to be used in software radio second-order band-pass sampling receivers are: use a clock generator to introduce one of the samples after sampling. The sampling delay is fixed to generate a phase difference, and a digital filter is designed with the phase difference of the two signals after sampling as a parameter to eliminate signal aliasing. Therefore, accurate delay is the key to the phase adjustment filtering algorithm. Since the clock signal provided by the clock generator for ADC B is relative to ADC A, in addition to the artificially required delay, there will also be clock jitter, so it affects One of the main factors of the performance of the sampled signal, the modeling analysis and error compensation of the clock signal jitter is one of the core problems to be solved in the establishment of a sampling system.

SUMMARY OF THE INVENTION

Purpose of the invention: In order to solve the above technical problems, the present invention proposes a second-order band-pass sampling clock jitter modeling method and compensation method.

Technical solution: The present invention aims to realize the modeling of the clock jitter error in the second-order band-pass sampling system, and to perform error compensation for the clock jitter error.

In order to achieve the above object, one aspect of the present invention proposes a second-order bandpass sampling system clock jitter modeling method, which includes the following steps:

(1) A delay TΔ is introduced between the two sampling channels of the second-order bandpass sampling system;

(2) Establish a phase difference model including the effect of clock jitter:

表示采样后相位差中实际的延时；f表示输入二阶带通采样系统的信号的频率，f_s表示采样频率，

g(f)表示群延迟产生的线性相位，

表示采样系统硬件引入的非线性相位，也就是时钟抖动当中随频率变化的部分；Among them, θ _real (f) represents the phase difference between the two sampling signals of the second-order band-pass sampling system under the influence of clock jitter, T _c represents the clock delay error, that is, the fixed delay in the clock jitter,

represents the actual delay in the phase difference after sampling; f represents the frequency of the signal input to the second-order band-pass sampling system, f _s represents the sampling frequency,

g(f) represents the linear phase due to the group delay,

Represents the nonlinear phase introduced by the sampling system hardware, that is, the frequency-dependent part of the clock jitter;

(3) With a fixed sampling frequency, a fixed delay T _Δ and a limited frequency offset range, the random frequency conversion single-spectrum signal is used as the input signal of the second-order bandpass sampling system for sampling, and the frequency region index is selected according to the frequency offset range. , when the output of the system deviates from the frequency region index, measure the two output signals of the second-order band-pass sampling system, and calculate the phase difference; select multiple different frequency region indexes for multiple measurements, and obtain multiple phase differences and then perform quadratic curve fitting on the measured phase difference value to obtain the nonlinear error coefficient of the clock delay, ie h ₁ ~ h ₃ , and then obtain the nonlinear phase

代入所述相位差模型，完成二阶带通采样系统时钟抖动建模。(4) will

Substitute the phase difference model to complete the clock jitter modeling of the second-order bandpass sampling system.

On the other hand, the present invention provides a clock jitter compensation method for a second-order bandpass sampling system, comprising the following steps:

的计算公式，确定

的值；(1) Determine the frequency f of the signal to be sampled, and the nonlinear phase calculated according to claim 1

calculation formula, determine

the value of;

作为非线性相位误差的补偿值，对二阶带通采样系统采样后的信号进行硬件误差补偿；(2) Take

As the compensation value of the nonlinear phase error, the hardware error compensation is performed on the signal sampled by the second-order band-pass sampling system;

(3) Use the phase adjustment filtering algorithm to compensate the fixed part of the clock jitter:

Denote the phase difference between the two sampling signals R ₀ (f) and R ₁ (f) processed in step (2) as β _n , at this time, β _n only contains the fixed part of the clock jitter, that is

和

Design three filter units S _A (f),

and

滤波后的结果相加，得到一路输出信号；R₀(f)经过S_A(f)滤波后与R₁(f)经过

滤波后的结果相加，得到另一路输出信号(4) R ₀ (f) filtered by S _A (f) and R ₁ (f)

The filtered results are added to obtain one output signal; R ₀ (f) is filtered by S _A (f) and R ₁ (f) is

The filtered results are added to obtain another output signal

Beneficial effect: Compared with the prior art, the present invention has the following advantages:

The invention divides the clock jitter error into a fixed linear part and a non-linear part that varies with frequency, and then models the clock jitter error of the entire second-order band-pass sampling system. Based on the modeling results, the linear part of the clock jitter error is divided and the nonlinear part to compensate. The invention can be applied to the existing phase adjustment filtering algorithm, can eliminate the influence of clock jitter error on the system, make the fixed sampling delay introduced into the system more accurate, and improve the anti-aliasing performance of the phase adjustment filtering algorithm.

Description of drawings

Fig. 1 is the overall flow chart of the present invention;

的条件下，带通采样接收机的SIR和α和θ_ε的函数关系图；Figure 2 is an example where the

Under the condition of , the functional relationship between SIR and α and θ _ε of the band-pass sampling receiver;

FIG. 3 is a schematic diagram of the result of quadratic fitting for nonlinear residual phase error;

Fig. 4 is the overall phase shift measurement of the BPS platform in the test process and the image of the test results;

Fig. 5 is the residual phase error histogram of quadratic fitting in the testing process;

FIG. 6 is a diagram illustrating the implementation of the phase adjustment filtering algorithm.

Detailed ways

The main purpose of this patent is to provide a software radio second-order bandpass sampling receiver with adjustable delay, which can model and analyze the phase error between two sampling signals caused by clock jitter, including fixed part and The part that varies with the frequency, and the error caused by the fixed part is utilized, and the polynomial fitting compensation is performed on the part that varies with the frequency, so as to achieve the technical scheme of eliminating the error.

In order to achieve the above object, the present invention firstly analyzes the clock jitter error in the second-order band-pass sampling system.

First, the inverse phase interpolation method is used to measure the performance of the second-order bandpass system when it separates the desired frequency signal: Assuming that the input signal stream x[f] of the software radio second-order bandpass sampling receiver contains two signals of different frequencies, this The frequency of the signal to be used is one of them, and being able to separate it is the basic function of a bandpass sampling system. After x[f] is sampled by ADC-A and ADC-B, two signals x _a [k] and x _b [k] are formed respectively. If the signal flow of ADC-B is inverted with that of ADC-A and If their amplitudes are exactly the same, after the two signal streams are added, the inverted signal in them will be completely eliminated. However, since perfect phase shift and amplitude balance cannot be achieved in the real world, there is still a residual after adding the signal of the frequency we want and the signal to remove the frequency out of phase.

和

To simplify the analysis, assume that an RF signal stream containing two frequencies is sampled and shifted down to baseband via a second-order BPS. As shown in (1-1), the A signal stream x _a [k] and the B signal stream x _b [k] are generated after sampling, where ω ₁ is the frequency of the desired signal and ω ₂ is the frequency of the signal to be removed , where T _S is the sampling period, and A ₁ and A ₂ are the corresponding amplitudes of the above two frequency signals, respectively. Note that due to the sampling process, signal stream B adds a phase shift relative to signal stream A, respectively

and

Under ideal conditions, with the correct phase given, signal stream B adjusts the phase of the signal that should be removed to be 180° out of phase with the signal in signal stream A. However, the presence of phase errors results in a lack of perfect matching in the two signal paths resulting in an amplitude imbalance. After passing a given π phase, the signal in the signal stream B is given by (1-2), where _θε and α represent the phase error and amplitude imbalance caused by the inverse interpolation operation, respectively.

之间。要说明的是，在反相插值操作时要选择合适的延时，以保持C尽可能大以获得高SNR。The suppressed signal given in (1-3) is obtained by adding (1-1) and (1-2). s _D [k] and N _ε [k] denote the desired signal and residual signal, respectively, C denotes a complex constant, which depends on the input signal bandwidth, sampling frequency and time delay chosen during the time-domain inverse interpolation operation, Its absolute value can be in

between. It should be noted that a suitable delay should be selected during the inverse interpolation operation to keep C as large as possible to obtain a high SNR.

We can conclude from the above analysis that the average signal-to-noise ratio (SIR) of the reconstructed sample s[k] is

where E[·] represents the expectation operator, assuming that A ₁ =A ₂ .

Figure 2 shows the functions of α and θ _ε in equation (1-4). In this figure, the reference plane represents the SIR value of 45dB. To achieve a higher value of SIR, α and _θε need to satisfy reasonable values. Points P1, P2 and P3 represent the α and _θε values when 45dB SIR is obtained; at points P4 and P5, 40.59dB and 37.04dB SIR are obtained, respectively. It can be seen from the image that to obtain more than 40dB of suppression when separating the desired signal, the phase error should be less than 0.8°, and the amplitude error should be less than 1.5%. When there are more frequencies in different regions in the signal stream to be received, this method can be used for analysis many times, and a similar conclusion can be obtained.

Based on the above analysis, we propose a technical solution to solve the technical problem, the overall principle of which is shown in Figure 1:

First, a delay T _Δ is introduced between the two sampling channels of the second-order band-pass sampling system, and then the clock jitter in the second-order band-pass sampling is modeled to obtain the fixed part and the frequency-dependent part of the clock jitter. The changed part is the hardware error; hardware error compensation is performed on the output signal of the second-order band-pass sampling based on the hardware error, and then for the fixed part of the clock jitter, based on the phase adjustment filtering algorithm, an appropriate filter is designed to fix the clock jitter part of the error compensation.

The above steps will be described in detail below.

1. System phase shift description and modeling: For the software radio second-order band-pass sampling system with adjustable delay, according to the band-pass sampling theory, the phase difference between ADC-B and ADC-A can ideally use the equation Description of (1-5), where n represents the position index of the signal in the Nyquist frequency region on the spectrum after band-pass sampling, T _Δ is the adjustable delay artificially introduced by the clock generator, f represents the signal frequency, f _s represents the sampling frequency. Since the clock jitter phenomenon of ADC-B sampling clock relative to ADC-A will also cause phase shift, resulting in the degradation of SIR performance, we introduce a new equation (1-6) to describe the actual phase shift of the actual above system, and establish a formula including Phase difference model for clock jitter effects.

θ _theory (f)=2πnf _s T _Δ +2πf ₀ T _Δ (1-5)

此处T_c表示时钟延迟误差，也就是时钟抖动当中的固定延时；

代表群延迟产生的线性相位；

则表示BPS硬件引入的非线性相位，也就是时钟抖动当中随频率变化的部分。in,

Here T _c represents the clock delay error, that is, the fixed delay in the clock jitter;

represents the linear phase produced by the group delay;

It represents the nonlinear phase introduced by the BPS hardware, that is, the frequency-dependent part of the clock jitter.

(LTE信号)，n＝20覆盖

(WCDMA信号)。来测量在ADC之后两个通道之间相位差的非线性部分为：For the phase shift model at the sampling point, we adopted the quadratic curve fitting method to carry out the following modeling analysis. With a fixed sampling rate of 96MHz, a fixed time delay T _Δ =2250ps and a limited frequency offset range between 4MHz and 44MHz, the random frequency conversion single spectrum signal is used as the input signal of the sampling system. When the samples are from n=18 and n=20 Measurements are obtained when the frequency region index is shifted, where n=18 covers

(LTE signal), n=20 coverage

(WCDMA signal). To measure the nonlinear part of the phase difference between the two channels after the ADC is:

At the same time, five different positions are designed and tested to obtain data samples; the nonlinear error coefficient of the clock delay can be calculated by performing quadratic curve fitting on the measurement function. Figure 3 shows the modeling results of the nonlinear phase difference in the above two cases. The star-shaped points represent the test value. When n=18, the nonlinear phase difference is expressed as:

At this point, the total phase description can be obtained as follows:

In the phase adjustment filtering algorithm of this embodiment, the above-mentioned phase shift can be considered as not only introducing the adjustable delay T _Δ of the clock generator, but also by combining the modeling method of quadratic fitting of the main factors, the fixed part of the clock jitter is The random variation with frequency is reflected in the overall phase, that is, the linear phase error offset obtained by the model is used as one of the input parameters of the phase adjustment filtering algorithm.

(LTE信号)，n＝20覆盖

(WCDMA信号)。频偏为4MHz，14MHz，24MHz，34MHz和44MHz。图4实线部分展示了对总体相位差建模的结果。从图5可以看出，二次拟合的残留误差保持在0.15°以下，满足了性能分析部分的相位差要求。Next, we further verify that the above modeling is accurate. The star-shaped points in Figure 4 show the random test values obtained from the BPS platform. In this test, the sampling frequency f _s =96 MHz and the clock delay T _Δ =2250 ps are still chosen. Measurements are obtained when samples are shifted from frequency region indices of n=18 and n=20, where n=18 covers

(LTE signal), n=20 coverage

(WCDMA signal). The frequency offsets are 4MHz, 14MHz, 24MHz, 34MHz and 44MHz. The solid line in Figure 4 shows the results of modeling the overall phase difference. It can be seen from Figure 5 that the residual error of the quadratic fitting is kept below 0.15°, which meets the phase difference requirement in the performance analysis section.

在上述建模过程中得到可靠的精确值之后，将

作为硬件误差补偿，一起送入后续相位调整滤波算法运算部分，实现了对于非线性相位误差的补偿。2. For the part that varies with frequency in clock jitter

After obtaining reliable and accurate values in the modeling process described above, the

As hardware error compensation, it is sent to the operation part of the subsequent phase adjustment filtering algorithm to realize the compensation of nonlinear phase error.

也就是此处相位差参数包含时钟抖动固定部分造成的相位差，以及在ADC-B中利用时钟信号发生器人为引入的可调延时产生的相位差。如图6所示，根据相位调整滤波算法设计三个滤波单元S_A(f)、

和

将其布置在FPGA当中体现为数字滤波器，使得两路采样后的信号以图6所示的方法经过滤波系统，由于可知相位差的存在而消除混叠，达到无混叠接受信号的目的。Use the existing phase adjustment filtering algorithm to compensate the fixed part of the clock jitter: Assume that the two signals with aliasing obtained by sampling are R ₀ (f) and R ₁ (f) respectively, and B is the bandwidth of the signal to be sampled. The phase difference between the two signals is

That is, the phase difference parameter here includes the phase difference caused by the fixed part of the clock jitter and the phase difference caused by the adjustable delay artificially introduced by the clock signal generator in ADC-B. As shown in Figure 6, according to the phase adjustment filtering algorithm, three filtering units S _A (f),

and

It is arranged in the FPGA and embodied as a digital filter, so that the two-channel sampled signals pass through the filtering system in the method shown in Figure 6, and the aliasing is eliminated due to the existence of the known phase difference, so as to achieve the purpose of receiving signals without aliasing.

The above is only the preferred embodiment of the present invention, it should be pointed out that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can also be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims (2)

1. A second-order band-pass sampling system clock jitter modeling method is characterized by comprising the following steps:

(1) two samples in a second order bandpass sampling systemIntroducing time delay T between channels_Δ；

(2) Establishing a phase difference model containing clock jitter influence:

wherein, theta_real(f) Representing the phase difference between two sampling signals of a second-order band-pass sampling system under the influence of clock jitter, T_cIndicating a clock delay error, i.e. a fixed delay in the clock jitter,

representing the actual delay in the sampled phase difference; f denotes the frequency of the signal input to the second order bandpass sampling system, f_sWhich is indicative of the sampling frequency, is,

g (f) represents the linear phase generated by the group delay,

represents the nonlinear phase introduced by the sampling system hardware, namely the part of clock jitter which changes with the frequency;

(3) fixed sampling frequency, fixed time delay T_ΔLimiting a frequency offset range, sampling by using a random frequency conversion single-spectrum signal as an input signal of a second-order band-pass sampling system, selecting a frequency area index according to the frequency offset range, measuring two paths of output signals of the second-order band-pass sampling system when an output result of the system is offset from the frequency area index, and calculating a phase difference; selecting multiple different frequency region indexes to perform multiple measurements to obtain multiple phase difference values, and measuring the phase difference valuesThe obtained phase difference value is subjected to quadratic curve fitting to obtain a nonlinear error coefficient, namely h, of clock delay₁～h₃To further obtain the nonlinear phase

(4) Will be provided with

And substituting the phase difference model to complete the clock jitter modeling of the second-order band-pass sampling system.

2. A second-order band-pass sampling system clock jitter compensation method is characterized by comprising the following steps:

(1) determining the frequency f of the signal to be sampled, the non-linear phase calculated according to claim 1

Is determined by the calculation formula

A value of (d);

(2) get

As a compensation value of the nonlinear phase error, performing hardware error compensation on the signal sampled by the second-order band-pass sampling system;

(3) the fixed part of the clock jitter is compensated by a phase adjustment filtering algorithm:

recording two paths of sampling signals R processed in the step (2)₀(f) And R₁(f) Has a phase difference of beta_nAt this time, β_nContaining only fixed parts of clock jitter, i.e.

Design three filter units S_A(f)、

And

(4)R₀(f) through S_A(f) Filtered and R₁(f) Through

Adding the filtered results to obtain an output signal; r₀(f) Through S_A(f) Filtered and R₁(f) Through

And adding the filtered results to obtain another output signal.

Images