CN111865741B

CN111865741B - Data transmission method and data transmission system

Info

Publication number: CN111865741B
Application number: CN201910333408.3A
Authority: CN
Inventors: 朱世强; 林嘉宏; 黄振庭; 翁而咨
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-04-24
Filing date: 2019-04-24
Publication date: 2022-03-01
Anticipated expiration: 2039-04-24
Also published as: CN111865741A

Abstract

A data transmission method and a data transmission system, the data transmission method is applicable to a data transmission system including a host and peripheral devices, comprising the following steps: setting a plurality of identification numbers by a processor of the host to at least one packet stored in the host ; transmit at least one packet from the host to the peripheral device via the transmission medium; assign at least one packet to a plurality of temporary storages in the memory of the peripheral device corresponding to the plurality of identification numbers by the processor of the peripheral device according to the plurality of identification numbers of the at least one packet storage blocks, wherein at least two of the multiple temporary storage blocks have different thresholds; and when one of the multiple temporary storage blocks reaches the threshold value of the multiple temporary storage blocks At least one packet of the portion stored by the one of the plurality of temporary storage blocks is transmitted via the I/O interface.

Description

Data transmission method and data transmission system

Technical Field

The present disclosure relates to a data transmission method and a data transmission system, and more particularly, to a data transmission method and a data transmission system of a Universal Serial Bus (USB).

Background

In a data transfer system, when data in a memory of a main system memory is transferred to a memory of a peripheral device through a Universal Serial Bus (USB), an aggregation (aggregation) technique is used to reduce the number of transfers. However, if data having a high priority is processed in the order of arrangement, the delay time is significantly increased. However, if the aggregation technique is not used, the utilization rate of the central processing unit is increased.

Therefore, how to preferentially process the data with high priority through the streaming mode without increasing the utilization rate of the central processing unit, so as to improve the data delay time, is one of the problems to be improved in the field.

Disclosure of Invention

One aspect of the present disclosure is to provide a data transmission method, which is suitable for a data transmission system. The data transmission system comprises a host and a peripheral device. The data transmission method comprises the following steps: setting at least one identification number for at least one packet stored in the host by a processor of the host; transmitting at least one packet from the host to the peripheral device via the transmission medium; distributing at least one packet to a plurality of temporary storage blocks of a memory of the peripheral device corresponding to at least one identification number by a processor of the peripheral device according to the at least one identification number of the at least one packet, wherein the plurality of temporary storage blocks respectively comprise thresholds, and the respective thresholds of at least two of the plurality of temporary storage blocks are different; and when one of the plurality of temporary storage blocks reaches the threshold value of the one of the plurality of temporary storage blocks, transmitting at least one packet of the part stored by the one of the plurality of temporary storage blocks through the input/output interface.

Another aspect of the present disclosure is to provide a data transmission system including a host and a peripheral device. The host includes a memory and a processor. The memory is used for storing at least one packet. The processor is used for setting at least one identification number to at least one packet and transmitting the at least one packet through a transmission medium. The peripheral device is connected with the host through a transmission medium and is used for receiving at least one packet. The peripheral device comprises a memory and a processor. The memory comprises a plurality of temporary storage blocks. The plurality of temporary storage blocks respectively comprise threshold values, and the threshold values of at least two temporary storage blocks in the plurality of temporary storage blocks are different. The processor is used for distributing at least one packet to a plurality of temporary storage blocks corresponding to at least one identification number according to at least one identification number of at least one packet, and transmitting at least one packet of a part stored in one of the plurality of temporary storage blocks through the input/output interface when one of the plurality of temporary storage blocks reaches a threshold value of the one of the plurality of temporary storage blocks.

Therefore, according to the technical solution of the present disclosure, embodiments of the present disclosure provide a data transmission method and a data transmission system, and particularly, to a data transmission method and a data transmission system of a usb, so that data with high priority is preferentially processed in a streaming mode without increasing the utilization rate of a central processing unit, thereby improving data delay time.

Drawings

In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description of the preferred embodiments of the invention in which:

FIG. 1 is a schematic diagram of a data transmission system shown in accordance with some embodiments of the present disclosure;

FIG. 2 is a schematic diagram illustrating a data transmission method of the present invention, according to some embodiments of the present disclosure; and

fig. 3 is a flow chart illustrating a method of data transmission in accordance with some embodiments of the present disclosure.

Description of the symbols

100: data transmission system

110: main unit

150: peripheral device

112. 152: memory device

114. 154: processor with a memory having a plurality of memory cells

116. 156: multiplexing circuit

158: input/output interface

152-1 to 152-N: temporary storage block

170: transmission medium

P1 to PN: sealing bag

S1 to SN: identification number

300: data transmission method

S310 to S360: step (ii) of

Detailed Description

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. Elements and configurations in the specific illustrations are used in the following discussion to simplify the present disclosure. Any examples discussed are intended for illustrative purposes only and do not limit the scope or meaning of the invention or its illustrations in any way.

Fig. 1 is a schematic diagram of a data transmission system 100 shown in accordance with some embodiments of the present disclosure. The data transmission system 100 includes a host 110 and a peripheral device 150. The host 110 is connected to the peripheral device 150 via a transmission medium 170. The host 110 includes a memory 112 and a processor 114. The peripheral device 150 includes a memory 152, a processor 154, and an input/output interface 158. The memory 152 includes a plurality of temporary storage blocks 152-1 to 152-N. The register blocks 152-1 to 152-N respectively include threshold values. The data transmission system 100 shown in fig. 1 is only an example, but the disclosure is not limited thereto.

In the embodiment of the present disclosure, the

memories

112 and 152 are First In First Out (FIFO) memories. However, the embodiments of the present invention are not limited thereto. In some embodiments, the transmission medium 170 may be a Universal Serial Bus (USB) transmission line or a USB interface transmission circuit. In some embodiments, the peripheral device 150 may be a wired network card or a wireless network card, but the embodiments of the invention are not limited thereto. In some embodiments, the transmission medium 170 is USB3.0 standard.

In the connection relationship, the host 110 and the peripheral device 150 are connected via the transmission medium 170. The memory 112 is coupled to the processor 114. The memory 152 is coupled to the processor 154, and the processor 154 is coupled to the input/output interface 158.

In an operational relationship, the memory 112 of the host 110 is used for storing at least one packet. When the host 110 transmits at least one packet to the peripheral device 150, the processor 114 of the host 110 sets an identification number (Stream ID) for each packet. In detail, the processor 114 determines a priority of each of the at least one packet, and sets at least one identification number (StreamID) for each packet according to the priority of each of the at least one packet. Then, the processor 114 of the host 110 transmits at least one packet to the peripheral device 150 via the transmission medium 170.

After the peripheral device 150 receives at least one packet transmitted by the host 110, the processor 154 of the peripheral device 150 allocates at least one packet to the temporary blocks 152-1 to 152-N corresponding to the identification number according to the respective identification number of the at least one packet. When one of the temporary blocks 152-1 to 152-N reaches a threshold, the processor 154 executes a packet transfer procedure via the i/o interface 158 to transfer the packet buffered in one of the temporary blocks 152-1 to 152-N to another device via Ethernet (Ethernet) or other wired/wireless transmission methods. In another embodiment, the packet forwarding procedure is performed by the processor 114 on the host side.

In some embodiments, the threshold value of each of the register blocks 152-1 to 152-N is set by the processor 114 as described above. The threshold may be the number of packets or the storage capacity, but the disclosure is not limited thereto. In another embodiment, the threshold of each of the temporary blocks 152-1 to 152-N is set by the processor 154 of the peripheral device 150.

In detail, please refer to fig. 1 and fig. 2 together. Fig. 2 is a schematic diagram illustrating a data transmission method according to the present invention, according to some embodiments of the present disclosure. The packets P1-PN are packets transmitted from the host 110 of fig. 1 to the peripheral device 150 of fig. 1. The temporary blocks 152-1 to 152-N illustrated in fig. 2 include different lengths to represent different threshold values.

As shown in FIG. 2, packets P1-PN each include one of the ID numbers S1-SN set by the host 110. For example, the processor 114 of the host 110 sets the identification number of the packet P1 to S1, the identification number of the packet P2 to S2, the identification number of the packet P3 to S1, and the identification number of the packet PN to SN. Then, the host 110 transmits the packet P1 to the PN to the peripheral device 150 by Bulk Out Transfer (Bulk Out Transfer).

After peripheral device 150 receives packets P1 through PN, processor 154 stores packets P1 through PN to buffer blocks 152-1 through 152-N corresponding to the identification numbers according to the respective identification numbers of packets P1 through PN. For example, since packet P1 has an id number of S1, processor 154 allocates packet P1 to the temporary block 152-1 corresponding to the id number of S1 for storage; since the identification number of packet P2 is S2, processor 154 allocates packet P2 to the temporary block 152-2 corresponding to identification number S2 for storage; since the identification number of packet P3 is S1, processor 154 allocates packet P3 to the temporary block 152-1 corresponding to identification number S1 for storage; since the identification number of the packet PN is SN, the processor 154 assigns the packet PN to the temporary block 152-N corresponding to the identification number SN for storage, and so on.

Then, when one of the temporary storage blocks 152-1 to 152-N reaches a threshold, the processor 154 sends out the packet stored in one of the temporary storage blocks 152-1 to 152-N.

In some embodiments, the register block for processing high priority packets includes a smaller threshold for storing high priority packets.

As shown in fig. 2, the threshold of the register block 152-2 is smaller than the thresholds of the other register blocks, i.e. the register block 152-2 is used to store packets with high priority. When the processor 114 in fig. 1 determines that the packet P2 is a high-priority packet, the processor 114 sets the identification number of the packet P2 to S2. Thus, when packet P2 is sent to peripheral device 150, processor 152 stores high priority packet P2 into buffer block 152-2.

Because the buffer block 152-2 has a smaller threshold, the packets stored in the buffer block 152-2 can be sent out faster. For example, assume that the threshold of register block 152-2 is 1 packet. When packet P2 is stored in buffer block 152-2, buffer block 152-2 reaches the threshold, and packet P2 is sent. Compared to the buffer block 152-2, the remaining buffer blocks 152-1, 152-3 to 152-N have larger thresholds, and the packets stored in the remaining buffer blocks 152-1, 152-3 to 152-N are sent out until the respective thresholds of the corresponding buffer blocks 152-1, 152-3 and 152-N are reached.

In some embodiments, the processor 154 of the peripheral device 150 frees up one of the buffer blocks 152-1 to 152-N when the packet stored in one of the buffer blocks 152-1 to 152-N is completely sent out. For example, after the processor 154 sends the packet of the temporary block 152-2 out through the input/output interface 158, the processor 154 frees up the temporary block 152-2. Thus, the remaining packets containing the identification number S2 can be stored in the register block 152-2.

Please refer back to fig. 1. In some embodiments, the processor 114 further comprises a multiplexing circuit 116 for retrieving at least one packet from the memory 112 and setting an identification number for each packet according to the priority of each packet. In some embodiments, the processor 154 further includes a multiplexing circuit 156 for obtaining an identification number of each packet from each packet and allocating at least one packet to a corresponding register block according to the identification number.

As described above, in the embodiments of the present disclosure, different thresholds are set in each temporary block of the peripheral device, and an identification number is set for each packet. Therefore, the data with high priority can be stored in the temporary storage block with lower threshold value without increasing the utilization rate of the central processing unit, so as to be processed preferentially in the streaming mode, and further improve the data delay time.

Please refer to fig. 3. Fig. 3 is a data transmission method 300, shown in accordance with some embodiments of the present disclosure. As shown in fig. 3, the data transmission method 300 includes steps S310 to S360. To make the data transmission method 300 of the present embodiment easy to understand, please refer to fig. 1 to fig. 3 together.

Step S310: setting at least one identification number to at least one packet stored in the host. In some embodiments, step S310 may be performed by the processor 114 shown in fig. 1. For example, the multiplexing circuit 116 of the processor 114 retrieves at least one packet from the memory 112 and sets an identification number for each packet according to the priority of each packet. Each identification number corresponds to a temporary block 152-1 to 152-N, respectively, as shown in fig. 1.

Step S320: setting respective threshold values of a plurality of temporary storage blocks of the peripheral device. In some embodiments, step S320 may be performed by the processor 114 or the processor 154 shown in fig. 1. For example, the processor 114 sets different thresholds for each of the register blocks 152-1 to 152-N. The threshold may be the number of packets or the storage capacity. In some embodiments, the register block for storing and processing high priority packets includes a smaller threshold.

Step S330: at least one packet is transmitted from the host to the peripheral device. In some embodiments, step S330 may be performed by the processor 114 shown in fig. 1. For example, the processor 114 may transmit at least one packet to the peripheral device 150 via the transmission medium 170. In some embodiments, at least one packet is transmitted in a Bulk Out Transfer (Bulk Out Transfer) manner.

Step S340: whether one of the plurality of temporary storage blocks reaches a threshold value is judged. If it is determined that one of the plurality of temporary blocks reaches the threshold value, step S350 is performed. If it is determined that one of the plurality of temporary blocks does not reach the threshold value, step S330 is executed to continue transmitting at least one packet from the host to the peripheral device.

In some embodiments, step S340 may be performed by the processor 154 shown in fig. 1. For example, please refer to fig. 2. If the threshold value of the register block 152-2 is 1024 bytes (Byte). Assume that when packet P3, each having a size of 1024 bytes, is stored in register block 152-2, register block 152-2 is determined to have reached the threshold. On the other hand, if the threshold of the register block 152-1 is 10240 bytes, when the register block 152-1 only stores the packets P1 and P3 with sizes of 1024 bytes, it is determined that the register block 152-1 has not reached the threshold.

Step S350: sending out the packet stored in one of the plurality of temporary blocks. In some embodiments, step S350 may be performed by the processor 154 via the input/output interface 158 as shown in fig. 1. For example, if the buffer block 152-2 reaches the threshold, the processor 154 sends at least one packet stored in the buffer block 152-2 through the input/output interface 158 via the input/output interface 158.

Step S360: releasing space of one of the plurality of temporary storage blocks. In some embodiments, S360 may be performed by the processor 154 as shown in fig. 1. For example, if at least one packet stored in the buffer 152-2 has been sent from the i/o interface 158, the processor 154 frees the buffer 152-2 so that the remaining packets containing the identification number S2 can be stored in the buffer 152-2. In some embodiments, as shown in fig. 3, after releasing the space of one of the temporary blocks, the process returns to step S340 to continuously determine whether the one of the temporary blocks reaches the threshold value.

In some embodiments, the

processors

114, 154 may be a server, a circuit, a Central Processing Unit (CPU), a Microprocessor (MCU) or other equivalent devices with functions of storing, calculating, reading data, receiving signals or information, transmitting signals or information, etc.

In some embodiments, the

memory

112, 152 may be implemented as a read-only memory, a flash memory, a floppy disk, a hard disk, an optical disk, a U-disk, a magnetic tape, a database accessible by a network, or a storage device with the same function as those of the memory, which can be easily realized by those skilled in the art.

In view of the foregoing, embodiments of the present disclosure provide a data transmission method and a data transmission system, and in particular, to a data transmission method and a data transmission system of a usb, so that data with high priority is preferentially processed in a streaming mode without increasing the utilization rate of a central processing unit, thereby improving data delay time.

Additionally, the above illustration includes exemplary steps in sequential order, but the steps need not be performed in the order shown. It is within the contemplation of the disclosure that the steps may be performed in a different order. Steps may be added, substituted, changed in order, and/or omitted as appropriate within the spirit and scope of embodiments of the disclosure.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims

1. A data transmission method is suitable for a data transmission system, wherein the data transmission system comprises a host and a peripheral device, and the data transmission method comprises the following steps:

setting at least one identification number for at least one packet stored in the host by a processor of the host;

transmitting the at least one packet from the host to the peripheral device via a transmission medium;

distributing, by a processor of the peripheral device, the at least one packet to a plurality of temporary storage blocks of a memory of the peripheral device corresponding to the at least one identification number according to the at least one identification number of the at least one packet, wherein the plurality of temporary storage blocks respectively include a threshold, and respective thresholds of at least two of the plurality of temporary storage blocks are different, wherein the temporary storage block for storing the high-priority packet includes a smaller threshold; and

when one of the plurality of temporary storage blocks reaches the threshold value of the one of the plurality of temporary storage blocks, transmitting a part of the at least one packet stored in the one of the plurality of temporary storage blocks through an input/output interface.

2. The data transmission method of claim 1, comprising:

setting respective thresholds of the plurality of temporary storage blocks of the peripheral device, wherein the thresholds comprise a packet number or a storage capacity; and

determining, by the processor of the host, a priority of each of the at least one packet.

3. The data transmission method of claim 1, further comprising:

setting the at least one identification number for the at least one packet according to a priority of the at least one packet, wherein the plurality of temporary storage blocks comprise a first temporary storage block and a second temporary storage block, the threshold value of the first temporary storage block is smaller than the threshold value of the second temporary storage block, and the first temporary storage block corresponds to a first identification number in the at least one identification number;

setting a minimum threshold value for the first temporary storage block; and

when the priority of a first packet in the at least one packet is high, the first identification number is set to the first packet.

4. The data transmission method of claim 1, further comprising:

when the at least one packet stored in the temporary storage block is completely sent out, releasing the space of the temporary storage block.

5. The data transmission method of claim 1, further comprising:

obtaining one of the at least one packet from a memory of the host by a multiplexing circuit of the host, and setting one of the at least one identification number to the one of the at least one packet according to a priority of the one of the at least one packet.

6. A data transmission system, comprising:

a host, comprising:

a memory for storing at least one packet; and

a processor for setting at least one identification number for the at least one packet and transmitting the at least one packet via a transmission medium; and

a peripheral device connected to the host via the transmission medium for receiving the at least one packet, wherein the peripheral device comprises:

a memory, comprising a plurality of temporary storage blocks, wherein the plurality of temporary storage blocks respectively comprise a threshold value, the threshold values of at least two temporary storage blocks in the plurality of temporary storage blocks are different, and the temporary storage block for storing the high-priority packet comprises a smaller threshold value; and

a processor for allocating the at least one packet to the plurality of temporary blocks corresponding to the at least one identification number according to the at least one identification number of the at least one packet, and transmitting a portion of the at least one packet stored in one of the plurality of temporary blocks through an input/output interface when the one of the plurality of temporary blocks reaches the threshold of the one of the plurality of temporary blocks.

7. The data transmission system according to claim 6, wherein the processor of the host is further configured to set the threshold for each of the plurality of temporary blocks, wherein the threshold comprises a number of packets or a storage capacity, and wherein the processor of the host is further configured to determine a priority for each of the at least one packet.

8. The data transmission system according to claim 6, wherein the processor of the host is further configured to set the at least one identification number for the at least one packet according to a priority of each of the at least one packet, wherein the plurality of temporary blocks includes a first temporary block and a second temporary block, the threshold of the first temporary block is smaller than the threshold of the second temporary block, wherein the first temporary block corresponds to a first identification number of the at least one identification number, wherein when a priority of a first packet of the at least one packet is high, a minimum threshold is set for the first temporary block, and the first identification number is set for the first packet.

9. The data transmission system according to claim 6, wherein the space of the one of the plurality of temporary blocks is released when the at least one packet of the portion stored in the one of the plurality of temporary blocks is completely sent out.

10. The data transmission system of claim 6, wherein the processor of the host comprises:

a multiplexing circuit for obtaining one of the at least one packet from the memory of the host and setting one of the at least one identification number to the one of the at least one packet according to a priority of the one of the at least one packet.