CN111864059A - Preparation method of storage bit and preparation method of MRAM - Google Patents

Abstract

The present invention provides a method for preparing storage bits and a method for preparing MRAM. The preparation method includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps: performing gas passivation treatment on the sidewall of the magnetic tunnel junction to reduce dangling bonds on the surface of the sidewall. Through the above-mentioned gas passivation treatment, the present invention can not only reduce dangling bonds on the sidewall surface, but also remove surface impurities and fill the vacancies in the surface layer and the surface, thereby reducing defect density, improving device stability, and alleviating etching damage The influence on TMR and other performance parameters can reduce the TMR loss rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field.

Description

Preparation method of storage bit and preparation method of MRAM

technical field

The invention relates to the field of semiconductor memory chip manufacturing, and in particular, to a method for preparing storage bits and a method for preparing MRAM.

Background technique

Memory chips are an important part of a computer, affecting the speed, integration, and power consumption of the entire computer. Inside the current computer, the memory is divided into two parts, the hard disk and the cache. The hard disk has a large capacity, and the data is not lost when the power is turned off, but the speed is slow. Even the more advanced solid state drives, NAND Flash, cannot be avoided. The cache speed is fast, such as DRAM and SRAM, but the capacity is small, and the data is lost when the power is turned off. With the gradual reduction of chip feature size, NAND, DRAM and SRAM face a series of insurmountable difficulties such as high power consumption and large area.

MRAM is currently the most potential next-generation memory chip. It brings together the high integration characteristics of DRAM, the high-speed characteristics of SRAM, and the non-volatility of Flash. In theory, it has the ability to read and write infinite times and has low power consumption. At present, the world's leading semiconductor companies have started trial production or mass production of MRAM.

Tunnel junction etching is one of the two major challenges in MRAM fabrication. The tunnel junction is the core device layer of MRAM. It consists of more than a dozen metals stacked into a film structure of dozens of layers. The thinnest layer is only a few angstroms thick. It is the carrier of data preservation. The task of tunnel junction etching is to etch the continuous tunnel junction film into discrete bits. There are two major difficulties in tunnel junction etching: short circuits and damage. Etching residues tend to adhere to the sidewalls of the bit cells, causing short circuits in the device. Secondly, the reactants in the etching process will cause damage to the surface layer of the device, thereby reducing the performance of the device; the halogen gas in the reactive ion etching will continuously penetrate into the device, causing the magnetic properties of the bit element to be damaged. Ion beam etching will destroy the lattice structure on the surface of the bit element, forming a damaged layer on the surface, which will also cause magnetic damage. These damages cannot be completely eliminated, but can only be gradually controlled and reduced.

In order to solve the short-circuit problem, a commonly adopted measure is to increase the etching dose. This further leads to aggravation of the magnetic damage phenomenon. In general, the TMR loss rate caused by magnetic damage reaches 20-30%.

The magnetic damage caused by tunnel junction etching severely restricts the yield of MRAM and limits its further development.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide a method for preparing storage bits and a method for preparing MRAM, so as to solve the problem of serious magnetic damage caused by tunnel junction etching in the prior art.

In order to achieve the above object, according to one aspect of the present invention, there is provided a method for preparing a storage bit cell, including the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps: The sidewalls of the junction are gas passivated to reduce dangling bonds on the sidewall surfaces.

Further, the step of forming the tunnel junction includes: sequentially forming a tunnel junction material layer and a first mask material layer on the bottom electrode; patterning the first mask material layer to form a first mask layer; The film layer etches the tunnel junction material layer to form a magnetic tunnel junction.

Further, ion beam etching is performed on the tunnel junction material layer to form a magnetic tunnel junction, preferably using an inert gas to perform ion beam etching.

Further, reactive ion etching is carried out to the tunnel junction material layer to form a magnetic tunnel junction, preferably the plasma source of reactive ion etching is selected from any one of capacitive coupling source, inductive coupling source and electron cyclotron resonance source, preferably The reactive gas for reactive ion etching is a fluorine-based gas and/or a chlorine-based gas.

Further, gas passivation treatment is performed on the magnetic tunnel junction with a passivation gas including a passivation gas, preferably the passivation gas is selected from any one or more of hydrogen, deuterium, ammonia and deuterated ammonia.

Further, the passivation gas also includes a carrier gas, preferably any one or more of the carrier gas helium, neon, argon, xenon and nitrogen.

Further, the magnetic tunnel junction is subjected to gas passivation treatment by using plasma formed by passivation gas, preferably the power of the plasma is 10-200W, the flow rate of the passivation gas is preferably 10-500sccm, and the pressure of the plasma is preferably 1～200W. 50 Torr, preferably the temperature of the gas passivation treatment is 20-300°C, and the preferably time of the gas passivation treatment is 10-500s.

Further, after the step of performing gas passivation treatment on the magnetic tunnel junction, the preparation method further includes the following step: forming an encapsulation layer covering the tunnel junction and the first mask layer on the bottom electrode.

Further, an insulating dielectric material is deposited on the bottom electrode to form an encapsulation layer, preferably the insulating dielectric material is selected from any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide Or more, preferably chemical vapor deposition or atomic layer deposition is used to form the encapsulation layer.

Further, the thickness of the encapsulation layer is 5-50 nm. Preferably, in the process of depositing the insulating dielectric material, or after depositing the insulating dielectric material, the preparation method further includes the step of performing gas passivation treatment on the surface of the insulating dielectric material.

According to another aspect of the present invention, a method for preparing an MRAM is provided, including the step of forming at least one storage bit, wherein the storage bit is formed by using the above-mentioned preparation method.

By applying the technical solution of the present invention, a method for preparing a storage bit is provided, which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method performs gas passivation treatment on the sidewall of the magnetic tunnel junction , to reduce dangling keys on the sidewall surface. No matter what etching method is adopted, a large number of high-energy particles will irradiate the tunnel junction during etching, resulting in the etched tunnel junction not only with uneven surface and large specific surface area, but also with disordered surface lattice, dislocations, impurities, The vacancy density is high, the magnetic anisotropy in the surface area is not strong, and multi-domain inversion is prone to occur, which affects the performance and stability of the device. Through the above-mentioned gas passivation treatment, the present invention can not only reduce dangling bonds on the sidewall surface, but also remove surface impurities and fill the vacancies in the surface layer and the surface, thereby reducing defect density, improving device stability, and alleviating etching damage The influence on TMR and other performance parameters can reduce the TMR loss rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field.

Description of drawings

The accompanying drawings forming a part of the present invention are used to provide further understanding of the present invention, and the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached image:

FIG. 1 shows that in the method for preparing a storage bit provided by the embodiment of the present application, a tunnel junction material, a first mask layer material, a second mask material layer and a patterned photoresist are sequentially formed on the bottom electrode Schematic diagram of the cross-sectional structure of the rear substrate;

FIG. 2 shows a schematic cross-sectional structure diagram of the substrate after the second mask material layer and the first mask material layer shown in FIG. 1 are sequentially formed into the second mask layer and the first mask layer;

FIG. 3 shows a schematic diagram of the cross-sectional structure of the substrate after etching the tunnel junction material layer with the first mask layer and the second mask layer shown in FIG. 2 as masks;

FIG. 4 shows a schematic cross-sectional structure diagram of the substrate after gas passivation treatment is performed on the sidewall of the magnetic tunnel junction shown in FIG. 3;

FIG. 5 shows a schematic cross-sectional structure diagram of the substrate after forming the encapsulation layer covering the tunnel junction and the first mask layer shown in FIG. 4 .

Wherein, the above-mentioned drawings include the following reference signs:

100, insulating medium layer; 10, connecting metal layer; 20, bottom electrode; 30, magnetic tunnel junction; 301, tunnel junction material layer; 310, reference layer; 311, reference material layer; 320, barrier layer; 321, potential barrier material layer; 330, free layer; 331, free material layer; 40, first mask layer; 410, first mask material layer; 50, second mask layer; 510, second mask material layer; 60 , photoresist; 70, encapsulation layer.

Detailed ways

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

As described in the background art, the preparation process of the storage bit in the prior art easily leads to the magnetic damage of the device. In order to solve the above-mentioned technical problem, the applicant of the present invention provides a method for preparing a storage bit cell, which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps: The sidewalls of the junction are gas passivated to reduce dangling bonds on the sidewall surfaces.

No matter what etching method is adopted, a large number of high-energy particles will irradiate the tunnel junction during etching, resulting in the etched tunnel junction not only with uneven surface and large specific surface area, but also with disordered surface lattice, dislocations, impurities, The vacancy density is high, the magnetic anisotropy in the surface area is not strong, and multi-domain inversion is prone to occur, which affects the performance and stability of the device. Through the above-mentioned gas passivation treatment, the present invention can not only reduce dangling bonds on the sidewall surface, but also remove surface impurities and fill the vacancies in the surface layer and the surface, thereby reducing defect density, improving device stability, and alleviating etching damage The influence on TMR and other performance parameters can reduce the TMR loss rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field.

Exemplary embodiments of the method for preparing a storage bit provided according to the present invention will be described in more detail below with reference to FIGS. 1 to 5 . These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.

First, the magnetic tunnel junction 30 is formed. The step of forming the magnetic tunnel junction 30 may include: sequentially forming a tunnel junction material layer 301 and a first mask material layer 410 on the bottom electrode 20 , and the bottom electrode 20 may be formed on the surface of the connection metal layer 10 in the insulating medium layer 100 , as shown in FIG. 1; the first mask material layer 410 is patterned to form the first mask layer 40, as shown in FIG. 2 and FIG. 3; Etching to form the magnetic tunnel junction 30, as shown in FIG. 4, the etching stays on the surface of the bottom electrode 20 or below the surface of the bottom electrode 20, so as to achieve complete conductive separation between the storage bits, the magnetic tunnel junction 30 can be etched The first mask layer 40 after the etching process serves as the top electrode of the storage bit cell.

The thickness of the magnetic tunnel junction 30 can be 5-50 nm, and those skilled in the art can reasonably select the materials of each layer in the tunnel junction material layer 301 according to the type of the magnetic tunnel junction 30 (MTJ) actually required. The above-mentioned magnetic tunnel junction 30 can have various forms according to the application, including but not limited to in-plane MTJ, vertical MTJ, top-pinned MTJ, bottom-pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ and multi-state MTJ.

In one embodiment, a reference material layer 311 , a barrier material layer 321 and a free material layer 331 are sequentially deposited on the bottom electrode 20 , and a magnetic tunnel including the reference layer 310 , the barrier layer 320 and the free layer 330 is obtained after etching junction 30, as shown in FIGS. 1-3.

In the above embodiment, data is stored by the spin direction of the free layer 330, and the barrier layer 320 in the magnetic tunnel junction 30 can also be the first barrier layer, and a second barrier layer, a pinning layer, a capping layer can be added. The material for forming the reference layer 310 may include magnetic metals such as cobalt iron boron, and the material for forming the barrier layer 320 may be a dielectric material such as magnesium oxide or aluminum oxide.

In a preferred embodiment, the steps of forming the above-mentioned first mask layer 40 and the above-mentioned second mask layer 50 include: depositing and forming a second mask material layer 510 on the first mask material layer 410, and forming a second mask material layer 510 on the first mask material layer 410 The photoresist 60 is covered on the second mask material layer 510, and the photoresist 60 is patterned by photolithography and developing processes, as shown in FIG. layer 510 and etching the first masking material layer 410 to transfer the pattern of the patterned photoresist 60 to obtain the second masking layer 50 and the first masking layer 40 , as shown in FIG. 2 .

In the above-mentioned preferred embodiment, those skilled in the art can reasonably select the above-mentioned first mask layer 40 material and mask material according to the prior art, for example, the above-mentioned first mask layer 40 material can be Ta, TaN, TiN and other materials, the above-mentioned mask material can be SiO _x , SiN _x and other materials; those skilled in the art can also reasonably set the process conditions of the above-mentioned lithography process according to the prior art, which will not be repeated here.

Preferably, ion beam etching is performed on the tunnel junction material layer 301 to form the above-mentioned magnetic tunnel junction 30 , as shown in FIG. 3 . Ion beam etching uses argon or other inert gas plasma, which is accelerated by an electric field and incident on the surface of the structure to perform physical etching of the tunnel junction. Using the ion beam etching process (IBE) can avoid the damage to the electromagnetic properties of the magnetic tunnel junction 30 (MTJ) caused by chemical corrosion caused by the reactive ion etching (RIE) process in the prior art.

In order to avoid the damage of the surface magnetic layer on the sidewalls of the magnetic tunnel junction 30 by the above-mentioned IBE etching, the above-mentioned ion beam etching is carried out using an inert gas. Due to the high cost of xenon gas, argon gas or krypton gas is preferably used as the main gas. Add a certain amount of neon gas. More preferably, the acceleration voltage of the ion beam etching is 50-1600V, and the energy of the ion beam etching is 50-1600eV.

In order to form the above-mentioned magnetic tunnel junction 30, reactive ion etching can also be performed on the above-mentioned tunnel junction material layer 301, and the plasma source of the above-mentioned reactive ion etching can be selected from any one of capacitive coupling source, inductive coupling source and electron cyclotron resonance source. A sort of. In order to avoid the damage of the surface magnetic layer on the sidewall of the magnetic tunnel junction 30 by the above-mentioned IBE etching, preferably, the reactive gas of the above-mentioned reactive ion etching is a fluorine-based gas and/or a chlorine-based gas; and, preferably, the above-mentioned reactive gas The pressure is 1 ~ 50mTorr.

After the step of forming the magnetic tunnel junction 30, a gas passivation process is performed on the sidewall of the magnetic tunnel junction 30 to reduce dangling bonds on the sidewall surface. The above-mentioned gas passivation treatment can not only reduce the dangling bonds on the sidewall surface, but also remove surface impurities and fill the vacancies inside and on the surface layer, thereby reducing defect density, improving device stability, and alleviating the effect of magnetic damage on TMR and other performance parameters. influences.

In the above-mentioned process of performing gas passivation treatment on the sidewall of the magnetic tunnel junction 30, a passivation gas including passivation gas is used to perform gas passivation treatment on the magnetic tunnel junction 30, in order to improve the treatment of surface defects and dangling bonds Effect, preferably, the above-mentioned passivation gas is selected from any one or more of hydrogen, deuterium, ammonia and deuterated ammonia.

The above-mentioned passivation gas can also include a carrier gas. In order to avoid the influence of the reaction between the carrier gas and the magnetic tunnel junction 30, preferably, any one of the above-mentioned carrier gases helium, neon, argon, xenon and nitrogen is used. one or more; preferably, the above-mentioned passivation gas accounts for 1-100% of the molar concentration of the above-mentioned carrier gas.

In order to improve the process efficiency of eliminating defects and dangling bonds on the surface of the magnetic tunnel junction 30, in a preferred embodiment, the magnetic tunnel junction 30 is gas passivated by using the plasma formed by the above passivation gas; more preferably , the power of the above-mentioned plasma is 10-200W, the flow rate of the passivation gas is 10-500sccm, the pressure is 1-50Tor, the temperature of the gas passivation treatment is 20-300°C, and the time is 10-500s.

After the step of performing gas passivation treatment on the sidewall of the shown magnetic tunnel junction 30, and using the first mask layer 40 as the top electrode of the storage bit cell, the above-mentioned preparation method of the present invention may further include the following steps: at the bottom An encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40 is formed on the electrode 20 , as shown in FIG. 5 . The encapsulation layer 70 is used to protect the first mask layer 40 and the magnetic tunnel junction 30 in subsequent processes.

An insulating dielectric material is deposited on the bottom electrode 20 to form the encapsulation layer 70. The encapsulation layer 70 may have a thickness of 5 to 50 nm. When the deposition thickness is less than 50 nm, during the deposition of the insulating dielectric material, or during the deposition After the above-mentioned insulating medium material, preferably, the above-mentioned preparation method of the present invention further includes the step of performing gas passivation treatment on the surface of the insulating medium material. The above passivation treatment can reduce the roughness, defect density and the number of interface dangling bonds of the encapsulation layer 70, thereby reducing the leakage current of the device.

The above-mentioned encapsulation layer 70 is non-conductive and non-magnetic, preferably, the above-mentioned insulating dielectric material is selected from any one or more of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, However, it is not limited to the above-mentioned preferred types, and those skilled in the art can reasonably select the specific types according to the prior art. Those skilled in the art can also reasonably select the process of depositing and forming the encapsulation layer 70 according to the prior art, for example, chemical vapor deposition or atomic layer deposition to form the encapsulation layer.

According to another aspect of the present invention, there is also provided a method for preparing an MRAM, which includes the step of forming at least one storage bit, and the storage bit is formed by the above-mentioned preparation method.

The method for preparing the above-mentioned storage bit provided by the present invention will be further described below with reference to the embodiments.

Example 1

The preparation method of the storage bit provided by this embodiment includes the following steps:

A second mask material layer 510 is deposited on the first mask material layer 410, and the photoresist 60 is covered on the second mask material layer 510. The photoresist 60 is used as a mask to etch the second mask material layer 510 to obtain a second mask layer 50 having a pattern consistent with the photoresist 60, as shown in FIG. 1 and FIG. 2; The mask layer 50 etches the first mask material layer 410 to transfer the pattern of the patterned photoresist 60 to obtain the first mask layer 40;

The tunnel junction material layer 301 is etched through the first mask layer 40 to form the magnetic tunnel junction 30, including the reference layer 310, the barrier layer 320 and the free layer 330, and the etching stays at the bottom electrode 20 and below the bottom electrode 20 , so as to achieve complete conductive separation between storage bits;

The surface of the magnetic tunnel junction 30 is subjected to gas passivation treatment by using the plasma formed by the passivation gas. In the passivation gas, hydrogen is used as the passivation gas, and argon is used as the carrier gas. 8.5Torr, power 75W, temperature 200℃, processing time 180s.

Plasma-enhanced chemical vapor deposition is used to deposit silicon nitride on the bottom electrode 20 to form an encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40. The reactive gases are silane and ammonia, and nitrogen and argon are used as carriers. gas. During deposition, the gas pressure was 8.5 Torr, the power was 75 W, the temperature was 200 °C, and the time was 25 s.

Example 2

The difference between the preparation method of the storage bit provided in this embodiment and Embodiment 1 is:

The flow rate of hydrogen gas was 10 sccm, the flow rate of argon gas was 5000 sccm, the pressure was 1 Torr, the power was 10 W, the temperature was 20 °C, and the processing time was 500 s.

Example 3

The difference between the preparation method of the storage bit provided in this embodiment and Embodiment 1 is:

Ammonia gas was used as passivation gas, argon gas was used as carrier gas, the flow rate of ammonia gas was 500 sccm, the flow rate of argon gas was 5000 sccm, the pressure was 50 Torr, the power was 200 W, the temperature was 300 °C, and the processing time was 10 s.

Example 4

The difference between the preparation method of the storage bit provided in this embodiment and Embodiment 1 is:

In the step of depositing the encapsulation layer, a gas passivation step is introduced: the encapsulation layer is silicon nitride, the reaction device is plasma enhanced chemical vapor deposition, the reaction gases are silane, ammonia, and nitrogen and argon are used as carrier gases. During deposition, the pressure was 8.5 Torr, the power was 75W, the temperature was 200°C, and the time was 5s; then the deposited silicon nitride was subjected to gas passivation treatment, using hydrogen as the passivation gas, argon as the carrier gas, the flow rate of hydrogen was 100sccm, and the argon gas was used as the carrier gas. The flow rate was 5000sccm, the pressure was 8.5 Torr, the power was 75W, the temperature was 200°C, and the treatment time was 30s. After the gas passivation treatment, the silicon nitride was continued to grow under the same process conditions for 20s.

Comparative Example 1

The difference between the preparation method of the storage bit provided by this comparative example and the embodiment 1 is:

After the magnetic tunnel junction 30 is formed, the surface of the magnetic tunnel junction 30 is not subjected to gas passivation treatment, and the encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40 is directly formed.

Combined with the conventional semiconductor manufacturing related processes in the prior art, such as photolithography, etching and other technologies, the storage bits in the above-mentioned embodiments 1 to 4 are prepared into MTJ devices, and then the above-mentioned embodiments 1 to 4 and comparative example 1 are used. The performances such as TMR impairment rate of MTJ devices are tested, and the test results are shown in the following table.

Table 1

It can be seen from the above test results that the gas passivation treatment on the sidewall of the magnetic tunnel junction can effectively reduce the TMR impairment rate, TMR dispersion value, critical magnetic field and critical voltage dispersion value of the MTJ device.

From the above description, it can be seen that the above-mentioned embodiments of the present invention achieve the following technical effects:

1. The above-mentioned gas passivation treatment can not only reduce the dangling bonds on the sidewall surface, but also remove the surface impurities and fill the vacancies in the surface layer and the surface, thereby reducing the defect density, improving the stability of the device, and alleviating the magnetic field. The impact of damage on TMR and other performance parameters can reduce the TMR impairment rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field;

2. By covering the encapsulation layer on the tunnel junction and the first mask layer (top electrode), when a voltage is applied across the tunnel junction, the encapsulation layer bears most of the partial voltage, resulting in a strong local electric field;

3. The gas passivation treatment of the encapsulation layer material can reduce the roughness of the encapsulation layer, the defect density and the number of interface dangling bonds, thereby reducing the leakage current of the device.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (11)

1. A method of fabricating a memory bit cell comprising the step of forming a magnetic tunnel junction, wherein after the step of forming the magnetic tunnel junction, the method further comprises the steps of:

and carrying out gas passivation treatment on the side wall of the magnetic tunnel junction so as to reduce dangling bonds on the surface of the side wall.

2. The method of claim 1, wherein the step of forming the tunnel junction comprises:

sequentially forming a tunnel junction material layer and a first mask material layer on the bottom electrode;

patterning the first mask material layer to form a first mask layer;

and etching the tunnel junction material layer through the first mask layer to form the magnetic tunnel junction.

3. The method of claim 2, wherein the tunnel junction material layer is ion beam etched to form the magnetic tunnel junction, preferably using an inert gas.

4. The method according to claim 2, wherein the tunnel junction material layer is subjected to reactive ion etching to form the magnetic tunnel junction, preferably a plasma source of the reactive ion etching is selected from any one of a capacitive coupling source, an inductive coupling source and an electron cyclotron resonance source, preferably a reactive gas of the reactive ion etching is a fluorine-based gas and/or a chlorine-based gas.

5. The method of claim 1, wherein the magnetic tunnel junction is gas passivated with a passivation gas comprising a passivation gas, preferably the passivation gas is selected from any one or more of hydrogen, deuterium, ammonia, and deuterated ammonia.

6. The method of claim 5, wherein the passivating gas further comprises a carrier gas, preferably any one or more of the carrier gases helium, neon, argon, xenon, and nitrogen.

7. The method according to claim 5, wherein the magnetic tunnel junction is passivated with a gas by using a plasma formed by the passivation gas, preferably the power of the plasma is 10 to 200W, preferably the flow rate of the passivation gas is 10 to 500sccm, preferably the pressure of the plasma is 1to 50Torr, preferably the temperature of the gas passivation is 20 to 300 ℃, and preferably the time of the gas passivation is 10 to 500 s.

8. The manufacturing method according to claim 2, wherein after the step of performing gas passivation treatment on the magnetic tunnel junction, the manufacturing method further comprises the steps of:

and forming a packaging layer covering the tunnel junction and the first mask layer on the bottom electrode.

9. The method according to claim 8, wherein an insulating dielectric material is deposited on the bottom electrode to form the encapsulation layer, preferably the insulating dielectric material is selected from any one or more of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, and the encapsulation layer is preferably formed by chemical vapor deposition or atomic layer deposition.

10. The preparation method according to claim 9, wherein the thickness of the encapsulation layer is 5-50 nm, preferably during or after the deposition of the insulating dielectric material, and the preparation method further comprises a step of performing gas passivation treatment on the surface of the insulating dielectric material.

11. A method of fabricating an MRAM comprising the step of forming at least one memory bit, wherein the memory bit is formed using the method of any of claims 1to 10.

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