CN111858217A - A hierarchical verification method, platform, device and storage medium - Google Patents

Abstract

The invention discloses a hierarchical verification method, platform, equipment and storage medium. The platform includes: an excitation top layer, which is used for: defining top-level incentives, each top-level incentive corresponds to different values of variables of the same enumeration type, and the Different values of variables correspond to different underlying incentives; the underlying incentives are used to: define underlying incentives, each underlying incentive has a different data format, and the different data formats correspond to different buses; the sequence top layer is used to: Store the top-level sequences corresponding to different top-level incentives, and use the top-level sequence to generate the corresponding top-level incentives; the bottom-level sequence is used to: store the bottom-level sequences corresponding to different bottom-level incentives, and determine the top-level incentives generated by the top-level sequence. After the underlying incentive is generated, the underlying incentive is generated using the corresponding underlying sequence. It can be seen that the present application can generate incentives corresponding to the bus protocols of different buses, which greatly improves the reusability of the platform.

Description

A hierarchical verification method, platform, device and storage medium

technical field

The present invention relates to the technical field of UVM, and more particularly, to a hierarchical verification method, platform, device and storage medium.

Background technique

UVM (Universal Verification Methodology, Universal Verification Methodology) is a verification methodology based on SystemVerilog. Using UVM to build a verification platform can enhance the reusability and standardization of tests; in the verification platform built by universal UVM, Both drivers and sequences are parameterized classes. A verification platform often contains only one type of sequence, and one type of sequence can only generate one type of stimulus for the driver to use, but in the test of the chip A variety of different bus protocols are often used, and different sequences need to be used to generate different incentives for different bus protocols. Therefore, the verification platform built by the general UVM cannot generate incentives corresponding to different bus protocols, which can be reused. low sex.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a hierarchical verification method, platform, equipment and storage medium, which integrates different bus types into the same platform through hierarchical design, and can generate incentives corresponding to the bus protocols of different buses, thereby greatly reducing the Improved platform reusability.

In order to achieve the above object, the present invention provides the following technical solutions:

A hierarchical verification platform includes an incentive top layer, an incentive bottom layer, a sequence top layer and a sequence bottom layer; wherein:

The incentive top layer is used for: defining top layer incentives, each of the top layer incentives corresponds to different values of a variable of the same enumeration type, and different values of the variable correspond to different bottom layer incentives;

The incentive bottom layer is used for: defining bottom layer incentives, each of the bottom layer incentives has a different data format, and the different data formats correspond to different buses;

The sequence top layer is used for: storing top-level sequences corresponding to different top-level excitations, and generating corresponding top-level excitations by using the top-level sequences;

The sequence bottom layer is used for: storing the bottom layer sequences corresponding to the different bottom layer incentives respectively, and after determining the bottom layer incentives corresponding to the top layer incentives generated by the sequence top layer, using the corresponding bottom layer sequences to generate the bottom layer incentives.

Preferably, it also includes a driving layer and an overall sequence layer;

The overall sequence layer is used for: acquiring the bottom layer incentives generated by the bottom layer of the sequence, sending the acquired bottom layer incentives to the driver layer, and caching a backup of the acquired bottom layer incentives;

The driver layer is configured to: if the underlying stimulus sent by the total sequence layer is successfully received, send the received underlying stimulus to the device under test; otherwise, instruct the total sequence layer to restore the cached backup of the underlying stimulus to the device under test. sent to the driver layer.

Preferably, the driver layer is further configured to: if the underlying excitation sent by the total sequence layer is successfully received, return information of successful reception to the total sequence layer;

The overall sequence layer is further configured to: delete the cached backup of the underlying incentives if receiving the successful reception information sent by the driver layer.

Preferably, it also includes a monitoring layer, the monitoring layer is used to: count the coverage obtained by the device under test using the received underlying stimulus to achieve the test, and when the coverage does not reach the coverage threshold, indicate that the test is in progress The device performs random testing until the coverage obtained by the device achieving the test in the test reaches the coverage threshold.

Preferably, the monitoring layer is further configured to: output a corresponding alarm if the number of random tests performed by the device in the test reaches the number of times threshold and the coverage obtained by the device in the test by implementing the test does not reach the coverage threshold information.

Preferably, the monitoring layer is further configured to: if the number of random tests performed by the device in the test does not reach the number of times threshold and the coverage obtained by the device in the test by implementing the test reaches the coverage threshold, output corresponding of the test completion information.

Preferably, the hierarchical verification platform is built based on UVM, and both the driver layer and the total sequence layer are encapsulated in the env layer of the hierarchical verification platform.

A hierarchical authentication method that includes:

The top-level sequence is used to generate corresponding top-level incentives; wherein, different top-level sequences correspond to different top-level incentives, and different top-level incentives correspond to different values of the variable of the same enumeration type, and different values of the variable correspond to different bottom-level incentives correspond;

Determine the bottom layer incentive corresponding to the generated top layer incentive, and use the bottom layer sequence corresponding to the bottom layer incentive to generate the bottom layer incentive; wherein, different bottom layer sequences correspond to different bottom layer incentives, and different bottom layer incentives have different Data format, the different data formats correspond to different buses.

A hierarchical verification device includes:

memory for storing computer programs;

The processor is configured to implement the steps of the above-mentioned hierarchical verification method when executing the computer program.

A computer-readable storage medium storing a computer program on the computer-readable storage medium, when the computer program is executed by a processor, implements the steps of the above-mentioned hierarchical verification method.

Embodiments of the present invention provide a hierarchical verification method, platform, device, and storage medium. The platform may include an incentive top layer, an incentive bottom layer, a sequence top layer, and a sequence bottom layer; wherein: the incentive top layer is used for: defining the top incentives, Each of the top-level incentives corresponds to different values of a variable of the same enumeration type, and different values of the variable correspond to different bottom-level incentives; the bottom-level incentives are used to: define bottom-level incentives, and each of the bottom-level incentives has different data formats, and the different data formats correspond to different buses; the sequence top layer is used for: storing the top-level sequences corresponding to the different top-level excitations, and generating corresponding top-level sequences by using the top-level sequences Incentive; the sequence bottom layer is used for: storing the bottom layer sequences corresponding to different bottom layer incentives respectively, and after determining the bottom layer incentives corresponding to the top layer incentives generated by the sequence top layer, using the corresponding bottom layer sequences to generate the bottom layer incentives . In the technical solution provided by this application, the top-level incentives define top-level incentives corresponding to different values of a variable of the same enumeration type, and different values of the variable correspond to different bottom-level incentives, and the bottom-level incentive definitions correspond to the data formats of different buses respectively. Bottom-level incentives, the top-level sequence contains top-level sequences corresponding to different top-level incentives, and the bottom-level sequence contains bottom-level sequences corresponding to different bottom-level incentives, so that when a bus corresponding incentive needs to be generated, the top-level sequence is used to generate the top-level incentive, and the top-level incentive is used. The underlying sequence of the excitation corresponding to the underlying excitation generates the underlying excitation, thereby realizing the generation of the excitation corresponding to the bus. It can be seen that the application integrates different bus types into the same platform through a hierarchical design, and can generate different bus protocols corresponding to the bus. incentives, thereby greatly improving the reusability of the platform.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

FIG. 1 is a schematic structural diagram of a hierarchical verification platform provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Please refer to FIG. 1, which shows a hierarchical verification platform provided by an embodiment of the present invention, which may include an incentive top layer, an incentive bottom layer, a sequence top layer, and a sequence bottom layer; wherein:

The incentive top layer is used to: define the top incentive, each top incentive corresponds to different values of the variable of the same enumeration type, and the different values of the variable correspond to different bottom incentives;

The incentive bottom layer is used to: define the bottom layer incentives, each bottom layer incentive has a different data format, and the different data formats correspond to different buses;

The sequence top layer is used to: store the top-level sequences corresponding to different top-level incentives, and use the top-level sequence to generate the corresponding top-level incentives;

The bottom layer of the sequence is used for: storing the bottom layer sequences corresponding to different bottom layer incentives, and after determining the bottom layer incentives corresponding to the top layer incentives generated by the top layer of the sequence, use the corresponding bottom layer sequences to generate the bottom layer incentives.

A hierarchical verification platform provided by the embodiment of the present application may be a verification platform built based on UVM, and the meanings of incentive (Transaction) and sequence (Sequence) are the same as those of the corresponding concepts in the prior art, and are not repeated here. This application sets up four layers in the hierarchical verification platform, namely, the incentive bottom layer, the incentive top layer, the sequence bottom layer and the sequence top layer; wherein, the incentive top layer is an abstract layer, and an enumeration type variable is defined in the incentive top layer, and the corresponding variable can be Different values (or different names) in the enumeration set of values represent corresponding different underlying incentives, that is, different values of the variable correspond to different underlying incentives, since the generated top-level incentives are actually defined as the top-level incentives Therefore, the essence of the top-level excitation definition variable is to define the top-level excitation; the excitation bottom layer defines data frames or packets of different buses, and sets constraints according to the bus protocols of different buses. The bus can include AMBA bus (Advanced Microcontroller). apb bus (advanced peripheral bus), ahb bus (advanced high-performance bus), asb bus (advanced system bus) and axi bus (high-speed extensible interface), because the data exchange in the physical protocol is based on Frame (abbreviation of data frame) or packet (abbreviation of data packet) as a unit, usually a frame or a packet to define various parameters, the size of each frame or packet is different, a stimulus is actually a frame Or packets, so the bottom layer of incentives to define data frames or packets corresponding to different buses is also the bottom layer incentives to define data formats corresponding to different buses; the top layer of sequences contains corresponding top-level sequences, and different top-level sequences can be used to generate different top-level sequences Incentive; the bottom layer of the sequence contains the corresponding bottom layer sequence, and different bottom layer incentives can be generated by using different bottom layer sequences.

The working process of the hierarchical verification platform in this embodiment of the present application may include: if a bottom-level stimulus corresponding to a certain bus needs to be generated, the top-level stimulus may be generated by using the corresponding top-level sequence in the top-level sequence, and the bottom-level stimulus corresponding to the generated top-level stimulus may be determined. , and then determine the underlying sequence corresponding to the underlying excitation, and use the underlying sequence in the underlying sequence to generate the corresponding underlying excitation, which is the underlying excitation corresponding to a bus.

In the technical solution provided by this application, the top-level incentives define top-level incentives corresponding to different values of a variable of the same enumeration type, and different values of the variable correspond to different bottom-level incentives, and the bottom-level incentive definitions correspond to the data formats of different buses respectively. Bottom-level incentives, the top-level sequence contains top-level sequences corresponding to different top-level incentives, and the bottom-level sequence contains bottom-level sequences corresponding to different bottom-level incentives, so that when a bus corresponding incentive needs to be generated, the top-level sequence is used to generate the top-level incentive, and the top-level incentive is used. The underlying sequence of the excitation corresponding to the underlying excitation generates the underlying excitation, thereby realizing the generation of the excitation corresponding to the bus. It can be seen that the application integrates different bus types into the same platform through a hierarchical design, and can generate different bus protocols corresponding to the bus. incentives, thereby greatly improving the reusability of the platform.

The hierarchical verification platform provided by the embodiment of the present invention may further include a driver layer and an overall sequence layer;

The overall sequence layer is used to: obtain the bottom-level incentives generated by the bottom layer of the sequence, send the acquired bottom-level incentives to the driver layer, and cache the backup of the acquired bottom-level incentives;

The driver layer is used to: if the underlying stimulus sent by the total sequence layer is successfully received, send the received underlying stimulus to the device under test, otherwise, instruct the total sequence layer to resend the cached backup of the underlying stimulus to the driver layer.

Among them, the driver layer (Driver) obtains the required underlying incentives by interacting with the overall sequence layer (sequencer). Specifically, the driver layer can obtain the top-level sequence through get_next_item(), and use the top-level sequence to generate the corresponding top-level incentives to determine The bottom-level incentive represented by the value of the variable of the enumeration type in the generated top-level incentive, initialize the bottom-level sequence corresponding to the bottom-level incentive, use the bottom-level sequence to generate the corresponding bottom-level incentive, and then send the bottom-level incentive by calling the driver task of the bottom-level sequence to the DUT (device under test). Among them, there is also a corresponding relationship between the driving task and the underlying incentive, and different driving tasks can drive different underlying incentives to the interface and send them to the DUT. There is a member variable seq_item_port in the driver layer, which is a port used to connect the driver and the sequencer. If the driver wants to send data, it must be sent from this port. If the sequencer has data to be handed over to the driver, it must also be sent through this port. Driver, to apply for data from this port, call the get_next_item method of this port, which can be seq_item_port.get_next_item(req).

It should be noted that, in order to improve reliability, the general sequence layer of this application can store the backup of the underlying incentive in its own cache while sending the underlying incentive to the driver layer, so that when the driver layer does not successfully receive the underlying incentive , the backup is sent to the driver layer again, and a backup is also kept when the backup is sent to the driver layer again, and so on.

In addition, when determining the value of the enumeration type variable contained in the top-level stimulus, it can be determined by the value of amba_op in the top-level stimulus. Specifically, the statement to obtain the top-level stimulus can be as follows:

Typedef enum{apb,ahb,axi,asb}amba_op_e;

class ahb_transacation extends uvm_sequence_item;

rand amba_op_e amba_op;

It can be seen that each time a top-level stimulus is generated, a random value of amba_op will be generated. 0 represents the apb bus, 1 represents the ahb bus, 2 represents the axi bus, and 3 represents the asb bus.

In the hierarchical verification platform provided by the embodiment of the present invention, the driver layer can also be used to: if the underlying incentive sent by the total sequence layer is successfully received, return the successful reception information to the total sequence layer;

The total sequence layer can also be used to delete the cached backup of the underlying incentives if the successful reception information sent by the driver layer is received.

In order to avoid the waste of cache resources in the overall sequence layer, the driver layer of the present application can return the successful reception information to the overall sequence layer after successfully receiving the underlying incentive sent by the overall sequence layer, so that the overall sequence layer can receive the information after receiving the information. , delete the corresponding backup that has been cached.

The hierarchical verification platform provided by the embodiment of the present invention may further include a monitoring layer, where the monitoring layer is used for: in the statistical test, the device uses the received underlying excitation to realize the coverage obtained by the test, and when the coverage does not reach the coverage threshold When the device under test is instructed to perform random testing until the coverage obtained by the device under test achieved by the test reaches the coverage threshold.

The monitoring layer can perform coverage statistics and use scripts to implement automated testing of the platform. The monitoring layer automatically obtains the coverage after automated testing. If the coverage reaches the coverage threshold set according to actual needs, the test is determined to be over. Otherwise, Instruct random testing to be performed, and monitor whether the coverage obtained after testing reaches the coverage threshold until the coverage reaches the coverage threshold, so as to realize automated testing in this way and ensure that the test coverage is up to standard. Specifically, after collecting the coverage ratio and outputting the coverage ratio to the text, the script can be used to read the coverage ratio value in the text, and then the corresponding control operation can be realized.

In the hierarchical verification platform provided by the embodiment of the present invention, the monitoring layer can also be used to: if the number of random tests performed by the device in the test reaches the number threshold and the coverage obtained by the device in the test does not reach the coverage threshold, output the Corresponding alarm information; and used to output corresponding test completion information if the number of random tests performed by the device under test does not reach the number threshold and the coverage obtained by the device under test achieved by the test reaches the coverage threshold.

In order to facilitate the staff to know the situation of random testing and avoid the waste of resources caused by non-stop random testing when the test is abnormal, the number of random tests in this application reaches the threshold set according to actual needs and the coverage rate does not reach the coverage rate. Threshold, and when the number of random tests does not reach the number threshold and the coverage rate reaches the coverage rate threshold, corresponding information is output, so as to facilitate the staff to carry out the corresponding work.

The embodiment of the present invention provides a hierarchical verification platform. The hierarchical verification platform can be built based on UVM, and the driver layer and the overall sequence layer are encapsulated in the env layer of the hierarchical verification platform.

Due to the different underlying incentives transmitted by the underlying sequence, the tlm transaction-level port cannot be used in the platform. In this application, uvm_config_db::get and uvm_config_db::set are used for data transmission between modules (driver layer and monitoring layer, etc.); and In order to further improve the interaction efficiency, this application cancels the encapsulation of the agent, and directly encapsulates the driver and sequencer in the env layer.

In addition, it should be noted that when the driver wants to drive the transaction, it applies for a transaction to the sequencer, and when the application is received, it is sent to the device under test. Specifically, it can be implemented by the following statement:

class ahb_transacation extends uvm_sequence_item;

rand bit reset;

rand transfer_t trans_type[];

rand bit[31:0]address[];

rand size_t trans_size;

rand burst_t burst_mode;

rand rw_t read_write;

rand bit[31:0] write_data[].

When defining the underlying incentives, it is also possible to create more subdivided underlying incentives based on the functional points that need to be verified in the test project, specify different constraints, and generate different data frames or packages. Specifically, the upper and lower limits of the address can be constrained according to the division of the memory address, the data sent can also be constrained (depending on the data constraints required by the specific module), and the check digit can be added as a constraint; For example, a project divides each module into different address spaces, and only by accessing addresses within this address space range can the corresponding modules be accessed. Among them, the statement specifying the corresponding constraint can be as follows:

The embodiment of the present invention also provides a hierarchical verification method, which may include:

S11: Use the top-level sequence to generate corresponding top-level incentives; wherein, different top-level sequences correspond to different top-level incentives, and different top-level incentives correspond to different values of the variable of the same enumeration type, and different values of the variable are associated with different top-level incentives. The underlying incentives correspond;

S12: Determine the bottom layer incentive corresponding to the generated top layer incentive, and use the bottom layer sequence corresponding to the bottom layer incentive to generate the bottom layer incentive; wherein, different bottom layer sequences correspond to different bottom layer incentives, and different bottom layer incentives have different Data format, the different data formats correspond to different buses.

The embodiment of the present invention also provides a hierarchical verification device, which may include:

memory for storing computer programs;

The processor is configured to implement the steps of the above hierarchical verification method when executing the computer program.

Embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above hierarchical verification method can be implemented.

The parts of the above technical solutions provided in the embodiments of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as to avoid redundant descriptions.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A hierarchical verification platform is characterized by comprising an excitation top layer, an excitation bottom layer, a sequence top layer and a sequence bottom layer; wherein:

the excitation top layer is used for: defining top-level excitations, wherein each top-level excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;

the excitation substrate is used for: defining underlying stimuli, each of said underlying stimuli having a different data format, and said different data formats corresponding to different buses;

the sequence top layer is used for: storing top-level sequences respectively corresponding to different top-level excitations, and generating corresponding top-level excitations by utilizing the top-level sequences;

the sequence bottom layer is used for: storing bottom layer sequences respectively corresponding to the different bottom layer excitations, and generating the bottom layer excitations by utilizing the corresponding bottom layer sequences after determining the bottom layer excitations corresponding to the top layer excitations generated by the top layer of the sequences.

2. The platform of claim 1, further comprising a drive layer and a global sequence layer;

the total sequence layer is used for: acquiring bottom layer excitation generated by the sequence bottom layer, sending the acquired bottom layer excitation to the driving layer, and caching backup of the acquired bottom layer excitation;

the driving layer is used for: and if the bottom layer excitation sent by the total sequence layer is successfully received, sending the received bottom layer excitation to the device under test, otherwise, instructing the total sequence layer to resend the cached backup of the bottom layer excitation to the drive layer.

3. The platform of claim 2, wherein the drive layer is further to: if the bottom layer excitation sent by the total sequence layer is successfully received, returning the information of successful reception to the total sequence layer;

the total sequence layer is further to: and if the information of successful receiving sent by the driving layer is received, deleting the cached backup of the bottom layer excitation.

4. The method of claim 3, further comprising a monitoring layer to: and counting the coverage rate obtained by the equipment under test by utilizing the received bottom layer excitation to realize the test, and indicating the equipment under test to carry out random test when the coverage rate does not reach the coverage rate threshold value until the coverage rate obtained by the equipment under test to realize the test reaches the coverage rate threshold value.

5. The platform of claim 4, wherein the monitoring layer is further to: and if the times of the random test of the equipment under test reach a time threshold value and the coverage rate of the equipment under test, which is obtained by realizing the test, does not reach the coverage rate threshold value, outputting corresponding alarm information.

6. The platform of claim 5, wherein the monitoring layer is further to: and if the times of the random test of the equipment in the test do not reach the time threshold value and the coverage rate of the equipment in the test, which is obtained by realizing the test, reaches the coverage rate threshold value, outputting corresponding test completion information.

7. The platform of claim 6, wherein the hierarchical verification platform is built based on UVM, and the driver layer and the overall sequence layer are both encapsulated in an env layer of the hierarchical verification platform.

8. A hierarchical verification method, comprising:

generating a corresponding top-level stimulus using the top-level sequence; wherein, different top-level sequences correspond to different top-level excitations, and the different top-level excitations correspond to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;

determining a bottom layer excitation corresponding to the generated top layer excitation, and generating the bottom layer excitation by using a bottom layer sequence corresponding to the bottom layer excitation; wherein different underlying sequences correspond to different underlying stimuli and the different underlying stimuli have different data formats corresponding to different buses.

9. A hierarchical authentication apparatus, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the hierarchical verification method of claim 8 when executing the computer program.

10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the hierarchical verification method as set forth in claim 8.

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