CN111832245A - Integrated circuit including standard cells, method for manufacturing the same, and computing system - Google Patents

Abstract

An integrated circuit including standard cells, a method of manufacturing the same, and a computing system for performing the method are provided. The integrated circuit includes: a standard cell including a first output pin and a second output pin configured to each output a same output signal; a first routing path connected to a first output pin; and a second routing path connected to the second output pin. The first routing path includes a first set of cells, the first set of cells includes at least one load cell, the second routing path includes a second set of cells, the second set of cells includes at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Description

Integrated circuit including standard cells, method for manufacturing the same, and computing system

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2019-0047526 filed on April 23, 2019 and Korean Patent Application No. 10-2019-0143659 filed on November 11, 2019 with the Korean Intellectual Property Office, Its entire disclosure is incorporated herein by reference.

technical field

Exemplary embodiments of the inventive concept relate to an integrated circuit, and more particularly, to an integrated circuit including standard cells, a method of manufacturing the integrated circuit, and a computing system for performing the method.

Background technique

In the manufacture of integrated circuits, a large number of semiconductor devices can be integrated into the integrated circuits. Therefore, the configuration of the integrated circuit may be complicated, and the semiconductor manufacturing process performed to manufacture the integrated circuit may be subdivided into various processes. In the manufacture of integrated circuits, the gate length of the device and the width of the wiring connecting the semiconductor devices have been gradually reduced. Electromigration (EM) may occur as the cross-sectional area of the wiring decreases. Due to EM, wirings may be open, or different wirings may be shorted to each other.

SUMMARY OF THE INVENTION

Exemplary embodiments of the inventive concept provide an integrated circuit including a standard cell in which output pins are separated from each other, a method of manufacturing the integrated circuit, and a computing system for performing the method.

According to an aspect of the present inventive concept, there is provided an integrated circuit including: a standard cell including a first output pin and a second output pin, the first output pin and the second output pin being configured to output the same respectively the output signal; a first routing path, connected to the first output pin; and a second routing path, connected to the second output pin. The first routing path includes a first cell group, the first cell group includes at least one load cell, the second routing path includes a second cell group, the second cell group includes at least one load cell, and the first routing path and the second routing path Electrically disconnected from each other outside the standard cell.

According to another aspect of the present inventive concept, there is provided a method of manufacturing an integrated circuit including a driving unit in which a first output pin and a second output pin are provided for supplying outputs to a plurality of load units the same output signal. The method includes: referring to a standard cell library, and arranging a driving unit based on netlist data, the netlist data including information about the integrated circuit; obtaining the allowable load levels of the first output pin and the second output pin; the load level, grouping the load cells into a first cell group and a second cell group; and connecting the first output pin to the input pin of at least one load cell of the first cell group, and connecting the second output pin An input pin to at least one load cell of the second cell group.

According to another aspect of the inventive concept, a computing system for fabricating an integrated circuit is provided. The computing system includes: a memory bank configured to store a standard cell library including information about a plurality of standard cells and a program for designing an integrated circuit; and a processor configured to access the memory. The processor is configured to perform the following operations by executing a program: a drive unit is arranged with reference to a standard cell library, the drive unit includes a first output pin and a second output pin, the respective outputs of the first output pin and the second output pin are provided to Identical output signals of load cells; grouping load cells into first cell groups and second cell groups based on the respective allowable load levels of the first output pin and the second output pin; connecting the first output pin to An input pin of at least one load cell of the first cell group, and a second output pin is connected to an input pin of at least one load cell of the second cell group.

Description of drawings

The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

1A and 1B are diagrams illustrating layouts of integrated circuits according to example embodiments.

FIG. 2 is a circuit diagram in a case where a standard cell included in an integrated circuit according to an exemplary embodiment is a clock gating cell.

FIG. 3 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

FIG. 4 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

FIG. 5 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

FIG. 6 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment.

FIG. 7 is a circuit diagram in a case where standard cells included in an integrated circuit according to an exemplary embodiment are clock gating cells.

FIG. 8 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment.

FIG. 9 is a diagram for describing a standard cell library referenced in a method of manufacturing an integrated circuit according to an exemplary embodiment.

FIG. 10 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment.

FIG. 11 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment.

FIG. 12 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment.

13 is a block diagram illustrating a computing system including a memory to store programs, according to an example embodiment.

Detailed ways

Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numbers may refer to the same elements.

It will be understood that the terms "first," "second," "third," etc. are used herein to distinguish elements from one another and that elements are not limited by these terms. Thus, a "first" element in one exemplary embodiment may be described as a "second" element in another exemplary embodiment.

It should be understood that descriptions of features or aspects in each exemplary embodiment should generally be considered available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

For ease of description, spatially relative terms such as "under", "below", "under (part)", "below", "above", " to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both an orientation of above and below.

It will be understood that when a component is referred to as being "connected to" another component, it can be directly connected to the other component or intervening components may be present. It will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Other words used to describe the relationship between elements should be interpreted in a similar fashion.

1A and 1B are diagrams illustrating layouts of integrated circuits according to example embodiments.

A standard cell may be a layout unit included in an integrated circuit and may be referred to as a cell. The load unit may be a layout unit with a load included in the integrated circuit. For example, the load unit may be a layout unit included in an integrated circuit including, for example, at least one capacitor. The load cells may correspond to flip-flops or latches, for example. However, the load cell is not limited to this. A load cell may be a type of standard cell, and may be driven by another standard cell (eg, a drive unit) that is not a load cell. The standard cells C1 to C6 described below may all be drive cells. An integrated circuit may include a number of various units. Each cell may have a structure based on predetermined criteria, and may be arranged and arranged in a plurality of rows. Here, the first direction X may be referred to as a first horizontal direction, the second direction Y may be referred to as a second horizontal direction, and a plane based on the first direction X and the second direction Y may be referred to as a horizontal plane.

Referring to FIG. 1A , an integrated circuit 10 according to an exemplary embodiment may include at least one first standard cell C1 defined by a cell boundary. The first standard cell C1 may be provided from a standard cell library (eg, D12 of FIG. 8 ).

The first standard cell C1 may include an active region extending in the first direction X, and may include a gate line extending in the second direction Y. The gate lines and active regions may form transistors. The first standard cell C1 may include at least one fin extending in the first direction X in the active region, and the fin may form a Fin Field Effect Transistor (FinFET) together with the gate line. The active region and the gate line may be electrically connected to the pattern of the conductive layer (eg, the first wiring layer M1 ) through contacts and/or vias.

In exemplary embodiments, the active region may include a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP, and the conductive region may include, for example, impurity-doped wells and doped structure of impurities. In an exemplary embodiment, the gate line may include a work function metal-containing layer and a gap-fill metal layer. For example, the work function metal-containing layer may include titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd) at least one metal, and the gap-filling metal layer may include a tungsten (W) layer or an aluminum (Al) layer )Floor. In exemplary embodiments, the gate line may include a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W.

The integrated circuit 10 may include a plurality of wiring layers (eg, a first wiring layer M1 , a second wiring layer M2 , and a third wiring layer M3 ) stacked in the third direction Z. In an exemplary embodiment, the width of the pattern provided in the third wiring layer M3 may be greater than that of the pattern provided in the second wiring layer M2, and the width of the pattern provided in the second wiring layer M2 may be greater than that of the pattern provided in the second wiring layer M2. The width of the pattern in the first wiring layer M1. However, the present disclosure is not limited thereto.

In an exemplary embodiment, the patterns provided in the first wiring layer M1 may extend in the first direction X, the patterns provided in the second wiring layer M2 may extend in the second direction Y, and the patterns provided in the third wiring layer M3 The patterns in can extend along the first direction X. However, the integrated circuit 10 according to the present disclosure is not limited thereto, and the direction in which each pattern extends may be set in various ways. The second wiring layer M2 may correspond to an upper layer with respect to the first wiring layer M1. For example, the second wiring layer M2 may be disposed over the first wiring layer M1.

The patterns disposed in each of the first wiring layer M1, the second wiring layer M2, and the third wiring layer M3 may include metal, conductive metal nitride, metal silicide, or a combination thereof. For example, patterns provided in each of the first wiring layer M1, the second wiring layer M2, and the third wiring layer M3 may include conductive materials such as W, Mo, Ti, Co, tantalum (Ta), Ni, tungsten silicide, silicide Titanium, cobalt silicide, tantalum silicide or nickel silicide.

The first standard cell C1 may include a pattern provided in the first wiring layer M1 and a pattern provided in the second wiring layer M2, and may include a pattern provided between the first wiring layer M1 and the second wiring layer M2 and the second wiring layer M2. A wiring layer M1 is connected to the first via V1 of the second wiring layer M2. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the first standard cell C1 may further include a pattern disposed in the third wiring layer M3, and may include a pattern disposed between the second wiring layer M2 and the third wiring layer M3 and the second wiring layer M3 The wiring layer M2 is connected to the second via hole V2 of the third wiring layer M3. The patterns shown in FIG. 1 may be some of the patterns included in the first standard cell C1. In an exemplary embodiment, additional patterns may also be included in the first standard cell C1.

In an exemplary embodiment, the first standard cell C1 may include a first output pin OP1 and a second output pin OP2. The first output pin OP1 and the second output pin OP2 may be provided separately from each other on the same horizontal plane (eg, the plane on which the second wiring layer M2 is provided). The first output pin OP1 and the second output pin OP2 may be spaced apart from each other in the first direction X by a first distance d1.

The first output pin OP1 and the second output pin OP2 may be electrically connected to each other in the first standard cell C1. For example, the first output pin OP1 and the second output pin OP2 may pass through the patterns M11 and M12 provided in the first wiring layer M1 and the first via provided between the first wiring layer M1 and the second wiring layer M2 The holes V1_11, V1_12, V1_21 and V1_22 are connected to each other. In this layout (eg, in a layout view), the first output pin OP1, the second output pin OP2, and the patterns M11 and M12 provided in the first wiring layer M1 may form a ring shape.

In an exemplary embodiment, the first and second output pins OP1 and OP2 may be patterns of the second wiring layer M2. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the first output pin OP1 and the second output pin OP2 may be disposed on any layer higher than the second wiring layer M2, and may be formed as a pattern of the third wiring layer M3, for example.

The first output pin OP1 may be connected to the first routing path RP1, which may include the first cell group STC1. The second output pin OP2 may be connected to a second routing path RP2, which may include a second cell group STC2.

The first standard cell C1 may be a driving unit for driving the first cell group STC1 and the second cell group STC2. The first cell group STC1 may include at least one load cell, and the second cell group STC2 may include at least one load cell. In an exemplary embodiment, the first standard cell C1 may be a power cell that supplies power to the first cell group STC1 and the second cell group STC2. Alternatively, in an exemplary embodiment, the first standard cell C1 may be a clock gating cell that provides an internal clock signal to the first cell group STC1 and the second cell group STC2.

The first output pin OP1 may be connected to an input pin of at least one load cell included in the first cell group STC1. The second output pin OP2 may be connected to an input pin of at least one load cell included in the second cell group STC2. The first cell group STC1 may receive the output signal output from the first output pin OP1, and the second cell group STC2 may receive the output signal output from the second output pin OP2. The output signals respectively output from the first output pin OP1 and the second output pin OP2 may be substantially the same signal. Here, when two signals are described as being substantially the same, the two signals may be the same as each other, or if not, they would be understood by those of ordinary skill in the art to be functionally the same as each other.

In an exemplary embodiment, the first routing path RP1 may include a first routing wiring M2R1 provided in the second wiring layer M2, a first routing wiring M3R1 provided in the third wiring layer M3, and the second wiring layer M2 Connected to the second via hole V2 of the third wiring layer M3. The second routing path RP2 may include a second routing wiring M2R2 provided in the second wiring layer M2, a second routing wiring M3R2 provided in the third wiring layer M3, and a second via V2. For example, the first routing path RP1 may include a first routing wiring M2R1 in contact with the first output pin OP1, and the second routing path RP2 may include a second routing wiring M2R2 in contact with the second output pin OP2. However, the present disclosure is not limited thereto. For example, in the exemplary embodiment, a plurality of routing wirings constituting the first routing path RP1 and the second routing path RP2 may be provided on the respective wiring layers in various manners.

In an exemplary embodiment, the first routing path RP1 and the second routing path RP2 are not connected to each other outside the first standard cell C1. For example, the first routing path RP1 and the second routing path RP2 may be electrically connected to each other inside the first standard cell C1, but may be electrically disconnected from each other outside the first standard cell C1.

The first standard cell C1 included in the integrated circuit 10 according to an exemplary embodiment may include a first output pin OP1 and a second output pin OP2 that output substantially the same signal. In this case, the first routing path RP1 connected to the first output pin OP1 and the second routing path RP2 connected to the second output pin OP2 may be disconnected from each other, and thus, the first output pin may be reduced The respective output loads of OP1 and the second output pin OP2. Therefore, the current density of the currents flowing through each of the first output pin OP1 and the second output pin OP2 can be reduced, so that the occurrence of electromigration (EM) can be prevented or reduced. In the integrated circuit 10 according to the exemplary embodiment, although no additional wiring is provided in the third wiring layer M3, defects in which the wirings are short-circuited or open to each other in the integrated circuit 10 due to EM can be reduced.

Referring to FIG. 1B , the integrated circuit 10a according to an exemplary embodiment may include at least one second standard cell C2. The second standard cell C2 may include a first output pin OP1a and a second output pin OP2a that output substantially the same signal.

The first and second output pins OP1a and OP2a may be patterns disposed in the second wiring layer M2, and may be spaced apart from each other in the first direction X by a second distance d2. In an exemplary embodiment, the second distance d2 by which the first output pin OP1a and the second output pin OP2a of the second standard cell C2 are spaced apart from each other may be greater than the first output pin of the first standard cell C1 of FIG. 1A OP1 and the second output pin OP2 are spaced apart from each other by a first distance d1. When the same load cell is connected to the first standard cell C1 of FIG. 1A and the second standard cell C2 of FIG. 1B , the respective current densities of the first output pin OP1a and the second output pin OP2a of the second standard cell C2 may be lower than the respective current densities of the first output pin OP1 and the second output pin OP2 of the first standard cell C1. Therefore, in the second standard cell C2 of FIG. 1B compared to the first standard cell C1 of FIG. 1A , the probability of occurrence of EM can be reduced.

A standard cell library D12 (eg, FIG. 8 ) for designing a computing system of integrated circuits 10 and 10a according to an exemplary embodiment may store information about the first standard cell C1 of FIG. 1A and about the second standard cell of FIG. 1B Information for C2. As described below with reference to FIG. 8 , in the process of manufacturing the integrated circuit, the standard cell library D12 can provide standard cells with the same function (eg, the same function of the driving unit) but different structures, and in the process of laying out the standard cells, it can be A standard cell with a suitable structure is selected from the standard cell library D12. For example, in the integrated circuits 10 and 10a, one of the first standard cell C1 of FIG. 1A and the second standard cell C2 of FIG. 1B may be selectively routed based on the respective load levels of the first cell group STC1 and the second cell group STC2 one. Thus, both integrated circuits 10 and 10a may include standard cells with the same function and performance but different structures.

FIG. 2 is a circuit diagram in a case where a standard cell included in an integrated circuit according to an exemplary embodiment is a clock gating cell. The area A of FIG. 2 may correspond to the respective layouts of the first standard cell C1 of FIG. 1A and the second standard cell C2 of FIG. 1B .

In FIG. 2, the circuit corresponding to each element of the first standard cell C1 and the second standard cell C2 of the clock gating unit CA is shown in detail. However, the present disclosure is not limited to the configuration shown in FIG. 2 . For example, in an exemplary embodiment, the circuit of each element of the clock gating unit CA may be modified. Also, for convenience of description, in order to describe the respective layouts of the first standard cell C1 of FIG. 1A and the second standard cell C2 of FIG. 1B , the clock gating unit CA will be described with reference to FIG. 2 . However, the present disclosure is not limited thereto, and the following description may be applied to other driving units for driving a plurality of load units.

2 , the clock gating unit CA may include a NOR gate 101 , a transmission gate 102 , a plurality of inverters 103 and 104 , a three-phase inverter 105 , a NAND gate 106 and an output inverter 107 .

The NOR gate 101 may receive an enable signal E and a scan enable signal SE, and may generate an inversion enable signal EN. The transmission gate 102, the inverter 104 and the three-phase inverter 105 may constitute a latch. The transmission gate 102 may receive the inversion enable signal EN and may transmit the inversion enable signal EN to the inverter 104 based on the clock signal CK. The inverter 104 may invert the inversion enable signal EN, and may transmit the first signal S1 to the NAND gate 106 . The three-phase inverter 105 may receive the first signal S1 and may output a signal generated by inverting the first signal S1 based on the clock signal CK.

The NAND gate 106 may receive the first signal S1 and the clock signal CK, and may generate an inverted clock signal CKb. The output inverter 107 may invert the inverted clock signal CKb to output the first output signal ECK1 and the second output signal ECK2. In this case, the first output signal ECK1 and the second output signal ECK2 may each be an internal clock signal supplied to a load unit connected to the clock gating unit CA.

The first output signal ECK1 may be output from the first output pin OP1 (or OP1 a ) connected to the output terminal of the output inverter 107 , and the second output signal ECK2 may be output from the second output pin OP1 (or OP1 a ) connected to the output terminal of the output inverter 107 . Output pin OP2 (or OP2a) output. The first output signal ECK1 and the second output signal ECK2 may be signals output from different output pins, or may be signals output from the same node (eg, the output terminal of the output inverter 107 ), and thus may be substantially the same Signal.

In the clock gating unit CA included in the integrated circuit 10 according to an exemplary embodiment, output pins outputting substantially the same signal may be divided into a first output pin OP1 (or OP1a) and a second output pin OP2 (or OP2a), and the first output signal ECK1 and the second output signal ECK2 can be provided to different load units, thereby reducing the first output pin OP1 (or OP1a) and the second output pin OP2 of the clock gating unit CA (or OP2a) the respective output load.

FIG. 3 is a diagram illustrating the layout of the integrated circuit 10b according to an exemplary embodiment. Hereinafter, further descriptions of previously described elements and aspects may be omitted for convenience of explanation.

3, the integrated circuit 10b according to an exemplary embodiment may include at least one third standard cell C3. The third standard cell C3 may include a first output pin OP1 and a second output pin OP2.

The first output pin OP1 and the second output pin OP2 may be electrically connected to each other in the third standard cell C3. For example, the first output pin OP1 and the second output pin OP2 may pass through the patterns M11 and M12 provided in the first wiring layer M1 , the first via provided between the first wiring layer M1 and the second wiring layer M2 The holes V1_11, V1_12, V1_21, V1_22, V1_31, and V1_32 and the pattern M21 provided in the second wiring layer M2 are connected to each other. The pattern M21 provided in the second wiring layer M2 may be connected to the patterns M11 and M12 provided in the first wiring layer M1 through the first via holes V1_31 and V1_32. In this layout (eg, in a layout view), the first output pin OP1, the second output pin OP2, the patterns M11 and M12 provided in the first wiring layer M1, and the patterns M11 and M12 provided in the second wiring layer M2 The patterns M21 may form a mesh structure.

The first output pin OP1 may be connected to the first routing path RP1, and the second output pin OP2 may be connected to the second routing path RP2. The first cell group STC1 may receive the output signal output from the first output pin OP1, and the second cell group STC2 may receive the output signal output from the second output pin OP2. The output signals respectively output from the first output pin OP1 and the second output pin OP2 may be substantially the same signal. In an exemplary embodiment, the first routing path RP1 and the second routing path RP2 are not connected to each other outside the third standard cell C3. For example, the first routing path RP1 and the second routing path RP2 may be electrically connected to each other in the third standard cell C3, but may be electrically disconnected from each other outside the third standard cell C3.

FIG. 4 is a diagram illustrating the layout of the integrated circuit 10c according to an exemplary embodiment. Hereinafter, further descriptions of previously described elements and aspects may be omitted for convenience of explanation.

4 , the integrated circuit 10c according to an exemplary embodiment may include a fourth standard cell C4 and a first cell group STC1 and a second cell group STC2 connected to the fourth standard cell C4. Each of the first cell group STC1 and the second cell group STC2 may include at least one load cell.

The integrated circuit 10c may include a plurality of wiring layers (eg, first to fourth wiring layers M1 to M4) stacked in the third direction Z. In an exemplary embodiment, the width of the pattern provided in the fourth wiring layer M4 may be greater than the width of the pattern provided in the third wiring layer M3, and the pattern provided in the fourth wiring layer M4 may be along the second direction Y extension. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the direction and width of each pattern extension may be set in various ways.

The first output pin OP1 may be connected to the first routing path RP1', which may include the first cell group STCl. The second output pin OP2 may be connected to a second routing path RP2', which may include a second cell group STC2.

In an exemplary embodiment, the first routing path RP1' may include a first routing wiring M3R1 of the third wiring layer M3, a first routing wiring M4R1 of the fourth wiring layer M4, connecting the first output pin OP1 to the third wiring layer M4R1 The second via V2 of the wiring layer M3 and the third via V3 connecting the third wiring layer M3 to the fourth wiring layer M4. The third wiring layer M3 may correspond to an upper layer with respect to the second wiring layer M2. For example, the third wiring layer M3 may be disposed over the second wiring layer M2. The second routing path RP2' may include a second routing wiring M2R2 of the second wiring layer M2, a second routing wiring M3R2 of the third wiring layer M3, and a second via connecting the second wiring layer M2 to the third wiring layer M3 v2. For example, the first routing path RP1' may include a first routing wiring M3R1 of the third wiring layer M3 and a second via V2 contacting the first output pin OP1 and the first routing wiring M3R1, and the second routing path RP2' may The second routing wiring M2R2 of the second wiring layer M2 in contact with the second output pin OP2 is included. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the second routing path RP2' may include a second via V2 connected to the pattern of the third wiring layer M3 and in contact with the second output pin OP2. The plurality of routing wirings constituting the first routing path RP1' and the second routing path RP2' may be arranged on the respective wiring layers in various ways.

In an exemplary embodiment, the first routing path RP1' and the second routing path RP2' are not connected to each other outside the fourth standard cell C4. For example, the first routing path RP1' and the second routing path RP2' may be electrically connected to each other in the fourth standard cell C4, but may be electrically disconnected from each other outside the fourth standard cell C4.

In the integrated circuit 10c according to the exemplary embodiment, the first output pin OP1 may be connected to the first routing wiring M3R1 provided in the third wiring layer M3 through the second via hole V2, and thus, the fourth wiring as the driving unit Standard cells C4 may be connected to a first cell group STC1 comprising at least one load cell. In the first to fourth wiring layers M1 to M4 , the degree of freedom of forming patterns can be increased toward higher levels, and patterns having relatively wide widths can be formed. Therefore, based on the load level of the first routing path RP1 ′, at least one of the first routing wirings M3R1 provided in the third wiring layer M3 and the first routing wirings M4R1 provided in the fourth wiring layer M4 can be adjusted to form The width of the pattern, or the number of patterns forming the at least one first routing wiring can be adjusted.

The fourth standard cell C4 included in the integrated circuit 10c according to the exemplary embodiment may include a plurality of output pins (eg, a first output pin OP1 and a second output pin OP2) connected to the first output pin OP1 The first routing path RP1' may be separately provided from the second routing path RP2' connected to the second output pin OP2, thereby reducing the respective output loads of the first output pin OP1 and the second output pin OP2.

FIG. 5 is a diagram illustrating the layout of the integrated circuit 10d according to an exemplary embodiment. Hereinafter, further descriptions of previously described elements and aspects may be omitted for convenience of explanation.

5, the integrated circuit 10d according to an exemplary embodiment may include at least one fifth standard cell C5. The fifth standard cell C5 may include a plurality of output pins OP1 to OP3, for example, may include a first output pin OP1, a second output pin OP2 and a third output pin OP3.

The first to third output pins OP1 to OP3 may be electrically connected to each other in the fifth standard cell C5. For example, the first to third output pins OP1 to OP3 may pass through the patterns M11 and M12 provided in the first wiring layer M1, the first via V1_11 provided between the first wiring layer M1 and the second wiring layer M2 , V1_12, V1_21, V1_22, V1_31' and V1_32' are connected to each other.

The third output pin OP3 may be connected to a third routing path RP3, which may include a third cell group STC3. The third cell group STC3 may include at least one standard cell as a load cell. In an exemplary embodiment, the third routing path RP3 may include a third routing wiring M2R3 of the second wiring layer M2, a third routing wiring M3R3 of the third wiring layer M3, and connecting the second wiring layer M2 to the third wiring layer The second via V2 of M3.

The third cell group STC3 may receive the output signal output from the third output pin OP3. The output signals respectively output from the first to third output pins OP1 to OP3 may be substantially the same signal.

In the exemplary embodiment, the first to third routing paths RP1 to RP3 are not connected to each other outside the fifth standard cell C5. For example, the first to third routing paths RP1 to RP3 may be electrically connected to each other in the fifth standard cell C5, but may be electrically disconnected from each other outside the fifth standard cell C5.

The fifth standard cell C5 of FIG. 5 may include three output pins that output substantially the same output signal. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the fifth standard cell C5 as the driving unit may include various numbers of output pins outputting substantially the same output signal. In the case where the load unit connected to the fifth standard cell C5 as the driving unit is the same, as the number of output pins outputting substantially the same signal increases, the load level of each output pin can be reduced, and each output pin The current density of the feet can be reduced. On the other hand, as the number of output pins that output substantially the same signal decreases, it may become easier to form routing paths to load cells. Therefore, in the integrated circuit, the number of pins included in the fifth standard cell C5 and outputting substantially the same output signal can be adjusted in various ways based on desired design characteristics.

FIG. 6 is a diagram illustrating the layout of the integrated circuit 10e according to an exemplary embodiment. Hereinafter, further descriptions of previously described elements and aspects may be omitted for convenience of explanation.

Referring to FIG. 6 , the integrated circuit 10e according to an exemplary embodiment may include at least one sixth standard cell C6 defined by cell boundaries. The sixth standard cell C6 may include patterns provided in the first wiring layer M1 and patterns provided in the second wiring layer M2. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the sixth standard cell C6 may further include a pattern disposed in the third wiring layer M3.

In an exemplary embodiment, the sixth standard cell C6 may include a first output pin OP1e and a second output pin OP2e. In Figure 6, the sixth standard cell C6 is shown to include two output pins: a first output pin OP1e and a second output pin OP2e. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the number of output pins provided in the sixth standard cell C6 may be three or more.

In an exemplary embodiment, the first output pin OP1e and the second output pin OP2e of the sixth standard cell C6 may be connected to different elements. For example, the first output pin OP1e may be connected to the first inverter, and the second output pin OP2e may be connected to the second inverter. The first inverting chip and the second inverting chip may receive a signal, and may output an output signal to the first output pin OP1e and the second output pin OP2e, respectively.

The first output pin OP1e may be connected to the first routing path RP1, and the second output pin OP2e may be connected to the second routing path RP2. The first cell group STC1 may receive the first output signal output from the first output pin OP1e, and the second cell group STC2 may receive the second output signal output from the second output pin OP2e. In an exemplary embodiment, the first output pin OP1e and the second output pin OP2e may be physically separated from each other, and the first output signals output from the first output pin OP1e and the second output pin OP2e, respectively and the second output signal may be substantially the same signal. The respective timing characteristics of the first output signal and the second output signal may vary.

In an exemplary embodiment, each of the first output pin OP1e and the second output pin OP2e may be arranged to have a pattern of the second wiring layer M2 of the sixth standard cell C6. The first output pin OP1e may be connected to the patterns M11 and M12 of the first wiring layer M1 through the first via holes V1_11 and V1_12 disposed between the first wiring layer M1 and the second wiring layer M2. The second output pin OP2e may be connected to the patterns M13 and M14 of the first wiring layer M1 through the first vias V1_21 and V1_22 disposed between the first wiring layer M1 and the second wiring layer M2.

In an exemplary embodiment, the first output pin OP1e and the second output pin OP2e may be disposed apart from each other on the same horizontal plane (eg, the plane on which the second wiring layer M2 is disposed). The patterns M11 and M12 of the first wiring layer M1 connected to the first output pin OP1e and arranged under the first output pin OP1e and the first wiring layer M12 connected to the second output pin OP2e and arranged under the second output pin OP2e. The patterns M13 and M14 of a wiring layer M1 may be provided separately from each other on the same horizontal plane (eg, the plane on which the first wiring layer M1 is provided). Therefore, the characteristics of the first output signal output from the first output pin OP1e may be different from the characteristics of the second output signal output from the second output pin OP2e.

The sixth standard cell C6 included in the integrated circuit 10e according to the exemplary embodiment may include a plurality of output pins (eg, a first output pin OP1e and a second output pin OP2e). The first routing path RP1 connected to the first output pin OP1e may be provided separately from the second routing path RP2 connected to the second output pin OP2e, thereby reducing the size of the first output pin OP1e and the second output pin OP2e respective output loads.

FIG. 7 is a circuit diagram in a case where standard cells included in an integrated circuit according to an exemplary embodiment are clock gating cells. The area AA of FIG. 7 may correspond to the layout of the sixth standard cell C6 shown in FIG. 6 . Hereinafter, further descriptions of previously described elements and aspects may be omitted for convenience of explanation.

In Fig. 7, the circuit of each element of the sixth standard cell C6 as the clock gating cell CAA is shown. However, the present disclosure is not limited to the configuration shown in FIG. 7 . For example, in an exemplary embodiment, the circuitry of each element of the clock gating unit CAA may be modified.

7 , the clock gating unit CAA may include a NOR gate 101, a transmission gate 102, a plurality of inverters 103 and 104, a three-phase inverter 105, a NAND gate 106, a first output inverter 107_1 and a second The inverter 107_2 is output.

The first output inverter 107_1 may receive the inverted clock signal CKb from the NAND gate 106, and may invert the inverted clock signal CKb to output the first output signal ECK1A. The second output inverter 107_2 may receive the inverted clock signal CKb from the NAND gate 106, and may invert the inverted clock signal CKb to output the second output signal ECK2A.

The first output signal ECK1A may be output from the first output pin OP1e connected to the output terminal of the first output inverter 107_1, and the second output signal ECK2A may be output from the second output pin connected to the output terminal of the second output inverter 107_2 Output pin OP2e output. For example, the first output signal ECK1A and the second output signal ECK2A may be signals output through the output terminals of the first output inverter 107_1 and the second output inverter 107_2 that receive the inverted clock signal CKb, the inverted clock signal CKb is a signal input to the first output inverter 107_1 and the second output inverter 107_2. The first output signal ECK1A and the second output signal ECK2A may be output via the first output inverter 107_1 and the second output inverter 107_2 as different output inverters, and thus may be substantially the same signal despite the characteristics such as timing There may be differences between characteristics.

For example, the timing characteristics of the first output signal ECK1A and the second output signal ECK2A may be different. Therefore, in the method of manufacturing an integrated circuit according to an exemplary embodiment, the first output pin OP1e connected to the first output pin OP1e of the clock gating unit CAA may be selected based on the respective characteristics of the first output signal ECK1A and the second output signal ECK2A A cell group and a second cell group connected to the second output pin OP2e of the clock gating cell CAA.

FIG. 8 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment. FIG. 9 is a diagram for describing a standard cell library referenced in a method of manufacturing an integrated circuit according to an exemplary embodiment.

8 and 9, a method of manufacturing an integrated circuit IC may refer to a process design kit (PDK). The PDK may include standard cell library D12 and design rules (DR).

The standard cell library D12 may include information on standard cells (eg, function information, characteristic information, and layout information). As shown in FIG. 9, the standard cell library D12 may include data D12_a and D12_b that define the layout of standard cells.

In an exemplary embodiment, the standard cell library D12 may define the layout of each standard cell (eg, C1 to C6 of FIGS. 1A to 6 ) having the same function and performance. For example, the first data D12_a may define a standard cell including one output pin outputting a specific output signal. The second to seventh data D12_1b to D12_6b may define standard cells including a plurality of output pins outputting specific output signals. The second data D12_1b may define the first standard cell C1 of FIG. 1A . The third data D12_2b may define the second standard cell C2 of FIG. 1B . The fourth data D12_3b may define the third standard cell C3 of FIG. 3 . The fifth data D12_4b may define the fourth standard cell C4 of FIG. 4 . The sixth data D12_5b may define the fifth standard cell C5 of FIG. 5 . The seventh data D12_6b may define the sixth standard cell C6 of FIG. 6 .

As described above with reference to FIGS. 6 and 7 , the seventh data D12_6b may include information DOP1 about the first output signal output from the first output pin OP1e of the sixth standard cell C6 of FIG. The information DOP2 of the second output signal output by the second output pin OP2e of the six standard cells C6. For example, the seventh data D12_6b may include timing characteristics of the first output signal and timing characteristics of the second output signal.

In an exemplary embodiment, an EM standard DR may be defined. For example, the EM standard DR may include a reference value based on a load level of a load unit connected to an output pin of a standard unit as a drive unit. In an exemplary embodiment, the EM standard DR may be received from a designer and stored in memory, or may be a standard defined in design rules.

In operation S10, a logic synthesis operation of generating netlist data D13 from register transfer level (RTL) data D11 may be performed. For example, a semiconductor design tool (eg, a logic synthesis tool) may perform logic synthesis from RTL data D11 written in a hardware description language (HDL) such as Verilog and VHSIC hardware description language (VHDL), referring to a standard cell library D12, thereby generating Netlist data D13 including netlist or bitstream.

In operation S20, a place and route (P&R) operation of generating the layout data D14 from the netlist data D13 with reference to the standard cell library D12 may be performed. In addition, in operation S20, a routing and routing operation of generating the layout data D14 from the netlist data D13 based on the acquired EM standard DR may be performed. In the routing and routing operation S20, operations of routing standard cells, generating interconnections, and generating layout data D14 may be performed. An example of operation S20 will be described below with reference to FIGS. 10 to 12 .

For example, a semiconductor design tool (eg, a P&R tool) may refer to the standard cell library D12 to route a plurality of standard cells according to the netlist data D13. For example, the semiconductor design tool may select one layout from a plurality of layouts of standard cells defined based on the netlist data D13, and may lay out the selected layout of the standard cells with reference to the data D12_a and D12_b. For example, driving cells may be laid out based on netlist data D13 including information on the integrated circuit IC with reference to the standard cell library D12.

The interconnect may electrically connect output pins and input pins of the standard cells, and may include, for example, at least one via and at least one routing wire. The layout data D14 may, for example, have a format such as GDSII, and may include geometric information about interconnects and standard cells.

In operation S30, optical proximity correction (OPC) may be performed. OPC may represent an operation of forming a pattern having a desired shape by correcting distortions in photolithography such as refraction caused by properties of light, which are included in the semiconductor process of manufacturing the integrated circuit IC. The pattern of the mask can be determined by applying OPC to the layout data D14. In an exemplary embodiment, the layout of the integrated circuit IC may be limitedly modified in operation S30. The process of restrictively modifying the integrated circuit IC in operation S30 may be a post-processing process of optimizing the structure of the integrated circuit IC, and may be referred to as a design revision process.

In operation S40, an operation of fabricating a mask may be performed. For example, by applying OPC to the layout data D14, a pattern of a mask can be defined to form a pattern provided in a multi-layer, and at least one mask (or photomask) for forming the multi-layer pattern can be manufactured.

In operation S50, an operation of manufacturing the integrated circuit IC may be performed. For example, a plurality of layers may be patterned by using at least one mask fabricated in operation S40, so that an integrated circuit IC may be fabricated. In an exemplary embodiment, operation S50 may include operations S51 and S52.

In operation S51, a front-end-of-line (FEOL) process may be performed. A FEOL process may refer to a manufacturing process in which various elements (eg, transistors, capacitors, resistors, etc.) are formed on a substrate. For example, the FEOL process may include operations to planarize and clean the wafer, operations to form channels, operations to form wells, operations to form gate lines, and operations to form source and drain electrodes.

In operation S52, a back end of line (BEOL) process may be performed. A BEOL process may refer to the process of connecting various elements (eg, transistors, capacitors, resistors, etc.) in a manufacturing process. For example, a BEOL process may include operations to silicide gate regions, source and drain regions, operations to add dielectric, operations to planarize, operations to form holes, operations to add metal layers, operations to form vias, and formation of passivation layer operations. The integrated circuit IC can then be packaged into a semiconductor package and used as part of various applications.

FIG. 10 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment. Operation S20 may include operations S21 to S25.

Referring to FIG. 10 , an allowable load level of each of a plurality of output pins of a plurality of output pins that are a standard unit of an operation unit (or a driving unit) for operating a plurality of load units may be acquired in operation S21 . In an exemplary embodiment, the allowable load level for each of the plurality of output pins may be pre-specified in a design rule, or may be information input from a designer. Alternatively, the allowable load level can be calculated based on the characteristics of the integrated circuit.

For example, referring to FIG. 1A , a first allowable load level of the first output pin OP1 and a second allowable load level of the second output pin OP2 may be obtained. In this case, the first load level may be the same as the second load level. Alternatively, for example, referring to FIG. 6 , a first allowable load level of the first output pin OP1e and a second allowable load level of the second output pin OP2e may be obtained. In this case, the first load level may be different from the second load level. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the first load level allowable by the first output pin OP1e may be the same as the second load level allowable by the second output pin OP2e.

In operation S23, the load cells may be grouped into a plurality of cell groups (eg, a first cell group and a second cell group) based on allowable load levels. For example, referring to FIG. 1A , the load cells may be divided into a first cell group STC1 and a second cell group STC2 based on a first load level and a second load level. For example, the load cells may be divided into a first cell group STC1 and a second cell group so as not to exceed the first load level and the second load level.

In operation S25, the plurality of output pins of the standard cell may be connected to the input pins of the load cell, respectively. For example, the input pin of at least one load cell included in the first cell group STC1 may be connected to the first output pin OP1, and the input pin of at least one load cell included in the second cell group STC2 may be connected to the second output Pin OP2.

FIG. 11 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment. Operation S20a may include operations S21a to S29a, and may be a simulation operation of checking whether the integrated circuit satisfies the EM standard. In an exemplary embodiment, operation S20a may be performed after operation S25 of FIG. 10 .

11 , in operation S21a, a load level of a cell group connected to each of a plurality of output pins of a standard cell as a driving unit for operating a plurality of load cells may be calculated. For example, referring to FIG. 1A , the load level of the first cell group STC1 connected to the first output pin OP1 may be calculated, and the load level of the second cell group STC2 connected to the second output pin OP2 may be calculated. In an exemplary embodiment, a load level of a routing path connected to each of the plurality of output pins may be calculated in operation S21a. The load level of the first routing path RP1 may be calculated based on the load level of the first cell group STC1, and the load level of the second routing path RP2 may be calculated based on the load level of the second cell group STC2.

In operation S23a, the calculated load level may be compared with a reference value of the load. The reference value of the load can be determined based on the EM standard of the design rule, and can be a pre-specified value. When the calculated load level is approximately equal to or less than the reference value of the load, layout data including a standard cell and a cell group connected to the standard cell may be generated in operation S25a (eg, D14 of FIG. 8 ).

When the calculated load level is greater than the reference value of the load, the standard unit may be changed to another standard unit for providing the same function and performance in operation S27a. For example, the standard cell may be changed from the first standard cell C1 of FIG. 1A to the second standard cell C2 of FIG. 1B based on the second data D12_1b and the third data D12_2b of the standard cell library D12 of FIG. 9 . Alternatively, for example, the standard cells may be changed from the first standard cell C1 of FIG. 1A to the third standard cell C3 of FIG. 3 based on the second data D12_1b and the fourth data D12_3b of the standard cell library D12.

Alternatively, for example, the standard cell may be changed from the first standard cell C1 of FIG. 1A to the fifth standard cell C5 of FIG. 5 based on the second data D12_1b and the fifth data D12_4b of the standard cell library D12. Accordingly, the load cells connected to the first standard cell C1 of FIG. 1A may be grouped into first to third cell groups STC1 to STC3 and may be connected to the first to third output pins OP1 to OP3.

Or, for example, in the case where the standard cell of operation S21a is a cell that outputs a specific output signal to one output pin, the standard cell may be changed from the standard cell of operation S21a based on the first data D12_a and the second data D12_1b of the standard cell library D12 from the standard cell of operation S21a The cell is changed to the first standard cell C1 of FIG. 1A. Therefore, the load cells connected to the standard cells of operation S21a may be grouped into first and second cell groups STC1 and STC2, and may be connected to first and second output pins OP1 and OP2.

In operation S29a, layout data D14 including a changed standard cell and a cell group connected to the changed standard cell may be generated. For example, the generated layout data D14 may include changed standard cells, a first cell group STC1, and a second cell group STC2. Therefore, in the method of manufacturing the integrated circuit according to the exemplary embodiment, the output load of the output pin of the standard cell as the driving unit does not exceed the reference value.

FIG. 12 is a flowchart illustrating an example of operation S20 of FIG. 8 according to an exemplary embodiment. Operation S20b may include operations S21b to S29b, and may be a simulation operation of checking whether the integrated circuit satisfies the EM standard. In an exemplary embodiment, operation S20b may be performed after operation S25 of FIG. 10 .

12 , in operation S21b, a load level of a routing path connected to each of a plurality of output pins of a standard unit that is a driving unit for operating a plurality of load units may be calculated. For example, referring to FIG. 1A , the load level of the first routing path RP1 connected to the first output pin OP1 may be calculated, and the load level of the second routing path RP2 connected to the second output pin OP2 may be calculated. In an exemplary embodiment, the load level of the first routing path RP1 may be calculated based on the load level of the first cell group STC1, and the load level of the second routing path RP2 may be calculated based on the load level of the second cell group STC2.

In operation S23b, the calculated load level may be compared with a reference value of the load. The reference value of the load can be determined based on the EM standard of the design rule, and can be a pre-specified value. When the calculated load level is approximately equal to or less than the reference value of the load, layout data including a standard cell and a routing path connected to the standard cell may be generated in operation S25b (eg, D14 of FIG. 8 ).

When the calculated load level is greater than the reference value of the load, the routing wiring connecting the standard cells to the cell group may be changed in operation S27b. For example, the first routing wirings M2R1 and M3R1 and the second via holes V2 shown in FIG. 1A that connect the first standard cell C1 to the first cell group STC1 may be changed to the first standard cell shown in FIG. 4 . C1 is connected to the first routing wirings M3R1 and M4R1, the second via V2, and the third via V3 of the first cell group STC1. Therefore, the routing wiring can be changed to a routing wiring including the pattern of the upper wiring layer. For example, the wiring layer in which the routing wiring is provided may be changed from a lower wiring layer to a relatively higher wiring layer.

In operation S29b, layout data D14 including a standard cell, a cell group connected to the standard cell, and a changed routing wiring may be generated. Therefore, in the method of manufacturing the integrated circuit according to the exemplary embodiment, the output load of the output pin of the standard cell as the driving unit does not exceed the reference value.

13 is a block diagram illustrating a computing system 1000 that includes a memory to store programs, according to an exemplary embodiment. At least some operations included in a method of fabricating an integrated circuit (eg, the methods of FIGS. 8 , 10 , 11 , and 12 ) according to an example embodiment may be performed by computing system 1000 .

Computing system 1000 may be a stationary computing system, such as a desktop computer, workstation, or server, or may be a portable computing system, such as a laptop computer. As shown in FIG. 13, computing system 1000 may include processor 1100, multiple input/output (I/O) devices 1200, network interface 1300, random access memory (RAM) 1400, read only memory (ROM) 1500, and Storage device 1600. The processor 1100 , a plurality of input/output (I/O) devices 1200 , the network interface 1300 , the RAM 1400 , the ROM 1500 and the storage device 1600 may be connected to the bus 1700 and may communicate with each other through the bus 1700 .

Processing chip 1100 may be referred to as a processing unit, and may include, for example, at least one core for executing any instruction set (eg, Intel Architecture 32 (IA-32), 64-bit Extended IA-32, x86-64, PowerPC, Sparc , MIPS, ARM, IA-64, etc.), such as microprocessors, application processors (APs), digital signal processors (DSPs), and graphics processing units (GPUs). For example, processor 1100 can access memory (eg, RAM 1400 or ROM 1500 ) through bus 1700 and can execute instructions stored in RAM 1400 or ROM 1500 .

The RAM 1400 may store a program 1420 for manufacturing an integrated circuit according to an exemplary embodiment, or may store at least a part of the program 1420 . Program 1420 may allow processor 1100 to perform at least some operations included in a method of fabricating an integrated circuit (eg, the method of FIG. 8). That is, program 1420 may include a plurality of instructions executable by processor 1100, and the plurality of instructions included in program 1420 may allow processor 1100 to perform at least some of the operations included in the flowchart described above with reference to FIG.

Storage device 1600 may retain data stored therein even if power to computing system 1000 is turned off. For example, storage device 1600 may include non-volatile storage devices, or may include storage media such as magnetic tapes, optical disks, or magnetic disks. Additionally, storage device 1600 may be attached to or detached from computing system 1000 . According to an exemplary embodiment, the storage device 1600 may store the program 1420 and the standard cell library described above, and the program 1420 or at least a portion thereof may be loaded from the storage device 1600 to the RAM 1400 before the processor 1100 executes the program 1420 . On the other hand, the storage device 1600 may store a file written in a program language and a program 1420 generated from the file by a compiler or the like, and at least a part of the program 1420 may be loaded into the RAM 1400 . Furthermore, as shown in FIG. 13, the storage device 1600 may store a database (DB) 1620, which may include information required for designing integrated circuits (eg, standard cell library D12 of FIG. 8).

The storage device 1600 may store data to be processed by the processor 1100 or data obtained through processing by the processor 1100 . For example, the processor 1100 may process data stored in the storage device 1600 based on the program 1420 to generate data, and may store the generated data in the storage device 1600 . For example, the storage device 1600 may store RTL data D11 , netlist data D13 and/or layout data D14 of FIG. 8 .

I/O devices 1200 may include input devices such as keyboards or pointing devices, and may include output devices such as display devices or printers. For example, the user can trigger the use of the processor 1100 to execute the program 1420, input the RTL data D11 and/or netlist data D13 of FIG. 8, and check the layout data D14 of FIG. 8 through the I/O device 1200.

Network interface 1300 may provide access to networks external to computing system 1000 . For example, a network may include multiple computing systems and communication links, which may include wired links, optical links, wireless links, or any type of link.

Although the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the claims. Various changes.

Claims (25)

1. An integrated circuit comprising: a standard unit, comprising a first output pin and a second output pin, the first output pin and the second output pin are configured to output the same output signal respectively; a first routing path connected to the first output pin; and a second routing path, connected to the second output pin, Wherein, the first routing path includes a first unit group, the first unit group includes at least one load unit, the second routing path includes a second unit group, and the second unit group includes at least one load unit, And the first routing path and the second routing path are electrically disconnected from each other outside the standard cell. 2. The integrated circuit of claim 1, wherein, The standard cell includes a first wiring layer including a plurality of patterns extending in a first horizontal direction and a second wiring layer including a plurality of patterns extending in a second horizontal direction , wherein the second wiring layer is disposed above the first wiring layer, and The first output pin and the second output pin are patterns of the second wiring layer. 3. The integrated circuit of claim 2, wherein, The first output pin and the second output pin pass through a first pattern of the plurality of patterns provided in the first wiring layer and are in contact with the first pattern and with the first pattern an output pin and a first via contacting the second output pin are electrically connected to each other, and In a layout view, the first pattern, the first output pin, and the second output pin have a ring shape. 4. The integrated circuit of claim 2, wherein, The first output pin and the second output pin pass through the first pattern of the plurality of patterns arranged in the first wiring layer, the plurality of patterns arranged in the second wiring layer a second pattern of the patterns and a first via in contact with the first pattern, the first output pin, the second output pin and the second pattern are electrically connected to each other, and In the layout view, the first pattern, the second pattern, the first output pin and the second output pin have a grid shape. 5. The integrated circuit of claim 2, wherein, The first routing path includes routing wiring including a pattern disposed in the second wiring layer and in contact with the first output pin, the pattern being different from a corresponding one of the second wiring layer on the pattern of the first output pin and the second output pin. 6. The integrated circuit of claim 2, wherein, the standard cell further includes a third wiring layer including a pattern extending in the first horizontal direction, wherein the third wiring layer is disposed over the second wiring layer, and The first routing path includes: routing wiring provided in the third wiring layer; and A via hole in contact with the routing wiring and the first output pin. 7. The integrated circuit of claim 2, wherein, The first output pin is electrically connected to a first pattern of the plurality of patterns provided in the first wiring layer and a first via contacting the first pattern and the first output pin hole, The second output pin is electrically connected to a second pattern of the plurality of patterns provided in the first wiring layer and a second pass that is in contact with the second pattern and the second output pin holes, and The first pattern and the second pattern are spaced apart from each other. 8. The integrated circuit of claim 1, wherein the standard cell further comprises: a third output pin configured to output the output signal, Wherein, the third routing path is connected to the third output pin and is electrically disconnected from the first routing path and the second routing path outside the standard cell. 9. The integrated circuit of claim 1, wherein, The standard unit is a clock gating unit configured to receive a clock signal to generate an internal clock signal. 10. A method of fabricating an integrated circuit, the method comprising: With reference to a library of standard cells, a driver unit is routed based on netlist data, the netlist data including information about the integrated circuit, wherein the integrated circuit includes the driver unit, and the driver unit includes a first output pin and a second output pin, the first output pin and the second output pin are configured to output the same output signal to a plurality of load units; obtaining the allowable load levels of the first output pin and the second output pin; grouping the load cells into a first cell group and a second cell group based on the allowable load level; and connecting the first output pin to the input pin of at least one load cell of the first cell group, and connecting the second output pin to the input of at least one load cell of the second cell group pin. 11. The method of claim 10, further comprising: After connecting the first output pin to the input pin of the at least one load cell of the first cell group and connecting the second output pin to the second cell group After the input pin of at least one load cell, calculating the load level of the first unit group and the load level of the second unit group; when the calculated load level is greater than a reference value, changing the drive unit based on the standard cell library; and Layout data including the changed drive cells, the first cell group, and the second cell group is generated. 12. The method of claim 11, wherein, the standard cell library includes information on a first standard cell and a second standard cell, each of the first standard cell and the second standard cell providing the same function as that of the drive unit, The first standard cell includes a first output pin and a second output pin spaced a first distance from each other in a first direction, and the second standard cell includes a second output pin spaced apart from each other in the first direction distance from the first output pin and the second output pin, and Changing the drive unit includes changing the first standard unit to the second standard unit. 13. The method of claim 11, wherein, the standard cell library includes information on a first standard cell and a second standard cell, each of the first standard cell and the second standard cell providing the same function as that of the drive unit, The first standard cell includes a plurality of first patterns arranged in the first wiring layer and first and second output pins respectively arranged in the second wiring layer, wherein, in the layout view, all the the first pattern and the first output pin and the second output pin have a ring shape, The second standard cell includes a plurality of first patterns provided in the first wiring layer, second patterns provided in the second wiring layer, and first patterns each provided in the second wiring layer an output pin and a second output pin, wherein, in the layout view, the first pattern, the second pattern of the second standard cell and the first output pin of the second standard cell and the second output pin has a grid shape, and Changing the drive unit includes changing the first standard unit to the second standard unit. 14. The method of claim 10, further comprising: After connecting the first output pin to the input pin of the at least one load cell of the first cell group and connecting the second output pin to the second cell group After the input pin of at least one load cell, calculating a load level of a first routing path including the first cell group and a first routing wire connecting the first cell group to the first output pin; calculating a load level of a second routing path including the second cell group and a second routing wire connecting the second cell group to the second output pin; When the calculated load level of the first routing path or the second routing path is greater than a reference value, changing at least one routing routing of the first routing routing and the second routing routing; and Layout data including the driving cells, the first cell group, the second cell group, and the changed routing wiring is generated. 15. The method of claim 14, wherein, Changing the at least one routing wiring of the first routing wiring and the second routing wiring includes changing the at least one routing wiring to include a pattern of an upper wiring layer. 16. The method of claim 10, further comprising: Obtain information about the allowable load level. 17. The method of claim 10, wherein, the standard cell library includes information on characteristics of a first output signal output from the first output pin and information on characteristics of a second output signal output from the second output pin, and The grouping of the load cells is performed based on the characteristic of the first output signal and the characteristic of the second output signal. 18. A computing system for fabricating an integrated circuit, the computing system comprising: a memory configured to store a standard cell library including information about a plurality of standard cells and a program for designing the integrated circuit; and a processor, configured to access the memory, wherein the processor is configured to perform the following operations by executing the program: Referring to the standard cell library, a drive unit is arranged, the drive unit includes a first output pin and a second output pin, and the first output pin and the second output pin each output to provide a plurality of loads the same output signal of the unit; grouping the load cells into a first cell group and a second cell group based on respective allowable load levels of the first output pin and the second output pin; and connecting the first output pin to the input pin of at least one load cell of the first cell group, and connecting the second output pin to the input of at least one load cell of the second cell group pin. 19. The computing system of claim 18, wherein, The standard cell library includes information about a first standard cell of the plurality of standard cells and a second standard cell of the plurality of standard cells, the first standard cell and the second standard cell each providing the same function as that of the drive unit, and The first standard cell includes a first output pin and a second output pin spaced a first distance from each other in a first direction, and the second standard cell includes a second output pin spaced apart from each other in the first direction distance from the first output pin and the second output pin. 20. The computing system of claim 18, wherein, The standard cell library includes information on standard cells among the plurality of standard cells, the standard cells provide the same function as that of the driving unit, and include first output pins each outputting the same output signal and the second output pin, The first output pin and the second output pin of the standard cell are patterns of a second wiring layer that is an upper layer with respect to the first wiring layer, and are passed through the wiring provided in the first wiring layer. a first pattern and a first via in contact with the first pattern and in contact with the first output pin and the second output pin of the standard cell are electrically connected to each other, and In a layout view, the first pattern, the first output pin of the standard cell, and the second output pin of the standard cell have a ring shape. 21. The computing system of claim 18, wherein, The standard cell library includes information on standard cells among the plurality of standard cells, the standard cells provide the same function as that of the driving unit, and include first output pins each outputting the same output signal and the second output pin, The first output pin and the second output pin of the standard cell are patterns of a second wiring layer that is an upper layer with respect to the first wiring layer, and are passed through the wiring provided in the first wiring layer. a first pattern, a second pattern disposed in the second wiring layer, and the first output pin in contact with the first pattern and with the standard cell, the second output of the standard cell the pins and the first vias of the second pattern contacts are electrically connected to each other, and In a layout view, the first pattern, the second pattern, the first output pin of the standard cell, and the second output pin of the standard cell have a grid shape. 22. The computing system of claim 18, wherein, The standard cell library includes information on standard cells among the plurality of standard cells, the standard cells providing the same functions as those of the driving unit, and including first to third outputs outputting the same output signal pin. 23. The computing system of claim 18, wherein, the standard cell library includes information on standard cells of the plurality of standard cells, the standard cells providing the same functions as those of the drive unit, and The standard cell includes first and second inverters each receiving a signal, a first output pin connected to an output terminal of the first inverter, and a first output pin connected to the second inverter the second output pin of the output terminal. 24. The computing system of claim 18, wherein the processor is further configured to: When at least one of the load level of the first cell group and the load level of the second cell group is greater than a reference value, changing the drive unit based on the standard cell library; and Layout data including the changed drive cells, the first cell group, and the second cell group is generated. 25. The computing system of claim 18, wherein the processor is further configured to: calculating a load level of a first routing path including the first cell group and a first routing wire connecting the first cell group to the first output pin; calculating a load level of a second routing path including the second cell group and a second routing wire connecting the second cell group to the second output pin; When the calculated load level of the first routing path or the second routing path is greater than a reference value, changing at least one of the first routing wiring and the second routing wiring; and Layout data including the driving cells, the first cell group, the second cell group, and the changed routing wiring is generated.

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