CN111832234B

CN111832234B - A chip layout method

Info

Publication number: CN111832234B
Application number: CN201910231110.1A
Authority: CN
Inventors: 林贵同; 曹攀
Original assignee: Beijing Puanxin Technology Co ltd
Current assignee: Beijing Puanxin Technology Co ltd
Priority date: 2019-03-26
Filing date: 2019-03-26
Publication date: 2024-07-12
Anticipated expiration: 2039-03-26
Also published as: CN111832234A

Abstract

The embodiment of the invention provides a chip layout method, which comprises the following steps: setting a non-replicable function unit matrix, namely a PUF unit matrix, in a chip; peripheral circuits are arranged on the periphery of the PUF unit matrix; and a grounding protection groove is arranged between the PUF unit matrix and the peripheral circuit. By arranging the grounding protection groove between the PUF unit matrix and the peripheral circuit unit, the instability caused by the influence of the peripheral circuit on the mapping of the PUF unit matrix function is overcome, and the failure of the PUF chip caused by the instability is avoided; this layout design method is suitable for all types of PUF chips.

Description

Chip layout method

Technical Field

The invention belongs to the field of electricity, and particularly relates to a chip layout method.

Background

Non-replicable function chips (PUF chips) have been demonstrated for identification, authentication and encryption/decryption functions on internet of things and other terminal devices. The PUF chip is a physical unclonable function, the function mapping relation between input (challenge)/output (response) is realized by a physical or analog method, and unlike a computer and mathematical function mapping relation, the function mapping relation of the PUF chip can be influenced by parameters such as external temperature, bias voltage and the like, and the same input (challenge) output (response) is slightly different, so that the PUF chip is plagued in the application of identification, authentication and encryption, and especially when the response stability of the PUF chip exceeds a certain degree, the PUF chip is invalid and becomes completely unusable.

The key component inside the PUF chip is a matrix composed of PUF units, the PUF units output 1bit response to 1bit challenge, the existing PUF matrix is composed of 16×16, 8×16, 32×16 or the like, the key component of the PUF chip is the key component, the fluctuation of the performance of each component in the microelectronic manufacturing process is utilized, the function relation of the challenge/response of each unit is random, but the function relation is expected to be stable, and the function mapping relation of different working environments is kept stable at different moments.

However, since the PUF chip needs to be provided with other peripheral circuits such as a readout circuit, a power supply bias circuit, and the like around the PUF cell matrix in addition to the PUF cell matrix portion, the peripheral circuits inevitably introduce noise during operation, and also introduce non-uniformity of bias voltage and the like through substrate crosstalk, which may cause non-uniformity of electrical characteristics of the PUF cell matrix, and such non-uniformity is unstable, which may cause failure of functional mapping characteristics of the PUF cell matrix. Especially for the peripheral cells of the PUF cell matrix. While these perimeter PUF cells account for more than 10% of the entire PUF cell matrix, for example 32 x 16, 48/512≡10%. This can easily lead to failure of more than 10% of the PUF cell matrix.

Disclosure of Invention

The embodiment of the invention provides a chip layout method which is used for overcoming the failure of a PUF chip caused by the instability of PUF unit matrix function mapping influenced by peripheral circuits, and is suitable for all types of PUF chips.

In order to achieve the above object, an embodiment of the present invention provides a chip layout method, including:

setting a non-replicable function unit matrix, namely a PUF unit matrix, in a chip;

Peripheral circuits are arranged on the periphery of the PUF unit matrix;

And a grounding protection groove is arranged between the PUF unit matrix and the peripheral circuit.

The technical scheme has the following beneficial effects: by adopting the bias layout method of the peripheral units of the PUF unit matrix, namely by arranging a grounding protection groove between the PUF unit matrix and the peripheral circuit units, the instability caused by the influence of the peripheral circuit on the mapping of the PUF unit matrix function is overcome, and the failure of the PUF chip caused by the instability is avoided; this layout design method is suitable for all types of PUF chips.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a chip layout method according to an embodiment of the invention;

FIG. 2 is a schematic layout diagram of a chip layout method according to an embodiment of the present invention;

fig. 3 is a cross-sectional view of a ground shield groove in accordance with an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, a flowchart of a chip layout method according to an embodiment of the present invention is shown, where the method includes:

s101, setting a non-replicable function unit matrix, namely a PUF unit matrix, in a chip;

s102, arranging a peripheral circuit around the PUF unit matrix;

And S103, setting a grounding protection groove between the PUF unit matrix and the peripheral circuit.

The centrally located PUF cell matrix 10 of fig. 2 is affected by the peripheral readout circuitry 34, the addressing circuitry 31, the control circuitry 32 and the bias circuitry 33, and the functional mapping characteristics of the PUF cell matrix 10 are affected not only by the microelectronic fabrication process but also by these peripheral circuitry. The effect of peripheral circuitry is not stable and is undesirable. The method of shielding these peripheral circuits is to protect the PUF cell matrix by grounding.

The ground protection slot 20 effectively shields the PUF cell matrix 10 from the effects of these peripheral circuits.

Further, the ground protection groove 20 has a groove structure, and the PUF cell matrix 10 is disposed in the groove of the ground protection groove 30.

The arrangement of the groove structure can effectively shield the influence of the peripheral circuit units on the PUF cell matrix 10.

Further, the distance between the edge of the PUF cell matrix 10 and the ground guard groove 20 is set in the range of 0.5 to 2 microns.

The distance between the edge of the PUF cell matrix 10 and the ground protection slot 20 is set between 0.5 micrometers and 2 micrometers, so that the effect of ground protection is achieved under the condition of ensuring structural design integrity and feasibility.

Further, the ground protection groove 20 is formed by a highly doped P-type layer 21, a ground metal 22 and a silicon substrate 23.

Further, ohmic contact is provided between the ground metal 22 and the highly doped P-type layer 21.

The entire PMOS and NMOS units 11 are surrounded by the p+ -type doped region, i.e., the highly doped P-type layer 21, and the surrounding metal wiring, i.e., the ground metal 22, in contact with the highly doped P-type layer 21, and the metal wiring in contact with the highly doped P-type layer 21 is grounded. The middle PMOS and NMOS constitute the PUF unit.

Further, the outer ring PUF cells of the PUF cell matrix 10 are set to a virtual state.

Further, the outer two rings of PUF cells of the PUF cell matrix 10 are set to a virtual state.

Setting Dummy virtual states for all peripheral PUF cells in the PUF cell matrix 10;

Taking a 32×16 PUF cell matrix as an example, if 32×16=512 PUF cell matrices are required, 33×17=561 PUF cell matrices or 34×18=612 PUF cell matrices should be set at the time of design. The peripheral one-turn PUF cells or two-turn PUF cells are set to be in a Dummy state, so that the function mapping characteristic of the 32×16=512 PUF cell matrices of the inner turn is protected to be stable.

Further, an oxide isolation layer 12 is provided between PUF cells 11 of the PUF cell matrix 10.

The arrangement of the grounding protection groove and the virtual state PUF units is increased, the cost of the PUF chip is not increased, the silicon chip area occupied by the increased grounding protection groove and the number of the Dummy PUF units is negligible, but the stability and the reliability of the PUF chip are improved. The error correction requirement in the PUF is greatly reduced, and the yield of the PUF chip is improved.

It should be understood that the specific order or hierarchy of steps in the processes disclosed are examples of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate preferred embodiment of this invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. As will be apparent to those skilled in the art; various modifications to these embodiments will be readily apparent, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, as used in the specification or claims, the term "comprising" is intended to be inclusive in a manner similar to the term "comprising," as interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean "non-exclusive or".

Those of skill in the art will further appreciate that the various illustrative logical blocks (illustrative logical block), units, and steps described in connection with the embodiments of the invention may be implemented by electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software (interchangeability), various illustrative components described above (illustrative components), elements, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design requirements of the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation is not to be understood as beyond the scope of the embodiments of the present invention.

The various illustrative logical blocks or units described in the embodiments of the invention may be implemented or performed with a general purpose processor, a digital signal processor, an Application Specific Integrated Circuit (ASIC), a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general purpose processor may be a microprocessor, but in the alternative, the general purpose processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. In an example, a storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC, which may reside in a user terminal. In the alternative, the processor and the storage medium may reside as distinct components in a user terminal.

In one or more exemplary designs, the above-described functions of embodiments of the present invention may be implemented in hardware, software, firmware, or any combination of the three. If implemented in software, the functions may be stored on a computer-readable medium or transmitted as one or more instructions or code on the computer-readable medium. Computer readable media includes both computer storage media and communication media that facilitate transfer of computer programs from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. For example, such computer-readable media may include, but is not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store program code in the form of instructions or data structures and other data structures that may be read by a general or special purpose computer, or a general or special purpose processor. Further, any connection is properly termed a computer-readable medium, e.g., if the software is transmitted from a website, server, or other remote source via a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless such as infrared, radio, and microwave, and is also included in the definition of computer-readable medium. The disks (disks) and disks (disks) include compact disks, laser disks, optical disks, DVDs, floppy disks, and blu-ray discs where disks usually reproduce data magnetically, while disks usually reproduce data optically with lasers. Combinations of the above may also be included within the computer-readable media.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A chip layout method, characterized in that the method comprises:

A non-copyable functional unit matrix, i.e., a PUF unit matrix, is set in the chip;

Disposing a peripheral circuit around the PUF unit matrix;

A ground protection groove is provided between the PUF unit matrix and the peripheral circuit;

The grounding protection groove is a groove structure, and the PUF unit matrix is arranged in the groove of the grounding protection groove; the distance between the edge of the PUF unit matrix and the grounding protection groove is set in the range of 0.5 microns to 2 microns; the grounding protection groove includes a highly doped P-type layer, a grounding metal and a silicon substrate; the grounding metal and the highly doped P-type layer are set to be in ohmic contact; the outer circle PUF unit of the PUF unit matrix is set to a virtual state.

2. The chip layout method according to claim 1, characterized in that:

The outer two circles of PUF units in the PUF unit matrix are set to a virtual state.

3. The chip layout method according to any one of claims 1 to 2, characterized in that:

An oxidation isolation layer is provided between the PUF units of the PUF unit matrix.

4. The chip layout method according to claim 3, characterized in that:

The peripheral circuit includes: a readout circuit, an address selection circuit, a control circuit and a bias circuit.