CN111835059A - Buck Boost Charger Configuration with Reverse Boost Mode - Google Patents

Abstract

Embodiments of the present disclosure relate to a buck boost charger configuration with a reverse boost mode. The present embodiments relate to methods and apparatus for operating battery chargers in computing systems with certain system load requirements, battery configurations, and external device power support. According to some aspects, the present embodiments provide methods and apparatus for providing a reverse boost mode of operation when a battery charger is providing system power from a battery, such as when an adapter is not connected. A reverse boost mode of operation according to an embodiment provides a regulated output voltage, allowing a load such as a CPU to operate at maximum performance even when the battery has been discharged below a threshold discharge level.

Description

Buck Boost Charger Configuration with Reverse Boost Mode

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of US Non-Provisional Patent Application No. 16/452,414, filed June 25, 2019, which claims priority to US Provisional Patent Application No. 67/720,650, filed August 21. This application also claims priority to US Provisional Patent Application No. 62/837,649, filed April 23, 2019, all of which are incorporated herein by reference in their entirety.

technical field

The present embodiments relate generally to mobile and computing devices, and more particularly to battery charger applications for such devices that manage and/or defer system shutdown conditions during battery-only mode in order to optimize system performance.

Background technique

Battery chargers, especially those for mobile computing devices, are responsible for performing or supporting a variety of operating conditions and applications. For example, conventional mobile computing devices, such as laptops or notebook computers, include plug-in ports for power adapters. When the adapter is plugged into this port, the battery charger is responsible for charging the battery using the adapter voltage specified by the mobile computing device manufacturer. Likewise, the battery charger is responsible for allowing the mobile computing device to operate using the energy stored in the battery when no adapter is plugged into the dedicated port, and also supports shutdown conditions or near shutdown conditions when battery levels are too low. While some traditional methods are acceptable to support these shutdown conditions, there are more opportunities for improvement.

SUMMARY OF THE INVENTION

In one or more embodiments, the method and apparatus allow the battery-only mode of operation to transition from ideal diode mode to reverse boost mode when the battery is discharged below a threshold level of battery capacity. Among other things, this prevents system downtime issues and extends maximum CPU performance cycles.

Description of drawings

These and other aspects and features of the present embodiments will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating an example device or system to which the present embodiments may be applicable.

Figure 2 is a diagram illustrating some of the problems in a standard battery charger application.

FIG. 3 is a diagram illustrating an example aspect of a reverse boost mode according to the present embodiment.

4 is a schematic diagram illustrating an example implementation of the present embodiment in a battery charger architecture including an integrated circuit.

5 is a flowchart illustrating an example method according to an embodiment.

Detailed ways

The present embodiments will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of embodiments to enable those skilled in the art to practice embodiments and alternatives that are apparent to those skilled in the art. Notably, the following figures and examples are not meant to limit the scope of the present embodiments to a single embodiment, but other embodiments may be implemented by interchanging some or all of the described or illustrated elements . Also, where some elements of the present embodiment may be partially or fully implemented using known components, only those parts of these known components that are necessary for understanding the present embodiment will be described, and the description of these known components will be omitted in order to avoid obscuring this example. As will be apparent to those skilled in the art, unless otherwise indicated herein, embodiments described as implemented in software are not limited thereto, but may include embodiments implemented in hardware or a combination of software and hardware, and vice versa . In this specification, embodiments showing a single component are not to be considered limiting; rather, unless expressly stated otherwise herein, this disclosure is intended to cover other embodiments comprising multiples of the same component, and vice versa. Furthermore, applicants do not intend for any term in the specification or claims to have an uncommon or special meaning unless explicitly set forth herein. Further, the present embodiments cover current and future known equivalents of the known components referred to herein by way of illustration.

As stated above, in accordance with certain aspects, the present embodiments relate to methods and apparatus for operating a battery charger in a computing system having certain system load requirements, battery configurations, and external device power support. According to other aspects, the present embodiments provide methods and apparatus for providing a reverse boost mode of operation when a battery charger is providing system power from a battery, such as when an adapter is not connected. A reverse boost mode of operation according to an embodiment provides a regulated output voltage, allowing a load such as a CPU to operate at maximum performance even when the battery has been discharged below a threshold discharge level.

FIG. 1 is a block diagram illustrating aspects of an example system 100 incorporating the present embodiments. System 100 may be a computing device such as a notebook computer (eg, MacBook, Ultrabook, etc.), laptop computer, tablet or tablet computer (iPad, Surface, etc.), etc., power bank, Universal Serial Bus Type C (USB- C) Interface platforms, or any system that uses batteries that are sensitive to power rails. In these and other embodiments, the system 100 includes a load 116, which may include a CPU 124 running a conventional operating system such as Windows, Android, or Apple iOS, and may be an x86 processor from Intel, AMD, or other manufacturers , and other processors, DSPs, GPUs, etc. made by Freescale, Qualcomm. The load 116 may also include a core voltage regulator 122 for supplying a regulated voltage from the output VSYS/VOUT of the charger 102 to the CPU 124 . It should be apparent that system 100 may include many other components not shown, such as solid state drives and other disk drives, memory, peripherals, displays, user interface components, and the like. According to certain aspects, the system 100 in which this embodiment may find particularly useful application has operating power requirements that may exceed the power limits of technologies such as USB-A (eg, over 60 watts). However, the present embodiment is not limited to application in such a system.

As shown, system 100 includes battery 104 and battery charger 102 . In an embodiment, the charger 102 is a step-up step-down narrow output voltage DC (NVDC) charger (ie, a DC-DC converter). According to certain general aspects, during normal operation of the system 100 , the battery charger 102 is configured to charge the battery 104 when the power adapter is plugged into the port 106 . Preferably, in addition to charging battery 104, battery charger 102 is adapted to convert power from the adapter to a voltage suitable for supplying components of system 100, including load 116 (eg, as known in the art). buck mode, boost mode, or buck-boost mode). According to some other general aspects, the battery charger 102 is configured to manage the supply of power from the battery 104 to the load 116 and/or peripherals connected to the port 106 when the power adapter is not plugged into the port 106 (eg, in a buck mode) , boost mode or buck-boost mode). More details of the battery charger 102 according to the present embodiment are provided below.

In other embodiments of notebook computers (eg, Ultrabooks) and system 100, batteries 104 may be rechargeable 1S/2S/3S/4S (ie, 1-cell stack, 2-cell stack, 3-cell stack, or 4-cell stack) Lithium-ion (Li-ion) batteries. In these and other embodiments, port 106 may be a USB port, such as a USB Type-C (USB-C) port or a USB Power Delivery (USB PD) port. Although not shown in FIG. 1, a switch between port 106 and charger 102 may also be provided to controllably couple power from an adapter connected to port 106 to charger 102, or alternatively, to Charger 102 and/or port 106 provide system power. Such switches may also include, or be implemented by, active devices, such as back-to-back FETs (not shown).

As further shown, an example system 100 in which the present embodiment may find particularly useful application includes an embedded controller (EC) 112 . EC 112 includes functionality for controlling certain operations of charger 102 and is generally responsible for managing the power configuration of system 100 (eg, depending on whether a power adapter is connected to port 106 , such as a port controller (not shown) coupled to port 106 out) detected and reported), receives the status of the battery 104 from the fuel gauge 114, and communicates the battery charge level and other operational control information (eg, via the SMbus or I2C interface) to the charger 102 and CPU 124 (eg, via the SMbus or I2C interface), such as It will become more apparent from the description below.

According to certain aspects, the applicant has recognized various problems that plague conventional battery chargers, such as the battery charger shown in FIG. 1, and/or adapters that include voltage regulators or converters.

For example, referring to FIG. 1 , the charger 102 may be configured to operate in a “battery only” mode in a standard battery charger application, eg, when the adapter is not plugged into the port 106 . During this time, the charger 102 provides the battery voltage to VSYS/VOUT by causing current to be drawn from the battery 104 (eg, using an "ideal diode" mode known to those skilled in the art). Also, during this time, the fuel gauge 114 continuously monitors the battery voltage and sends battery charge information to the EC 112 .

Figure 2 provides two graphs illustrating system operation in this "battery only" mode. The top graph 202 illustrates battery voltage (shown by curve 222 ) as a function of time, while the bottom graph 204 illustrates battery discharge current (shown by curve 224 ) as a function of the same time. It can be seen that the battery discharge current (shown by curve 224 ) varies over time based on the operating requirements of the load 116, but never exceeds the maximum discharge current level 226 (eg, limited by the CPU 124 or core VR 122). At the same time, the charger 102 is responsible for providing power from the battery 104 (eg, using an "ideal diode" mode known to those skilled in the art) to the output node VOUT/VSYS. Meanwhile, in this conventional case, core VR 122 operates to provide a regulated voltage to CPU 124 from node VOUT/VSYS.

Meanwhile, referring to FIG. 1 , the cell voltage shown by curve 222 is continuously monitored by the fuel gauge 114 and this information is provided to the EC 112 . In some implementations, the EC 112 determines the maximum and minimum capacities of the battery 102 based on the number of cells used to implement the battery 102 . For example, in the case of a two-cell (eg, 2S) battery, the maximum battery voltage is 2×4.2V=8.4V, and the minimum battery voltage is 2×3V=6V. In such an example, a 30% charged battery level is slightly above 6V.

This information is provided to the EC 112 and communicated to the CPU 124 when the battery is discharged to about 30% of the battery capacity as shown at time 206 (as monitored by the fuel gauge 114 ). At this point, the CPU 124 must limit the system load current from a maximum level 226 to a reduced level 228 to prevent an imminent system shutdown. As further shown in Figure 2, if the battery continues to discharge without supplemental power from the adapter or elsewhere, then at a subsequent time 208, the battery voltage will reach a minimum charge level (eg, in the 2S example described above, approximately 5V), at which point CPU 124 and/or EC 112 have no choice but to shut down the system (eg, via a power-on-reset (POR)).

In accordance with certain aspects, Applicants should recognize that, as described above, it would be beneficial to defer or eliminate performance degradation of CPU 124 during the period between times 206 and 208 . For example, in gaming laptops and other applications, if CPU performance is constrained, these systems may struggle to run games at low battery levels, which is unacceptable for gamers/users. Similar questions apply to web content developers and/or video editors. Also, even during the period between times 206 and 208 , when operating in the conventional “ideal diode” mode, the load 116 only receives lower and lower battery voltages as indicated by the curve 222 . As such, the load 116 is susceptible to "load insertion" (eg, when other devices other than the CPU 124 are connected to the system 100) or other events that may cause a spike in battery discharge current. Such an event may cause the system voltage seen by the load 116 to drop below a specified minimum battery voltage (eg, a voltage drop due to an ideal diode's increased drain-source current and drain-source resistance).

In accordance with these and other aspects, embodiments provide a reverse boost mode (as opposed to a traditional "ideal diode" mode) to allow the CPU 124 to continue to operate at full performance and with voltage regulated, even if battery levels have dropped to below the specified charge level, thus solving these and other problems. While operation in reverse boost mode according to an embodiment may require shutting down the system completely faster than conventional methods, in many situations such as those described above, this compromise is desirable.

FIG. 3 illustrates an example aspect of a reverse boost mode according to the present embodiment. Similar to FIG. 2 , the top graph 302 illustrates battery voltage (shown by curve 322 ) as a function of time, while the bottom graph 304 illustrates battery discharge current (shown by curve 324 ) as a function of the same time ). It can be seen that the battery discharge current (shown by curve 324 ) varies over time based on the operational requirements of the load 116 , but never exceeds the maximum discharge current level 326 (eg, as described above, by the CPU 124 or the core VR 122 ) limits). Unlike the conventional operation shown in FIG. 2 , it can be seen from FIG. 3 that the reverse boost mode according to an embodiment is enabled when the battery is discharged below about 30% of the battery capacity at time 306 . As a result, system shutdown can be prevented for an extended period of time up to time 308 without any CPU performance limitations and voltages regulated (as opposed to battery voltage only), albeit at a faster rate than conventional methods by discharging batteries to The minimum level of cost, as shown in segment 322-A of curve 322. As described in more detail below, in one example of a reverse boost mode according to an embodiment, one or more battery control transistor (eg, FET) and bypass transistor (FET) pairs are controlled in some manner , to regulate the system voltage to any value and prevent system shutdown without limiting CPU performance.

FIG. 4 is a schematic block diagram illustrating one example of a detailed implementation of the present embodiment in a battery charger architecture, such as the battery charger architecture shown in FIG. 1 , using integrated circuit 402 . Although the illustrated example charger 102 to be described in more detail below is a buck boost charger, the present embodiments are not limited to this example and may include other types of chargers, such as buck chargers and/or boost charger.

The example charger 102 in these embodiments includes a power switch transistor including a field effect transistor (FET) Q1 402 with its drain coupled to node 404 and its source coupled to an intermediate node 406 . The drain of the other FETQ2 is coupled to node 406 and its source is coupled to a reference (eg, GND). The example charger 102 also includes FET Q4 407, whose drain is coupled to node 412 and whose source is coupled to intermediate node 405; and FET Q5 408, whose drain is coupled to node 405 and whose source is coupled to GND. Those skilled in the art will appreciate that FETs Q1 402, Q2 403, Q4 407, and Q5 408 are coupled in a buck-boost configuration, and more specifically, an H-bridge buck-boost configuration. In other embodiments, any other type of buck-boost configuration known in the art may also be used.

Additionally, charger 102 includes FET Q6 416 with its drain coupled to node 404 and its source coupled to intermediate node 420 ; and FET Q7 418 with its source coupled to node 420 and its drain coupled to output node 410 . As mentioned above, FETs Q6 416 and Q7 418 may implement back-to-back bypass FETs that provide additional control for allowing power to be delivered from the adapter to the load. Other examples may also include a single bypass FET. This arrangement of bypass FETs results in a configuration with a common source 415 (also referred to as a bypass source). The gates of FET Q6 416 and FET Q7 418 are also coupled together and may be referred to as bypass gate 417 . Bypass source 415 and bypass gate 417 are both coupled to IC 402 to allow IC 402 to control the operation of the bypass FET. Charger 102 includes inductor L1 coupled between node 406 and node 405 . As shown, output node 410 provides system voltage VSYS to a system load 416, such as a CPU (not shown).

In this example, the charger 102 also includes a pair of battery control transistors FET Q3 414 (eg, NGATE) and FETQ8 426 (eg, BGATE). NGATE FET Q3 414 has its drain coupled to node 410 and its source coupled to node 412. BGATE FET Q8 426 has its drain coupled to node 412 and its source coupled to battery 104 via resistor R2 427 . As mentioned above, FETs Q3 414 and Q8 426 may implement one or more battery control transistors. The gates of FETs Q3 414 and Q8 426 are coupled to IC 402 for controlling charging and discharging of rechargeable battery 104 . For example, when the power adapter is not connected, FETs Q3 414 and Q8 426 may be turned on to allow power from battery 104 to be provided to the system load via node 410 . As known to those skilled in the art, when a power adapter is connected, FET Q3 414 can be turned on and FET Q8 426 can be controlled in a linear fashion to control charging of rechargeable battery 104 .

FETs Q1 402, Q2 403, Q4 407, Q5 408, Q3 414, Q6 416, Q7 418 and Q8 426 are shown implemented using N-channel MOSFETs, although other types of switching devices are contemplated, such as P-channel devices, other Similar forms (eg, FETs, MOS devices, etc.), bipolar junction transistors (BJTs), etc., insulated gate bipolar transistors (IGBTs), etc.

As shown, IC 402 according to the present embodiment includes a normal mode module 422 and a reverse boost mode module 424, which control transistor Q1 402 via an output connection to its gate during normal mode and reverse boost mode, respectively , Q2 403, Q4 407, Q5 408, Q3 414, Q6 416 and Q7 418 operations. For ease of illustration, modules 422 and 424 are shown separately, but the modules 422 and 424 may include common circuitry that includes circuitry that is also shared by modules used by IC 202 to control other operations of system 100 . Additionally and relatedly, although the present description focuses on the IC 402 operating in a battery-only mode (such as when an adapter is not connected to the port 106 ), it should be apparent that the IC 402 may be included for use in other modes, such as Other modules and/or functions that operate when a power adapter is connected to port 106 and battery 104 is charging). Details of such additional functionality and/or circuitry are omitted herein for clarity of the present embodiments.

The normal mode module 422 operates FETs Q1 402, Q2 403, Q4 407, Q5 408 and Q3 414 in buck mode or boost mode or buck boost mode to regulate the output voltage VSYS to a narrow DC range to stabilize the system bus voltage. In this mode, bypass FETs Q6 416 and Q7 418 are turned off and maintained in the off state, while NGATE FET Q3 414 is turned on. Module 422 may operate when system power is provided from an adapter, a battery, or a combination of the two (eg, where only the battery 104 is connected, the adapter is connected only to the port 106, or a combination of both). As such, in an embodiment, the module 422 is configured for the battery 104 configuration at various power and load conditions, such as a 2-cell Li-ion battery, a 3-cell Li-ion battery, or a 4-cell Li-ion battery, with an input voltage in the range of 3.2V to 23.4V and the system output voltage VSYS range is 2.4V to 18.304V).

More specifically, in battery-only mode (eg, as communicated to IC 402 by EC 112 ), module 422 first operates to turn off FETs Q1 402 , Q2 403 , Q4 407 , Q5 408 , and turn off bypass FET Q6 416 and Q7 418 , and turn on NGATE FET Q3 414 and BGATE FET Q8 426 to achieve a traditional “ideal diode” mode where power from battery 104 is provided directly to node 410 . Module 422 that performs this "ideal diode" mode operation (eg, maintaining NGATE FET Q3 414 and BGATE FET Q8 426 in a substantially ON state) can be implemented using various known techniques, and is therefore herein for the sake of clarity of the invention , omitting its further details. During this mode, module 422 does not provide any voltage regulation, so the voltage from battery 104 is provided to node 410 . However, it should be apparent that this voltage can be reduced by multiplying the current drawn from the battery 104 by the drain-source resistance of resistor R2 427 and NGATE FET Q3 414 and BGATE FET Q9 426 . Also, as shown in Figures 2 and 3, the battery voltage will decrease over time as the battery discharges.

However, according to aspects of this embodiment, when a predefined battery charge level (such as 30% of maximum battery charge, as detected by the fuel gauge 114 ) is broken through the IC 402 (eg, from the EC 112 ) ) When a "reverse boost enable" signal is received, the normal mode module 422 is disabled and the reverse boost mode module 424 is activated. During this mode, module 424 turns off NGATE FET Q3 414 (eg, maintains NGATE FET in the OFF state), turns on bypass FETs Q6 416 and Q7 418, and operates FETs Q1 402, Q2 in reverse boost switching mode 403 , Q4 407 and Q5 408 to provide the regulated voltage to the load via the output node 410 . Those skilled in the art will understand how to use switching transistors such as Q1 402, Q2 403, Q4 407, Q5 408 and Q5 408 and control signals such as pulse width modulated (PWM) signals to achieve a boost mode of operation, so Further details thereof are omitted herein for the sake of clarity.

FIG. 5 is a flowchart illustrating an example reverse boost mode method that may be implemented by a charger 102 , such as the charger shown in FIG. 4 , according to an embodiment.

For illustration, FIG. 5 shows the charger 102 operating in a normal battery only mode in block 502 . For example, this may be in response to IC 402 receiving an indication from EC 112 (eg, via I2C, SMBus, etc.) that the adapter is not connected to port 106 . In the example of FIG. 4 , the normal battery only mode may include a normal mode module 422 that turns off FETs Q1 402 , Q2 403 , Q4 407 and Q5 408 , turns off bypass FETs Q6 416 and Q7 418 , and turns on FET Q3 414 and Q8 426 to enable “ideal diode” mode to provide the voltage from battery 104 to output node 410 .

Block 504 instructs the EC 112 to continuously monitor information from the fuel gauge 114 . In the box, the EC 112 compares information from the fuel gauge 114 to determine whether the battery 104 has been discharged to a predetermined level, such as 30% of the maximum battery charge, based on, for example, the number of cells implementing the battery 104 .

If the EC 112 determines that the threshold discharge level has been reached, then in block 506 the EC 112 may request the charger 102 to transition from the normal battery only mode to the reverse boost mode by signaling that reverse boost is enabled. EC 112 may do so by writing certain values (eg, one or more bits of one or more control registers of charger 102 ) into registers via SMBus. EC 112 may also perform certain operations to direct charger 102 to regulate VSYS to some target voltage (eg, via SMbus). In other embodiments, the charger 102 determines the target voltage independently (eg, by using information about adapter voltage levels).

In response to the indication to request reverse boost mode in block 506 , charger 102 reverse boost mode operation of charger 102 begins in block 508 . The block includes disabling the operation of the normal mode module 422 and enabling the operation of the reverse boost module 424 . During this mode, module 424 turns off FET Q3 414, turns on bypass FETs Q6 416 and Q7 418, and operates FETs Q1 402, Q2 403, Q4 407, and Q5 408 in reverse boost switching mode to pass the output Node 410 provides a regulated voltage to the load that corresponds to the target voltage and is higher than the battery voltage. To perform this voltage regulation, module 424 may monitor the voltage at output node 410 using a feedback circuit (not shown) and generate PWM switches to Q1 402, Q2 403, Q4 407, Q5 408 using techniques known to those skilled in the art Signal.

It should be noted that the reverse boost mode of this embodiment can be fire-and-forget by the customer, thus eliminating the need for overhead processing for monitoring and protecting the system or battery.

Although the embodiments of the present invention have been described in detail with reference to the preferred embodiments thereof, it should be apparent to those skilled in the art that the form may be modified without departing from the spirit and scope of the present disclosure. and details to be changed and modified. The appended claims are intended to cover such changes and modifications.

Claims (15)

1. A method for operating a battery charger in a battery-only mode when a battery is being used to power a load, the method comprising:

receiving a first indication of the battery-only mode;

in response to the first indication, causing a voltage from the battery to be provided to the load via a battery control transistor pair;

receiving a second indication that the battery has been discharged below a threshold level; and

in response to the second indication, causing the regulated voltage to be provided from the battery to the load using a plurality of switching transistor and at least one bypass transistor pair, the plurality of switching transistors coupled in a buck-boost configuration, distinct from the battery control transistor pair.

2. The method of claim 1, wherein causing the regulated voltage to be provided to the load comprises: operating the battery charger in a reverse boost mode.

3. The method of claim 2, wherein the reverse boost mode comprises maintaining an NGATE FET of the battery control transistor pair in an off state and maintaining the bypass transistor pair in an on state.

4. The method of claim 1, wherein causing the voltage from the battery to be provided to the load comprises: operating the battery charger in an ideal diode mode.

5. The method of claim 4, wherein the ideal pattern comprises: maintaining the battery control transistor pair in an on state and maintaining the bypass transistor pair in an off state.

6. The method of claim 1, wherein receiving the first indication and the second indication comprises: a signal is received from an external entity.

7. The method of claim 6, wherein the external entity comprises an embedded controller.

8. A battery charger having a battery-only mode when a battery is being used to power a load, comprising:

a normal mode module configured to cause voltage from the battery to be provided to the load via a battery control transistor pair; and

a reverse boost module configured to cause a regulated voltage to be provided from the battery to the load using a plurality of switching transistor and at least one bypass transistor pair in response to an indication that the battery has discharged below a threshold level, the plurality of switching transistors coupled in a buck-boost configuration, distinct from the battery control transistor pair.

9. The battery charger of claim 8, wherein the reverse boost module is configured to cause the regulated voltage to be provided to the load by operating the battery charger in a reverse boost mode.

10. The battery charger of claim 9, wherein the reverse boost mode comprises maintaining a NGATE FET of the battery control transistor pair in an off state and maintaining the bypass transistor pair in an on state.

11. The battery charger of claim 9, wherein the reverse boost mode comprises controlling the switch using a pulse width modulated control signal.

12. The battery charger of claim 8, wherein the normal mode module is configured to cause the voltage from the battery to be provided to the load by operating the battery charger in an ideal diode mode.

13. The battery charger of claim 12, wherein the ideal mode comprises maintaining the pair of battery control transistors in an on state and maintaining the pair of bypass transistors in an off state.

14. The battery charger of claim 8, wherein the indication is received from an external entity.

15. The battery charger of claim 14, wherein the external entity comprises an embedded controller.

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