CN111834466A - Thin film transistor and its manufacturing method, array substrate, display panel and equipment - Google Patents

Abstract

The application relates to the technical field of display, and particularly discloses a thin film transistor and a manufacturing method thereof, an array substrate, a display panel and electronic equipment, wherein the thin film transistor comprises a grid electrode, a grid electrode insulating layer, an active layer and a protective layer; the active layer is arranged on one side of the grid electrode insulating layer, the grid electrode is arranged on the other side, away from the active layer, of the grid electrode insulating layer, the square resistance value of the grid electrode is smaller than or equal to a preset square resistance value, and the grid electrode at least comprises a first metal layer; the protective layer at least covers the exposed surface of the first metal layer to prevent the first metal layer from being oxidized. By the method, the RC delay on the grid can be reduced, and the problem of uneven screen flicker of the display device is solved.

Description

Thin film transistor and its manufacturing method, array substrate, display panel and equipment

technical field

The present application relates to the field of display technology, and in particular, to a thin film transistor and a method for manufacturing the same, an array substrate, a display panel and a device.

Background technique

In the prior art, Low Temperature Poly-Silicon (LTPS) panels have been widely used in smartphones and tablet computers. Since the gate itself has a predetermined resistance, parasitic capacitance will also be generated between the gate and the drain of the thin film transistor, and the resistance and capacitance will form a resistance-capacitance delay (RC delay) circuit.

Based on the development trend of display panels towards large size and high resolution, higher requirements are placed on the trace width inside the display panel - the gate width is getting smaller and smaller, and the gate length is getting longer and longer. As a result, the load of each gate is getting larger and larger, the charging time is getting smaller and smaller, and the pixel density is getting larger and larger, and the RC delay inside the display panel is difficult to control within a small range. In this case, the GOA circuit cannot normally input the gate scanning signal, which causes the display panel to have a problem of poor display.

SUMMARY OF THE INVENTION

Based on this, the present application provides a thin film transistor and a method for manufacturing the same, an array substrate, a display panel and an electronic device to reduce the RC delay on the gate and improve the problem of uneven flickering of the display device.

In a first aspect, an embodiment of the present application provides a thin film transistor, including a gate electrode, a gate insulating layer, an active layer and a protective layer; wherein the active layer is provided on one side of the gate insulating layer, and the gate electrode is provided on one side of the gate insulating layer. The other side of the gate insulating layer away from the active layer, the sheet resistance value of the gate is less than or equal to the preset sheet resistance value, the gate at least includes a first metal layer; the protective layer at least covers the exposed surface of the first metal layer to prevent The first metal layer is oxidized.

In a second aspect, an embodiment of the present application provides a method for manufacturing a thin film transistor, the method comprising: providing a gate, wherein a sheet resistance value of the gate is less than or equal to a preset sheet resistance value, and the gate at least includes a first metal layer A gate insulating layer is formed on one side of the gate; an active layer is formed on the side of the gate insulating layer away from the gate; a protective layer is formed on the gate, wherein the protective layer at least covers the exposed surface of the first metal layer, to prevent the first metal layer from being oxidized.

In a third aspect, an embodiment of the present application provides an array substrate, including a substrate and a plurality of pixel units disposed on the substrate, the plurality of pixel units are arranged in an array, and each pixel includes the aforementioned thin film transistors and thin film transistors respectively. Electrically connected pixel electrodes.

In a fourth aspect, an embodiment of the present application provides a display panel, including the aforementioned array substrate, a color filter substrate disposed opposite to the array substrate, and a spacer disposed between the array substrate and the color filter substrate; wherein the spacer Used to support array substrate and color filter substrate.

In a fifth aspect, an embodiment of the present application provides an electronic device, including a back cover, a cover plate, the aforementioned display panel, a drive circuit for driving the display panel, and a backlight module for providing a backlight source to the display panel; The display panel, the driving circuit and the backlight module are mounted on the rear cover, and the cover plate covers the display panel.

The beneficial effects of the present application are: different from the prior art, the present application provides a thin film transistor and its manufacturing method, an array substrate, a display panel and an electronic device, wherein the sheet resistance of the gate of the thin film transistor is less than or equal to The preset sheet resistance value reduces the overall resistance of the gate, thereby improving the RC delay on the gate signal line and improving the problem of uneven flickering of the display device. In addition, the present application uses a protective layer to cover the exposed surface of the first metal layer. Therefore, in the subsequent high temperature process, the first metal layer will not be oxidized by oxygen and other oxides in the environment due to the protection of the protective layer. It can improve the stability of the gate and ensure the low sheet resistance value of the gate.

Description of drawings

1 is a schematic structural diagram of a first embodiment of a thin film transistor of the present application;

2 is a schematic structural diagram of a second embodiment of a thin film transistor of the present application;

3 is a schematic structural diagram of a third embodiment of a thin film transistor of the present application;

4 is a schematic structural diagram of a fourth embodiment of a thin film transistor of the present application;

5 is a schematic structural diagram of a fifth embodiment of a thin film transistor of the present application;

6 is a schematic structural diagram of a sixth embodiment of a thin film transistor of the present application;

7 is a schematic structural diagram corresponding to the manufacturing method of the thin film transistor of the present application;

FIG. 8 is a schematic flowchart of the first embodiment of the manufacturing method of the thin film transistor of the present application;

9 is a schematic flowchart of a second embodiment of the method for manufacturing a thin film transistor of the present application;

10 is a schematic flowchart of a third embodiment of the method for manufacturing a thin film transistor of the present application;

11 is a schematic flowchart of a fourth embodiment of the method for manufacturing a thin film transistor of the present application;

12 is a schematic flowchart of a fifth embodiment of the method for manufacturing a thin film transistor of the present application;

13 is a schematic structural diagram of an embodiment of an array substrate of the present application;

FIG. 14 is a schematic structural diagram of an embodiment of a display panel of the present application;

FIG. 15 is a schematic structural diagram of an embodiment of an electronic device of the present application.

Detailed ways

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present application, and should not be construed as a limitation on the present application. In addition, this application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

Referring to FIG. 1 , the thin film transistor 10 includes a gate electrode 11 , a gate insulating layer 12 , an active layer 13 and a protective layer 14 . The gate 11 is disposed on the side of the gate insulating layer 12 away from the active layer 13 , the sheet resistance of the gate 11 is less than or equal to a predetermined sheet resistance, and the gate 11 at least includes a first metal layer 111 .

The protective layer 14 covers at least the exposed surface of the first metal layer 111 to prevent the first metal layer 111 from being oxidized. When the protective layer 14 only covers the exposed surface of the first metal layer 111, the projection of the protective layer 14 on the gate insulating layer 12 partially overlaps with the projection of the gate 11 on the gate insulating layer 12, which can reduce the number of gate 11, The parasitic capacitance between the protective layer 14 and the source electrode (not shown in the figure) and the drain electrode (not shown in the figure) improves the performance of the thin film transistor 10 .

Specifically, the thin film transistor 10 can be a low temperature polysilicon thin film transistor 10, and the low temperature polysilicon thin film transistor 10 has become the preferred technology for the development of high-resolution small and medium-sized products due to its advantages of high carrier mobility. The active layer 13 is a low temperature polysilicon layer.

In this embodiment, the gate insulating layer 12 is located on the side of the gate 11 and can be formed by chemical deposition; the active layer 13 is located on the side of the gate insulating layer 12 away from the gate 11 and can be formed by chemical deposition .

The gate insulating layer 12 may be a single-layer or multi-layer composite stack composed of one or both of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride and aluminum oxide. Floor.

Further, in order to make the sheet resistance of the gate 11 (the symbol is Rs, and the expression is Rs=ρ/t; where ρ is the resistivity of the material of the gate 11, and t is the thickness of the gate 11 ) value is less than or equal to the preset value For the sheet resistance value, the material of the first metal layer 111 may be a low resistivity metal element, for example, the material of the first metal layer 111 is selected from at least one of copper and aluminum. In the embodiment of the present application, the resistivity of the material of the first metal layer 111 is reduced, so that the sheet resistance when applied to the gate electrode 11 is smaller, so as to meet the requirement of the thin film transistor 10 for low resistance value of the gate electrode 11 .

Wherein, in the embodiment of the present application, the preset sheet resistance value may be 0.01-0.5 ohm/square, and preferably, the preset sheet resistance value may be 0.01-0.1 ohm/square.

Further, the material of the protective layer 14 can be a metal or metal alloy with electrical conductivity and low affinity with oxygen, for example, the material of the protective layer 14 is selected from molybdenum, titanium, their alloys or mixtures, and molybdenum-niobium alloys. at least one. The affinity of the protective layer 14 to oxygen is smaller than the affinity of the first metal layer 111 to oxygen. Since the protective layer 14 is used to cover at least the exposed first metal layer 111 , the first metal layer 111 can be effectively prevented from being oxidized by oxygen and other oxides in the environment, so as to ensure the low sheet resistance value of the gate 11 .

Different from the prior art, the present application provides a thin film transistor 10, wherein the sheet resistance value of the gate electrode 11 of the thin film transistor 10 is less than or equal to a predetermined sheet resistance value, that is, the overall resistance of the gate electrode 11 is reduced, thereby improving the The RC delay on the gate 11 improves the problem of uneven flickering of the display device. In addition, the present application uses the protective layer 14 to cover the exposed surface of the first metal layer 111. Therefore, in the subsequent high temperature process, the first metal layer 111 is protected by the protective layer 14 and will not be affected by oxygen and other oxides in the environment. Oxidation maximizes the stability of the gate 11 and ensures a low sheet resistance value of the gate 11 .

Please refer to FIG. 2 and FIG. 3 , in terms of structure, the gate 11 can be a single metal layer or a multi-layer structure, and the multi-layer structure includes a double-layer structure or a three-layer structure. The second metal layer 112 , the first metal layer 111 and the third metal layer 113 are disposed in contact with the gate insulating layer 12 . The above-mentioned metal layers can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition and other methods.

Preferably, the material of the first metal layer 111 is selected from at least one of copper and aluminum, and the material of the second metal layer 112 and the third metal layer 113 is selected from titanium or titanium-containing alloys.

As a specific embodiment, the gate 11 may be a film layer of a titanium/copper/titanium stack structure, or the gate 11 may be a film layer of a titanium/aluminum/titanium stack structure. It should be noted that each film of the stack structure The material of the layer is a metal element. Wherein, the sheet resistance value of the film layer of the titanium/aluminum/titanium stack structure is 0.05 ohm/square.

The cross-section of each metal layer of the three-layer structure is a trapezoidal shape with an upper narrow and a lower width, and a surface of the metal layer close to the gate insulating layer 12 is a trapezoidal bottom surface. The above-mentioned trapezoidal structure with a narrow top and a wide bottom can eliminate the step climbing on the surface of the gate 11 , thereby completely eliminating the risk of disconnection of each sub-layer caused by the climbing, and further improving the yield of the thin film transistor 10 .

Further, when the gate electrode 11 is a titanium/copper/titanium stacked structure film layer or the gate electrode 11 is a titanium/aluminum/titanium stacked structure film layer, the material of the protective layer 14 is preferably titanium. At this time, the gate electrode 11 The protective layer 14 can still be regarded as a gate 11 as a whole, and will not affect the sheet resistance of the film of the titanium/copper/titanium stacked structure or the film of the gate 11 of the titanium/aluminum/titanium stacked structure.

Referring to FIGS. 4 and 5 , when the gate 11 has a single-layer structure, or the material of the protective layer 14 is different from that of the gate 11 , the protective layer 14 can completely cover the outer surface of the gate 11 , and the protective layer 14 The exposed gate insulating layer 12 is at least partially covered.

Referring to FIG. 6 , the active layer 13 includes a channel region 131 , a source doped region 132 on one side of the channel region 131 , and a drain doped region 133 on the opposite side of the channel region 131 . The projection of the gate 11 on the gate insulating layer 12 coincides with the projection of the channel region 131 on the gate insulating layer 12, that is, the gate 11 covers the low-temperature polysilicon undoped region (ie, the channel region 131) below it. , and does not overlap with the source doping region 132 and the drain doping region 133 .

The protective layer 14 may be etched through an etching process to form a plurality of gate 11-protective layer 14 composite structures spaced apart from each other. The cross-sectional shape of the protective layer 14 is a trapezoid with a narrow top and a wide bottom. The surface of the protective layer 14 in contact with the gate insulating layer 12 is the bottom surface of the trapezoid. The projection of the protective layer 14 on the gate insulating layer 12 covers the channel region 131 at the gate. Projection on the polar insulating layer 12 .

Further, the thin film transistor 10 further includes a source electrode 15 and a drain electrode 16 formed on both sides of the active layer 13 , and the source electrode 15 and the drain electrode 16 are respectively electrically connected to the source doped region 132 and the drain doped region 133 . .

Referring to FIG. 7 and FIG. 8 , the present application provides a method for manufacturing a thin film transistor 10 for manufacturing the thin film transistor 10 in the above-mentioned embodiments. The manufacturing method of the thin film transistor 10 includes:

S100: The gate 11 is provided.

Specifically, the sheet resistance value of the gate 11 is less than or equal to the predetermined sheet resistance value. In order to make the sheet resistance of the gate 11 (the symbol is Rs, the expression is Rs=ρ/t; where ρ is the resistivity of the material of the gate 11, and t is the thickness of the gate 11) value is less than or equal to the preset sheet resistance value , the material of the first metal layer 111 may be a low resistivity metal element, for example, the material of the first metal layer 111 is selected from at least one of copper and aluminum. In the embodiment of the present application, the resistivity of the material of the first metal layer 111 is reduced, so that the sheet resistance when applied to the gate electrode 11 is smaller, so as to meet the requirement of the thin film transistor 10 for low resistance value of the gate electrode 11 . Wherein, in the embodiment of the present application, the preset sheet resistance value may be 0.01-0.5 ohm/square, and preferably, the preset sheet resistance value may be 0.01-0.1 ohm/square.

The gate 11 may be a single metal layer or a multi-layer structure, and the multi-layer structure includes a double-layer structure or a three-layer structure. For example, the gate 11 includes a second metal layer 112, a first metal layer 111 and a third metal layer 112 stacked in sequence. The metal layer 113 and the second metal layer 112 are arranged in contact with the gate insulating layer 12 . The above metal layers can be formed by sputtering, thermal evaporation, atomic layer deposition, physical vapor deposition, chemical vapor deposition and other methods.

Preferably, the material of the first metal layer 111 is selected from at least one of copper and aluminum, and the material of the second metal layer 112 and the third metal layer 113 is selected from titanium or titanium-containing alloys.

As a specific embodiment, the gate 11 may be a film layer of a titanium/copper/titanium stack structure, or the gate 11 may be a film layer of a titanium/aluminum/titanium stack structure. It should be noted that each film of the stack structure The material of the layer is a metal element. Wherein, the sheet resistance value of the film layer of the titanium/aluminum/titanium stack structure is 0.05 ohm/square. The cross-section of each metal layer of the three-layer structure is a trapezoidal shape with an upper narrow and a lower width, and a surface of the metal layer close to the gate insulating layer 12 is a trapezoidal bottom surface. The above-mentioned trapezoidal structure with a narrow top and a wide bottom can eliminate the step climbing on the surface of the gate 11 , thereby completely eliminating the risk of disconnection of each sub-layer caused by the climbing, and further improving the yield of the thin film transistor 10 .

Further, the step S100 includes patterning the gate 11 to form a plurality of gate 11 units. For example, the etching time of the etching step is between 6 and 18 seconds, and the etching temperature of the etching step is between 35 and 45° C. between. In one example, the etching step is performed with an acid containing an aluminum component.

S110 : forming the gate insulating layer 12 on the side of the gate electrode 11 .

Specifically, in step S110, for example, the gate insulating layer 12 can be formed on the gate electrode 11 by using common materials or fabrication methods in the semiconductor process, for example, sputtering, thermal evaporation, atomic layer deposition, physical vapor deposition, The method of chemical vapor deposition will deposit the gate insulating layer 12 on the gate electrode 11 .

The gate insulating layer 12 may be a single-layer or multi-layer composite stack composed of one or both of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride and aluminum oxide. Floor.

S120 : forming the active layer 13 on the side of the gate insulating layer 12 away from the gate 11 .

Specifically, in step S120 , the active layer 13 can be formed on the side of the gate insulating layer 12 away from the gate electrode 11 , for example, by using common materials or fabrication methods in semiconductor processes. Wherein, the active layer 13 is a low temperature polysilicon layer.

S130 : forming the protective layer 14 on the gate electrode 11 .

Specifically, the protective layer 14 can be deposited on the gate electrode 11 by using plasma enhanced chemical vapor deposition method, and the protective layer 14 covers at least the exposed surface of the first metal layer 111 to prevent the first metal layer 111 from being oxidized.

Further, the material of the protective layer 14 can be a metal or metal alloy with electrical conductivity and low affinity with oxygen, for example, the material of the protective layer 14 is selected from molybdenum, titanium, their alloys or mixtures, and molybdenum-niobium alloys. at least one. Since the protective layer 14 is used to cover at least the exposed first metal layer 111 , the first metal layer 111 can be effectively prevented from being oxidized by oxygen and other oxides in the environment, so as to ensure the low sheet resistance value of the gate 11 .

Further, when the gate electrode 11 is a titanium/copper/titanium stacked structure film layer or the gate electrode 11 is a titanium/aluminum/titanium stacked structure film layer, the material of the protective layer 14 is preferably titanium. At this time, the gate electrode 11 The protective layer 14 can still be regarded as a gate 11 as a whole, and will not affect the sheet resistance of the film of the titanium/copper/titanium stacked structure or the film of the gate 11 of the titanium/aluminum/titanium stacked structure.

Different from the prior art, the present application provides a method for manufacturing a thin film transistor 10 , wherein the sheet resistance value of the gate electrode 11 of the thin film transistor 10 is less than or equal to a predetermined sheet resistance value, that is, the overall resistance of the gate electrode 11 is reduced. , thereby improving the RC delay on the gate 11 and improving the problem of uneven flickering of the display device. In addition, the present application uses the protective layer 14 to cover the exposed surface of the first metal layer 111. Therefore, in the subsequent high temperature process, the first metal layer 111 is protected by the protective layer 14 and will not be affected by oxygen and other oxides in the environment. Oxidation maximizes the stability of the gate 11 and ensures a low sheet resistance value of the gate 11 .

Please refer to FIG. 9 and FIG. 8 , the manufacturing method of the thin film transistor 10 further includes:

S140 : forming a first photoresist layer on the first dielectric layer 110 for forming the gate electrode 11 .

The first dielectric layer 110 may be a single metal layer or a multi-layer structure, and the multi-layer structure includes a double-layer structure or a three-layer structure. For example, the first dielectric layer 110 includes a second metal dielectric layer and a first metal dielectric layer stacked in sequence. and the third metal dielectric layer, each metal dielectric layer can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition and other methods.

S150 : Expose the first photoresist layer by using the first mask, wherein the reserved area of the first photoresist layer corresponds to the gate electrode 11 .

S160 : performing an etching process to remove the first dielectric layer 110 in the partially exposed area to form the gate electrode 11 .

Further, the active layer 13 in step S120 includes a middle region, a first region on one side of the middle region, and a second region on the opposite side of the middle region.

Referring to FIG. 10, after step S160, the method further includes:

S170: Use a third mask to pattern the first photoresist layer, so that the middle area is not covered by the first photoresist layer, and the first area and the second area are covered by the remaining first photoresist layer .

S180 : Doping the first region to obtain the source doping region 132 , and doping the second region to obtain the drain doping region 133 .

The middle region is the channel region 131 .

Further, after step S180 , the method further includes: removing the remaining first photoresist layer to expose the gate electrode 11 . Wherein, the remaining first photoresist layer is etched by dry etching, and specifically, the remaining first photoresist layer is ashed by oxygen, that is, the remaining first photoresist is removed by means of oxygen burning photoresist glue layer. In other embodiments, ultrasonic heating can also be used to remove the remaining first photoresist layer.

Please refer to FIG. 11 and FIG. 8 , step S130 includes:

S131 : depositing a second dielectric layer 140 for forming the protective layer 14 on the gate electrode 11 .

The material of the second dielectric layer 140 may be a metal or metal alloy with electrical conductivity and low affinity with oxygen. For example, the material of the second dielectric layer 140 is selected from molybdenum, titanium, their alloys or mixtures, and molybdenum-niobium alloys. at least one of.

S132 : forming a second photoresist layer on the second dielectric layer 140 .

S133 : Expose the second photoresist layer by using the second mask, wherein the reserved area of the second photoresist layer corresponds to the protective layer 14 .

S134 : performing an etching process to remove the second dielectric layer 140 in the partially exposed area to form the protective layer 14 .

Please refer to FIG. 12 and FIG. 8, after step S134, the method further includes:

S135: Use the third mask to pattern the second photoresist layer, so that the middle area is not covered by the second photoresist layer, and the first area and the second area are covered by the remaining second photoresist layer .

S136 : Doping the first region to obtain the source doping region 132 , and doping the second region to obtain the drain doping region 133 . The middle region is the channel region 131 .

Optionally, in one embodiment, the doping may be N-type doping or P-type doping, and correspondingly, an N-type thin film transistor 10 or a P-type thin film transistor 10 is fabricated.

Further, after step S136 , the method further includes: removing the remaining second photoresist layer to expose the protective layer 14 . Wherein, the remaining second photoresist layer is etched by dry etching, and specifically, the remaining second photoresist layer is ashed by using oxygen, that is, the remaining second photoresist layer is removed by means of oxygen burning photoresist glue layer. In other embodiments, ultrasonic heating can also be used to remove the remaining second photoresist layer.

In one embodiment, the projection of the gate 11 on the gate insulating layer 12 coincides with the projection of the channel region 131 on the gate insulating layer 12 .

The cross-sectional shape of the protective layer 14 is a trapezoid with a narrow top and a wide bottom. The surface of the protective layer 14 in contact with the gate insulating layer 12 is the bottom surface of the trapezoid. The projection of the protective layer 14 on the gate insulating layer 12 covers the channel region 131 at the gate. Projection on the polar insulating layer 12 .

Referring to FIG. 13 , the present application also provides an array substrate 20 , which includes: a plurality of pixel units 23 arranged in a matrix form divided by gate lines 21 and data lines 22 that intersect horizontally and vertically, and the pixel units 23 include pixel electrodes 231, further comprising the thin film transistor 10 in the above embodiment. The source electrode 15 of the thin film transistor 10 is electrically connected to the data line 22 , and the drain electrode 16 of the thin film transistor 10 is electrically connected to the pixel electrode 231 . Since the thin film transistor 10 has been described in detail in the foregoing embodiments, it will not be repeated here.

Further, the drain electrode 16 of the thin film transistor 10 may be integrally formed with the pixel electrode 231 . In this way, the drain electrode 16 and the pixel electrode 231 can be formed at the same time, thereby simplifying the production process and improving the production efficiency.

An embodiment of the present application provides an array substrate 20, the array substrate 20 includes a thin film transistor 10, wherein the sheet resistance value of the gate electrode 11 of the thin film transistor 10 is less than or equal to a predetermined sheet resistance value, that is, the overall resistance of the gate electrode 11 is reduced , thereby improving the RC delay on the gate 11 and improving the problem of uneven flickering of the display device. In addition, the present application uses the protective layer 14 to cover the exposed surface of the first metal layer 111. Therefore, in the subsequent high temperature process, the first metal layer 111 is protected by the protective layer 14 and will not be affected by oxygen and other oxides in the environment. Oxidation maximizes the stability of the gate 11 and ensures a low sheet resistance value of the gate 11 .

Referring to FIG. 14 , the present application further provides a display panel 30 , which can be specifically arranged in an electronic device, such as a mobile phone, a personal computer, a tablet computer, a PDA (Personal Digital Assistant), and the like.

The display panel 30 in the embodiment of the present application includes an array substrate 20 , a spacer 31 and a color filter substrate 32 . The array substrate 20 is the array substrate 20 in the above embodiment, and the spacer 31 is disposed between the array substrate 20 and the color filter substrate 32 to support the array substrate 20 and the color filter substrate 32 .

Specifically, the color filter substrate 32 includes an organic flat layer 321 , a color resist layer 322 and a black matrix 323 . The organic flat layer 321 is laid on the color resist layer 322 , the color resist layer 322 includes color resists of different colors, and the color resists are separated from each other by a black matrix 323 . Specifically, the color resist colors contained in the color resist layer 322 may be red, green, blue, white, yellow, and the like. One end of the spacer 31 is in contact with the spacer 31 region of the alignment film layer of the array substrate 20 , and the other end is disposed corresponding to the black matrix 323 of the color filter substrate 32 .

Referring to FIG. 15 , the present application further provides an electronic device 40 , the electronic device 40 includes a cover plate 41 , a back cover 42 , a display panel 30 , a driving circuit (not shown in the figure) and a backlight module (not shown in the figure) .

The cover plate 41 is mounted on the display panel 30 to cover the display panel 30 . The cover plate 41 may be a transparent glass cover plate 41 . In some embodiments, the cover plate 41 may be a glass cover plate 41 made of a material such as sapphire. The cover plate 41 includes a display area 411 and a non-display area 412 , and the display panel 30 is attached and installed under the cover plate 41 to form a display surface of the electronic device 40 .

The cover plate 41 and the rear cover 42 can be combined to form a casing 43, the casing 43 has a closed space formed by the cover plate 41 and the rear cover 42, and is used for devices such as driving circuits and backlight modules. At the same time, the display panel 30 is electrically connected to the drive circuit.

Different from the prior art, the present application provides a thin film transistor 10 and a manufacturing method thereof, an array substrate 20 , a display panel 30 and an electronic device 40 , wherein the sheet resistance of the gate 11 of the thin film transistor 10 is less than or equal to a predetermined value. Setting the sheet resistance value means reducing the overall resistance of the gate 11 , thereby improving the RC delay on the gate 11 and improving the problem of uneven flickering of the display panel 30 . In addition, the present application uses the protective layer 14 to cover the exposed surface of the first metal layer 111 . Therefore, in the subsequent high temperature process, the first metal layer 111 is protected by the protective layer 14 and will not be affected by oxygen and other oxides in the environment. Oxidation maximizes the stability of the gate 11 and ensures a low sheet resistance value of the gate 11 .

The above are only the embodiments of the present application, and are not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied in other related technical fields, All are similarly included in the scope of patent protection of the present application.

Claims (17)

1. A thin film transistor comprises a grid electrode, a grid electrode insulating layer, an active layer and a protective layer;

the active layer is arranged on one side of the grid electrode insulating layer, the grid electrode is arranged on the other side, away from the active layer, of the grid electrode insulating layer, the square resistance value of the grid electrode is smaller than or equal to a preset square resistance value, and the grid electrode at least comprises a first metal layer;

the protective layer at least covers the exposed surface of the first metal layer to prevent the first metal layer from being oxidized.

2. The thin film transistor according to claim 1,

the material of the first metal layer is selected from at least one of copper and aluminum;

the material of the protective layer is at least one of molybdenum, titanium and alloy or mixture thereof, and molybdenum-niobium alloy.

3. The thin film transistor according to claim 1,

the grid further comprises a second metal layer and a third metal layer, the second metal layer, the first metal layer and the third metal layer are sequentially stacked, and the second metal layer is in contact with the grid insulating layer;

the cross sections of the second metal layer, the first metal layer and the third metal layer are in a trapezoid shape with a narrow top and a wide bottom, and the surface of each metal layer of the grid, which is close to the grid insulation layer, is the bottom surface of the trapezoid.

4. The thin film transistor according to claim 3,

the material of the first metal layer is selected from at least one of copper and aluminum;

the material of the second metal layer and the third metal layer is selected from titanium or titanium-containing alloy.

5. The thin film transistor according to claim 1,

the protective layer completely covers the outer surface of the grid electrode, and at least partially covers the exposed grid electrode insulating layer.

6. The thin film transistor according to claim 1,

the active layer comprises a channel region, a source electrode doped region positioned on one side of the channel region and a drain electrode doped region positioned on the other side of the channel region;

wherein a projection of the gate electrode on the gate insulating layer coincides with a projection of the channel region on the gate insulating layer;

the section of the protective layer is in a trapezoid shape with a narrow top and a wide bottom, the surface of the protective layer, which is in contact with the gate insulating layer, is the bottom surface of the trapezoid, and the projection of the protective layer on the gate insulating layer covers the projection of the channel region on the gate insulating layer.

7. A method of manufacturing a thin film transistor, the method comprising:

providing a grid, wherein the square resistance value of the grid is less than or equal to a preset square resistance value, and the grid at least comprises a first metal layer;

forming a gate insulating layer on one side of the gate;

forming an active layer on one side of the gate insulating layer, which is far away from the gate;

and forming a protective layer on the grid, wherein the protective layer at least covers the exposed surface of the first metal layer to prevent the first metal layer from being oxidized.

8. The method of claim 7,

the material of the first metal layer is selected from at least one of copper and aluminum;

the material of the protective layer is at least one of molybdenum, titanium and alloy or mixture thereof, and molybdenum-niobium alloy.

9. The method of claim 7,

the grid further comprises a second metal layer and a third metal layer, the second metal layer, the first metal layer and the third metal layer are sequentially stacked, and the second metal layer is in contact with the grid insulating layer;

the cross sections of the second metal layer, the first metal layer and the third metal layer are in a trapezoid shape with a narrow top and a wide bottom, and the surface of each metal layer of the grid, which is close to the grid insulation layer, is the bottom surface of the trapezoid.

10. The method of claim 9,

the material of the first metal layer is selected from at least one of copper and aluminum;

the material of the second metal layer and the third metal layer is selected from titanium or titanium-containing alloy.

11. The method of claim 7, further comprising:

forming a first photoresist layer on a first dielectric layer for forming the grid;

exposing the first photoresist layer by using a first mask, wherein a reserved area of the first photoresist layer corresponds to the grid;

and carrying out an etching process to remove the first dielectric layer of the partial exposure area to form the grid.

12. The method of claim 7, wherein the step of forming a protective layer on the gate electrode comprises:

depositing a second dielectric layer for forming the protective layer on the grid;

forming a second photoresist layer on the second dielectric layer;

exposing the second photoresist layer by using a second mask, wherein the reserved area of the second photoresist layer corresponds to the protective layer;

and carrying out an etching process to remove the second dielectric layer in the partial exposure area to form the protective layer.

13. The method of any one of claims 11 or 12, wherein the active layer comprises a middle region, a first region on one side of the middle region, and a second region on an opposite side of the middle region;

after the step of providing the gate electrode, or after the step of forming the protective layer on the gate electrode, the method further includes:

patterning the first photoresist layer or the second photoresist layer using the third reticle such that the intermediate region is not covered by the first photoresist layer or the second photoresist layer, and the first region, the second region are covered by the remaining first photoresist layer or the second photoresist layer;

and doping the first region to obtain a source doped region, and doping the second region to obtain a drain doped region, wherein the middle region is a channel region.

14. The method of claim 13,

the projection of the grid electrode on the grid electrode insulating layer is coincided with the projection of the channel region on the grid electrode insulating layer;

the section of the protective layer is in a trapezoid shape with a narrow top and a wide bottom, the surface of the protective layer, which is in contact with the gate insulating layer, is the bottom surface of the trapezoid, and the projection of the protective layer on the gate insulating layer covers the projection of the channel region on the gate insulating layer.

15. An array substrate, comprising: a plurality of pixel units arranged in a matrix form and defined by gate lines and data lines, the pixel units including pixel electrodes, and further including the thin film transistors according to any one of claims 1 to 6, the sources of the thin film transistors being electrically connected to the data lines;

and the drain electrode of the thin film transistor is electrically connected with the pixel electrode.

16. A display panel comprising the array substrate of claim 15, a color filter substrate disposed opposite to the array substrate, and a spacer disposed between the array substrate and the color filter substrate;

the spacer is used for supporting the array substrate and the color film substrate.

17. An electronic device comprising a rear cover, a cover plate, the display panel according to claim 16, a driving circuit for driving the display panel, and a backlight module for providing a backlight source to the display panel;

the display panel, the driving circuit and the backlight module are arranged on the rear cover, and the cover plate covers the display panel.

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