CN111813712B - Cache allocation control method, device, terminal equipment and storage medium - Google Patents
Cache allocation control method, device, terminal equipment and storage mediumInfo
- Publication number
- CN111813712B CN111813712B CN202010484651.8A CN202010484651A CN111813712B CN 111813712 B CN111813712 B CN 111813712B CN 202010484651 A CN202010484651 A CN 202010484651A CN 111813712 B CN111813712 B CN 111813712B
- Authority
- CN
- China
- Prior art keywords
- storage device
- external storage
- cache
- allocated
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
本申请实施例适用于集成电路技术领域，提供了一种缓存分配控制方法、装置、终端设备及存储介质，所述方法包括：当检测到外接存储设备时，识别所述外接存储设备的存储类型；根据所述外接存储设备的存储类型，确定待分配给所述外接存储设备的缓存数量；按照所述待分配给所述外接存储设备的缓存数量，为所述外接存储设备分配相应数量的缓存。本实施例通过将缓存配置成可分割的形式，根据外接存储设备类型的不同，分别为各个外接存储设备分配缓存，有助于提高CPU的性能。
The embodiments of the present application are applicable to the field of integrated circuit technology and provide a cache allocation control method, apparatus, terminal device, and storage medium. The method comprises: upon detecting an external storage device, identifying the storage type of the external storage device; determining the amount of cache to be allocated to the external storage device based on the storage type of the external storage device; and allocating a corresponding amount of cache to the external storage device based on the amount of cache to be allocated to the external storage device. This embodiment configures the cache in a divisible form, allocating cache to each external storage device based on the type of the external storage device, thereby helping to improve CPU performance.
Description
The application claims priority of Chinese application patent application with application date of 2019, 12 month and 31 date, application number of 201911423537.8 and name of 'a cache allocation control method, device, terminal equipment and storage medium'.
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a method and apparatus for controlling cache allocation, a terminal device, and a storage medium.
Background
Generally, a System-on-a-Chip (SoC) includes a central processing unit (Central Processing Unit, CPU) and a plurality of memory devices. The memory device may be roughly divided into an instruction memory and a data memory according to the stored information. Common instruction memories include on-chip ROM, off-chip FLASH, etc., and common data memories include on-chip ROM, on-chip RAM, off-chip SDRAM, off-chip FLASH, etc. The access speed of the on-chip ROM and the on-chip RAM is higher, and the access speed of the off-chip SDRAM and the off-chip FLASH is lower.
In operation of a CPU, since execution of any instruction involves the type of operation being performed and the data being operated upon, it is often necessary to access both the instruction and the data at the same time. However, the operation performance of the CPU is limited by the slower of the command access speed and the data access speed, and how to balance the command access speed and the data access speed to exert the performance of the CPU as much as possible is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, embodiments of the present application provide a cache allocation control method, apparatus, terminal device, and storage medium, which can balance the instruction access speed and the data access speed, and improve the CPU performance.
A first aspect of an embodiment of the present application provides a method for controlling cache allocation, including:
When an external storage device is detected, identifying the storage type of the external storage device;
Determining the number of caches to be allocated to the external storage device according to the storage type of the external storage device;
and distributing corresponding quantity of caches for the external storage equipment according to the quantity of caches to be distributed to the external storage equipment.
Optionally, when the external storage device is detected, identifying a storage type of the external storage device includes:
When an external storage device is detected, identifying a storage object in the external storage device, wherein the storage object comprises at least one of a program object and a data object;
And determining the storage type of the external storage device according to the storage object in the external storage device.
Optionally, when the external storage device is detected, identifying a storage type of the external storage device includes:
When an external storage device is detected, identifying the access bandwidth of the external storage device;
And determining the storage type of the external storage device according to the access bandwidth of the external storage device.
Optionally, when the external storage device is detected, identifying a storage type of the external storage device includes:
When the external storage device is detected, identifying a predefined product type in a nonvolatile memory accessible by a chip CPU;
And determining the storage type of the external storage device according to the product type.
Optionally, the determining, according to the storage type of the external storage device, the number of caches to be allocated to the external storage device includes:
reading configuration information of the external storage device;
obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to test results obtained by testing external storage devices of different storage types in advance;
And determining the number of the caches to be allocated to the external storage device according to the cache allocation information.
Optionally, the cache includes a plurality of cache memories, and determining, according to the cache allocation information, the number of caches to be allocated to the external storage device includes:
And determining the number of the cache memories to be allocated to the storage objects in the external storage device according to the number of the cache memories required by different storage objects recorded in the cache allocation information.
Optionally, the allocating a corresponding number of caches to the external storage device according to the number of caches to be allocated to the external storage device includes:
and according to the number of the cache memories to be allocated to the storage objects, allocating the corresponding number of the cache memories to the storage objects in the external storage device.
Optionally, the allocating, according to the number of cache memories to be allocated to the storage object, a corresponding number of cache memories to the storage object in the external storage device includes:
determining an access interface corresponding to the storage object;
And associating and configuring the cache memory allocated to the storage object with the access interface.
A second aspect of an embodiment of the present application provides a cache allocation control device, including:
the identification module is used for identifying the storage type of the external storage device when the external storage device is detected;
the determining module is used for determining the buffer memory quantity to be allocated to the external storage device according to the storage type of the external storage device;
And the distribution module is used for distributing the corresponding quantity of caches for the external storage equipment according to the quantity of the caches to be distributed to the external storage equipment.
A third aspect of an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the cache allocation control method according to any one of the first aspect when executing the computer program.
A fourth aspect of an embodiment of the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the cache allocation control method according to any one of the first aspects.
A fifth aspect of an embodiment of the present application provides a computer program product, which when run on a terminal device, causes the terminal device to execute the cache allocation control method of any one of the first aspects above.
Compared with the prior art, the embodiment of the application has the following advantages:
According to the embodiment of the application, when the external storage device is detected, the storage type of the external storage device can be identified first, and the number of the caches to be allocated to the external storage device is determined according to the storage type, so that the corresponding number of the caches can be allocated to the external storage device according to the number of the caches. According to the embodiment, the caches are configured in a partible form, and different proportions or specific numbers of caches are respectively distributed to the external storage devices according to different types of the external storage devices, so that the performance of the CPU is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flowchart illustrating a buffer allocation control method according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating steps of another method for controlling cache allocation according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating steps of a method for controlling allocation of a buffer according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a cache allocation control device according to an embodiment of the present application;
fig. 5 is a schematic diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
Typically, in chip design, the core functions of a chip may be designed in the form of on-chip memory. That is, a general function of a certain chip that can be applied to a plurality of different products is designed in the chip, and personalized development for the different products can be processed in the form of an off-chip memory. Typically, on-chip memory has a small capacity but a fast access speed, while off-chip memory has a large capacity and can be changed but has a relatively slow access speed. In practical tests, the access speed of the on-chip memory can reach more than 30 times of the access speed of the off-chip memory.
Therefore, in order to balance the access speeds of different memories, the present embodiment configures the caches in a divisible form, and tests the number of caches required to obtain optimal performance when different memories exist, so that when the presence of off-chip memories is detected, the caches can be allocated according to the corresponding number of caches.
The technical scheme of the application is described below through specific examples.
Referring to fig. 1, a flowchart illustrating steps of a buffer allocation control method according to an embodiment of the present application may specifically include the following steps:
S101, when an external storage device is detected, identifying the storage type of the external storage device;
It should be noted that the method may be applied to a terminal device, that is, the execution body of the embodiment is the terminal device. The terminal device may be a product produced based on a certain SoC chip, such as a certain electronic device or other device, etc. The terminal equipment can improve the CPU operation efficiency by distributing the cache.
In general, products produced based on a certain type of SoC chip may be a variety of different types of products or devices. For example, for the SoC chip, the chip manufacturer may write the most core and general-purpose program or algorithm into the chip, and for different customers, write other algorithms or programs required separately into other storage devices, and associate the storage devices with the SoC chip, so as to flexibly configure the SoC chip for different customers.
In this embodiment, the external storage device may be a device in which a corresponding program or algorithm is written according to actual needs of a device manufacturer.
After the SoC chip is powered on, if the existence of the external storage device is detected, the storage type of the external storage device can be first identified.
Generally, depending on the object stored, a certain storage device may be roughly divided into an instruction storage device, a data storage device, or a device capable of storing instructions and data at the same time.
It should be noted that, the external storage device in the embodiment of the present application may include all memories except the CPU cache memory, including a common data memory type, such as a common instruction memory (on-chip ROM, off-chip FLASH, etc.), and a common data memory (on-chip ROM, on-chip RAM, off-chip SDRAM, off-chip FLASH, etc.). All memory that the CPU needs to access through cache memory, including all memory on-chip and off-chip.
In the embodiment of the application, the storage type of the external storage device is identified by identifying the storage object of the external storage device or identifying the access bandwidth of the external storage device or identifying the predefined product type in the nonvolatile memory accessible by the chip CPU when the external storage device is detected, and then the storage type of the external storage device is determined according to the storage object or the access bandwidth or the product type.
S102, determining the number of caches to be allocated to the external storage device according to the storage type of the external storage device;
in this embodiment, the caches may be configured in a separable form, and according to different storage types of the external storage device, how many caches need to be allocated to the device may be determined according to the respective storage types.
For example, for an instruction storage device storing code to be executed and a data storage device storing only video data, a general buffer may be allocated to each of the two storage devices, respectively, to ensure balance of access speeds of instructions and data.
S103, according to the number of the caches to be allocated to the external storage device, allocating corresponding numbers of caches to the external storage device.
In this embodiment, after determining how many caches need to be allocated to the external storage device, the corresponding caches may be allocated to the external storage device.
In the embodiment of the application, when the external storage device is detected, the storage type of the external storage device can be identified first, and the number of the caches to be allocated to the external storage device is determined according to the storage type, so that the corresponding number of the caches can be allocated to the external storage device according to the number of the caches. According to the embodiment, the caches are configured in a partible form, and different proportions or specific numbers of caches are respectively distributed to the external storage devices according to different types of the external storage devices, so that the performance of the CPU is improved.
Referring to fig. 2, a flowchart illustrating steps of another cache allocation control method according to an embodiment of the present application may specifically include the following steps:
S201, when an external storage device is detected, identifying a storage object in the external storage device;
In this embodiment, the external storage device may refer to an off-chip device. The on-chip and off-chip are two concepts in the field of integrated circuits, the on-chip refers to the inside of the integrated circuit made into a chip, and is abbreviated as on-chip, and the off-chip refers to the outside of the integrated circuit chip. The connection of the integrated circuit chip to the external device generally needs to be achieved through a special interface circuit and bus.
By connecting other storage devices outside the chip, a plurality of different end products can be produced based on the same chip. For example, a chip may be disposed on a circuit board and then different resources may be attached to the periphery thereof to form a plurality of different products. The general codes required by the different products can be written into the chip, and the codes corresponding to the additional functions required by the different products can be written into the external device according to the types of the products. Under the condition, the definition mode of the product type can write the specific code into a nonvolatile memory accessible by a chip CPU through a production stage, the CPU reads and accesses the specific code after powering on to obtain the corresponding product type, and then the CPU can adjust the cache allocation modes of different external storage devices according to the requirement characteristics of different product types for different memories and the detected information such as the storage object and the access bandwidth of the external storage device.
When the chip is electrified, if the existence of the external storage device is detected, the storage object in the external storage device can be identified first. In this embodiment, the storage object may include a program object, a data object, or both.
S202, determining the storage type of the external storage device according to the storage object in the external storage device;
In this embodiment, the external storage device may be divided into a device storing only program objects, such as a device storing executable programs or codes, or a device storing only data objects, such as a device storing only some picture data, video data, and not including other executable programs or codes, or a device storing both program objects and data objects, such as a device storing not only video data but also other executable programs, according to the difference of storage objects in the external storage device.
S203, reading configuration information of the external storage device;
in this embodiment, the configuration information of the external storage device may be factory information written into the chip when the chip leaves the factory, and it is known through the configuration information what kind of product the current chip is applied to, and what kind of configuration needs to be cached on the product, so as to help to improve the performance of the CPU.
S204, obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to test results obtained by testing external storage devices of different storage types in advance;
In this embodiment, for different products to which the chip is applied, the external storage device may be tested respectively, so as to understand what cache configuration mode is the configuration mode in which the product can obtain the optimal performance.
In a specific implementation, for a certain product, a program or code for implementing certain specific functions of the product may be written into an external storage device, and then the external storage device is connected. Then, by testing the CPU running performance under different cache configuration modes, it can be known which cache configuration mode should be adopted when the chip of the product is connected with the storage device, and the optimal performance can be obtained.
For example, if the chip buffer capacity is 32kb buffer, 1kb buffer is first allocated as instruction buffer, 31kb buffer is used as data buffer, then the chip performance is tested to obtain a performance result, then 2kb buffer is allocated as instruction buffer, 30kb buffer is used as data buffer, then the chip performance is tested to obtain another performance result, according to the method, at least 32 performance results can be tested, the buffer allocation mode with optimal performance can be identified in the 32 performance results and written into configuration information, similar performance test is not needed again after chip batch production, and the optimal performance effect can be achieved by directly configuring the buffer allocation mode according to the instruction of the configuration information.
S205, determining the number of caches to be allocated to the external storage device according to the cache allocation information;
in this embodiment, after the type of the external storage device is identified, the number of caches to be allocated to the external storage device may be determined according to the cache allocation information in the configuration information.
For example, a 1kb cache may be allocated as the instruction cache and a 31kb cache as the data cache.
S206, according to the number of the caches to be allocated to the external storage device, allocating a corresponding number of caches to the external storage device.
According to the embodiment of the application, according to different storage types of the external storage equipment, a cache allocation mode with optimal CPU performance when the external storage equipment is externally connected with the corresponding type can be obtained through testing and written into configuration information, so that after detecting the external storage equipment of a certain type, the allocation mode can be directly read out from the configuration information, and cache allocation is carried out according to the mode. According to the embodiment, the buffer allocation modes corresponding to different external storage devices are obtained through testing, so that the buffer can be flexibly allocated, the use in different scenes can be dealt with, and the CPU performance is improved.
Referring to fig. 3, a flowchart illustrating steps of another method for controlling cache allocation according to an embodiment of the present application may specifically include the following steps:
s301, when an external storage device is detected, identifying a storage object in the external storage device;
s302, determining the storage type of the external storage device according to the storage object in the external storage device;
S303, reading configuration information of the external storage device;
S304, obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to test results obtained by testing external storage devices of different storage types in advance;
It should be noted that, steps S301 to S304 in the present embodiment are similar to steps S201 to S204 in the foregoing embodiment, and reference may be made to each other.
S305, determining the number of the cache memories to be allocated to the storage objects in the external storage device according to the number of the cache memories required by different storage objects recorded in the cache allocation information;
In this embodiment, the cache may include a plurality of cache memories. That is, the caches are configured in the form of memory clusters, allocated dynamically for different application objects and scenarios.
In a specific implementation, the allocation manner configured in the cache allocation information may refer to the number of cache memories required for different storage objects in the external storage device.
For example, for an external storage device that stores both program objects and data objects, half of the cache memory may be allocated to program objects therein, while the other half may be allocated to other data objects.
S306, determining an access interface corresponding to the storage object;
In this embodiment, after determining how many cache memories need to be allocated to the storage objects in the external storage device, a corresponding number of cache memories may be allocated to different storage objects in the external storage device according to the number of cache memories to be allocated to different storage objects.
In a specific implementation, access interfaces corresponding to different storage objects may be determined. For example, which are instruction interfaces to which the program object corresponds and which are data interfaces to which the data object corresponds.
It should be noted that, in a typical implementation, the instruction interface and the data interface may be the same physical interface. The distinction of the physical locations of the memory may be made depending on the address field saved or the instruction the CPU initiates the access. The above process can be analogous to the meaning of "port" in the internet, i.e. the physical ports are identical, but can be distinguished according to the difference of the target "port" in data distribution.
S307, the cache memory allocated to the storage object is configured in association with the access interface.
In this embodiment, when allocating caches for different storage objects, the cache memory that needs to be allocated to the storage object may be configured in association with the access interface corresponding to the cache memory.
As an example of this embodiment, if a product produced based on a certain chip needs to support both the on-chip ROM + on-chip RAM mode of operation and the off-chip FLASH + on-chip RAM mode of operation.
Then, when the working mode of the on-chip ROM+the on-chip RAM is supported, the on-chip ROM is a private memory of the CPU, and the access bandwidth of the on-chip ROM interface meets the requirement of the CPU for real-time reading, so that the cache function is not required to be used. In this case, the optimal cache allocation scheme is to divide all the memory in the cache into on-chip RAM access interfaces to ensure that the access speeds of the instructions and data reach equilibrium.
When the off-chip FLASH+on-chip RAM working mode is supported, the access bandwidth of the off-chip FLASH is usually significantly smaller than that of the on-chip RAM, or the access efficiency of the off-chip FLASH is lower, the access speed is slower, and the off-chip FLASH often contains both program objects (instructions) and data objects (data). Therefore, the optimal scheme in this case is to divide half of the total cache memory into the instruction interfaces of the off-chip FLASH and the other half into the data interfaces of the off-chip FLASH.
In the embodiment of the application, the cache can be configured into a cache memory cluster, so that the cache memory is flexibly distributed to the storage objects stored by the external storage equipment according to the storage objects, and the CPU performance is improved.
It should be noted that, the sequence number of each step in the above embodiment does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiment of the present application in any way.
Referring to fig. 4, a schematic diagram of a cache allocation control device according to an embodiment of the present application may specifically include the following modules:
The identifying module 401 is configured to identify a storage type of an external storage device when the external storage device is detected;
A determining module 402, configured to determine, according to a storage type of the external storage device, a number of caches to be allocated to the external storage device;
And the allocation module 403 is configured to allocate a corresponding number of caches for the external storage device according to the number of caches to be allocated to the external storage device.
In the embodiment of the present application, the identification module 401 may specifically include the following sub-modules:
The storage object identification sub-module is used for identifying a storage object in the external storage device when the external storage device is detected, wherein the storage object comprises at least one of a program object and a data object;
And the first storage type determining submodule is used for determining the storage type of the external storage device according to the storage object in the external storage device.
In an embodiment of the present application, the identification module 401 may further include the following sub-modules:
The access bandwidth identification sub-module is used for identifying the access bandwidth of the external storage device when the external storage device is detected;
and the second storage type determining submodule is used for determining the storage type of the external storage device according to the access bandwidth of the external storage device.
In an embodiment of the present application, the identification module 401 may further include the following sub-modules:
The product type identification sub-module is used for identifying a predefined product type in a nonvolatile memory accessible by the chip CPU when the external storage device is detected;
And the third storage type determining submodule is used for determining the storage type of the external storage device according to the product type.
In the embodiment of the present application, the determining module 402 may specifically include the following sub-modules:
The configuration information reading sub-module is used for reading the configuration information of the external storage device;
The cache allocation information acquisition sub-module is used for acquiring cache allocation information matched with the configuration information, and the cache allocation information is generated according to test results obtained by testing external storage devices of different storage types in advance;
And the buffer memory quantity determining submodule is used for determining the buffer memory quantity to be allocated to the external storage device according to the buffer memory allocation information.
In the embodiment of the present application, the cache includes a plurality of cache memories, and the cache number determining submodule may specifically include the following units:
And the cache memory number determining unit is used for determining the number of the cache memories to be allocated to the storage objects in the external storage device according to the number of the cache memories required by different storage objects recorded in the cache allocation information.
In the embodiment of the present application, the allocation module 403 may specifically include the following sub-modules:
And the buffer memory allocation sub-module is used for allocating corresponding numbers of buffer memories for the storage objects in the external storage device according to the numbers of the buffer memories to be allocated to the storage objects.
In the embodiment of the present application, the cache memory allocation submodule may specifically include the following units:
An access interface determining unit, configured to determine an access interface corresponding to the storage object;
And the association configuration unit is used for associating and configuring the cache memory allocated to the storage object with the access interface.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference should be made to the description of the method embodiments.
Referring to fig. 5, a schematic diagram of a terminal device according to an embodiment of the present application is shown. As shown in fig. 5, the terminal device 500 of the present embodiment comprises a processor 510, a memory 520 and a computer program 521 stored in said memory 520 and executable on said processor 510. The processor 510, when executing the computer program 521, implements the steps of the embodiments of the above-described cache allocation control method, such as steps S101 to S103 shown in fig. 1. Or the processor 510, when executing the computer program 521, performs the functions of the modules/units in the above-described device embodiments, for example, the functions of the modules 401 to 403 shown in fig. 4.
Illustratively, the computer program 521 may be partitioned into one or more modules/units that are stored in the memory 520 and executed by the processor 510 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which instruction segments may be used to describe the execution of the computer program 521 in the terminal device 500. For example, the computer program 521 may be divided into an identification module, a determination module, and an allocation module, where each module specifically functions as follows:
the identification module is used for identifying the storage type of the external storage device when the external storage device is detected;
the determining module is used for determining the buffer memory quantity to be allocated to the external storage device according to the storage type of the external storage device;
And the distribution module is used for distributing the corresponding quantity of caches for the external storage equipment according to the quantity of the caches to be distributed to the external storage equipment.
The terminal device 500 may include, but is not limited to, a processor 510, a memory 520. It will be appreciated by those skilled in the art that fig. 5 is merely an example of a terminal device 500 and is not meant to be limiting as to the terminal device 500, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the terminal device 500 may also include input and output devices, network access devices, buses, etc.
The Processor 510 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 520 may be an internal storage unit of the terminal device 500, such as a hard disk or a memory of the terminal device 500. The memory 520 may also be an external storage device of the terminal device 500, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the terminal device 500. Further, the memory 520 may also include both an internal storage unit and an external storage device of the terminal device 500. The memory 520 is used to store the computer program 521 and other programs and data required by the terminal device 500. The memory 520 may also be used to temporarily store data that has been output or is to be output.
The above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications and substitutions can be made to the technical solutions described in the foregoing embodiments or equivalent substitutions can be made to some technical features thereof, and these modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911423537 | 2019-12-31 | ||
| CN2019114235378 | 2019-12-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111813712A CN111813712A (en) | 2020-10-23 |
| CN111813712B true CN111813712B (en) | 2025-08-29 |
Family
ID=72848132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010484651.8A Active CN111813712B (en) | 2019-12-31 | 2020-06-01 | Cache allocation control method, device, terminal equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111813712B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106997275A (en) * | 2016-01-26 | 2017-08-01 | 南宁富桂精密工业有限公司 | Buffer memory management method and the electronic installation using this method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8782344B2 (en) * | 2012-01-12 | 2014-07-15 | Fusion-Io, Inc. | Systems and methods for managing cache admission |
| WO2014102886A1 (en) * | 2012-12-28 | 2014-07-03 | Hitachi, Ltd. | Information processing apparatus and cache control method |
| US9110592B2 (en) * | 2013-02-04 | 2015-08-18 | Microsoft Technology Licensing, Llc | Dynamic allocation of heterogenous memory in a computing system |
| US9703848B2 (en) * | 2015-11-13 | 2017-07-11 | International Business Machines Corporation | Caching linked queries for optimized compliance management |
| US10037149B2 (en) * | 2016-06-17 | 2018-07-31 | Seagate Technology Llc | Read cache management |
| US9996478B1 (en) * | 2016-12-09 | 2018-06-12 | Advanced Micro Devices, Inc. | No allocate cache policy |
| TWI647567B (en) * | 2017-12-13 | 2019-01-11 | 國立中正大學 | Method for locating hot and cold access zone using memory address |
-
2020
- 2020-06-01 CN CN202010484651.8A patent/CN111813712B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106997275A (en) * | 2016-01-26 | 2017-08-01 | 南宁富桂精密工业有限公司 | Buffer memory management method and the electronic installation using this method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111813712A (en) | 2020-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20160283111A1 (en) | Read operations in memory devices | |
| CN107436809A (en) | Data processor | |
| CN110554913A (en) | Neural network system, method of operation, and application processor | |
| US20190087208A1 (en) | Method and apparatus for loading elf file of linux system in windows system | |
| US9436450B2 (en) | Method and apparatus for optimising computer program code | |
| CN116431534A (en) | Data access method, switch and storage medium | |
| CN111208933A (en) | Data access method, device, equipment and storage medium | |
| CN110717050A (en) | Method and device for accessing knowledge map database | |
| CN113918233B (en) | AI chip control method, electronic device and AI chip | |
| CN105556402A (en) | Method for manipulating a control program of a control device | |
| CN112631955A (en) | Data processing method, data processing device, electronic device, and medium | |
| US8478946B2 (en) | Method and system for local data sharing | |
| CN111813712B (en) | Cache allocation control method, device, terminal equipment and storage medium | |
| US7827333B1 (en) | System and method for determining a bus address on an add-in card | |
| US7725806B2 (en) | Method and infrastructure for recognition of the resources of a defective hardware unit | |
| US10970206B2 (en) | Flash data compression decompression method and apparatus | |
| US11354130B1 (en) | Efficient race-condition detection | |
| JP4703753B2 (en) | Information processing apparatus, semiconductor memory device, and program | |
| CN113791942B (en) | Method and device for automatically distributing test tasks | |
| US11360713B2 (en) | Semiconductor device and debug system | |
| US7526689B1 (en) | Testing address lines of a memory controller | |
| US8380908B2 (en) | Emulation of an input/output advanced programmable interrupt controller | |
| US20110131397A1 (en) | Multiprocessor system and multiprocessor control method | |
| US11966749B2 (en) | Processor and booting method thereof | |
| CN120123067B (en) | Computing device, processor, electronic device, and computing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |