CN111813450A - Computing method, device and related products - Google Patents

Abstract

The disclosure relates to an operation method, an operation device and a related product. The integrated circuit board includes: the device comprises a storage device, an interface device, a control device and a machine learning chip; the machine learning chip is respectively connected with the storage device, the control device and the interface device; the storage device is used for storing data; the interface device is used for realizing data transmission between the machine learning chip and external equipment; the control device is used for monitoring the state of the machine learning chip.

Description

Computing method, device and related products

technical field

The present disclosure relates to the field of computer technology, and in particular, to a method, device and related products for processing matrix mirroring instructions.

Background technique

With the continuous development of science and technology, the use of machine learning, especially neural network algorithms, is becoming more and more extensive. It has been well used in image recognition, speech recognition, natural language processing and other fields. However, due to the increasing complexity of neural network algorithms, the types and quantities of data operations involved continue to increase. In the related art, the mirroring process for matrix data is inefficient and slow.

SUMMARY OF THE INVENTION

In view of this, the present disclosure proposes a method, device and related products for processing a matrix mirroring instruction, so as to improve the efficiency and speed of mirroring processing on a matrix.

According to a first aspect of the present disclosure, there is provided an apparatus for processing a matrix mirroring instruction, the apparatus comprising:

The control module is configured to parse the received matrix mirroring instruction, obtain the operation code and operation field of the matrix mirroring instruction, and determine the waiting period required to execute the matrix mirroring instruction according to the operation code and the operation field. Mirroring matrix and target addresses, and determining the mirroring strategy required for mirroring;

a processing module that performs mirroring processing on the matrix to be mirrored according to the mirroring strategy to obtain a mirrored matrix, and stores the mirrored matrix in the target address,

The operation code is used to indicate that the processing performed by the matrix mirroring instruction on the matrix data is mirror processing, and the operation field includes the address of the matrix to be mirrored and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning computing device, the device comprising:

One or more matrix mirroring instruction processing devices described in the first aspect above are used to obtain the matrix to be mirrored and control information from other processing devices, perform specified machine learning operations, and transmit the execution results to the I/O interface. other processing devices;

When the machine learning computing device includes a plurality of the matrix mirror instruction processing devices, the plurality of the matrix mirror instruction processing devices can be connected through a specific structure and data can be transmitted;

Wherein, a plurality of the matrix mirror instruction processing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the matrix mirror command processing devices share the same control system Or have their own control systems; a plurality of the matrix mirror instruction processing devices share memory or have their own memory; the interconnection mode of the plurality of the matrix mirror instruction processing devices is an arbitrary interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing device, the device comprising:

The machine learning computing device, universal interconnection interface, and other processing devices described in the second aspect above;

The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip, where the machine learning chip includes the machine learning network computing device described in the second aspect or the combined processing device described in the third aspect.

According to a fifth aspect of the present disclosure, a machine learning chip packaging structure is provided, and the machine learning chip packaging structure includes the machine learning chip described in the fourth aspect.

According to a sixth aspect of the present disclosure, there is provided a board card including the machine learning chip packaging structure described in the fifth aspect.

According to a seventh aspect of the present disclosure, an electronic device is provided, and the electronic device includes the machine learning chip described in the fourth aspect or the board card described in the sixth aspect.

According to an eighth aspect of the present disclosure, a method for processing a matrix mirroring instruction is provided. The method is applied to an apparatus for processing a matrix mirroring instruction, and the method includes:

Parse the received matrix mirroring instruction, obtain the opcode and operation field of the matrix mirroring instruction, and determine the matrix to be mirrored and the target address required to execute the matrix mirroring instruction according to the operation code and the operation field , and determine the mirroring strategy required for mirroring;

Perform mirroring processing on the matrix to be mirrored according to the mirroring strategy to obtain a mirrored matrix, and store the mirrored matrix in the target address,

Wherein, the operation code is used to indicate that the processing performed by the matrix mirroring instruction on the matrix is mirror processing, and the operation field includes the address of the matrix to be mirrored and the target address.

In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Cameras, projectors, watches, headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

In some embodiments, the vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical Equipment includes MRI machines, ultrasound machines and/or electrocardiographs.

The matrix mirror instruction processing method, device, and related products provided by the embodiments of the present disclosure include a control module and a processing module. The control module is used to parse the received matrix mirroring instruction, obtain the operation code and operation field of the matrix mirroring instruction, and determine the matrix to be mirrored and the target address required to execute the matrix mirroring instruction according to the operation code and operation field. The processing module is used for performing mirror processing on the mirror matrix to be mirrored according to the mirroring strategy, to obtain the mirrored matrix, and store the mirrored matrix into the target address. The matrix mirroring instruction processing method, device and related products provided by the embodiments of the present disclosure have a wide range of applications, and the processing efficiency and processing speed of performing mirroring processing on a matrix according to the matrix mirroring instruction are high.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

1a and 1b illustrate block diagrams of a combined processing apparatus according to an embodiment of the present disclosure.

FIG. 2 shows a schematic structural diagram of a board according to an embodiment of the present disclosure.

FIG. 3 shows a block diagram of an apparatus for processing a matrix mirroring instruction according to an embodiment of the present disclosure.

FIG. 4 shows a block diagram of a matrix mirror instruction processing apparatus according to an embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of an application scenario of an apparatus for processing a matrix mirroring instruction according to an embodiment of the present disclosure.

FIG. 6 shows a flowchart of a method for processing a matrix mirroring instruction according to an embodiment of the present disclosure.

Detailed ways

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures denote elements that have the same or similar functions. While various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present disclosure may be practiced without certain specific details. In some instances, methods, means, components and circuits well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.

As neural network algorithms are more and more widely used in image recognition, speech recognition, natural language processing and other fields, the complexity of neural network algorithms is getting higher and higher, and the types and quantities of data operations involved are increasing. Among them, a matrix is a common data form in neural network algorithms, consisting of numbers and/or characters. The processing of the matrix in the neural network algorithm includes mirroring the matrix. In the related art, it is necessary to perform mirror image processing on the matrix, which is inefficient and slow.

The present disclosure provides a machine learning computing device, the machine learning computing device can perform related operations of neural network algorithms, and the machine learning computing device can include one or more for mirroring a matrix according to a received matrix mirroring instruction. The matrix mirroring instruction processing device is used to obtain the matrix to be mirrored and control information from other processing devices, and execute the specified machine learning operation. The machine learning computing device can obtain matrix mirroring instructions from other machine learning computing devices or non-machine learning computing devices, and transmit the execution results to peripheral devices (also called other processing devices) through the I/O interface. Peripherals such as camera, monitor, mouse, keyboard, network card, wifi interface, server. When more than one matrix mirror instruction processing device is included, the matrix mirror command processing devices can be linked and transmitted through a specific structure, for example, interconnected and transmitted through the PCIE bus to support larger-scale neural network operations. At this time, the same control system can be shared, or there can be independent control systems; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

The machine learning computing device has high compatibility and can be connected with various types of servers through the PCIE interface.

FIG. 1a shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. As shown in Fig. 1a, the combined processing device includes the above-mentioned machine learning computing device, a general interconnection interface and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete the operation specified by the user.

Other processing devices include one or more processor types among general-purpose/special-purpose processors such as a central processing unit (CPU), a graphics processing unit (GPU), and a neural network processor. The number of processors included in other processing devices is not limited. Other processing devices serve as the interface between the machine learning computing device and external data and control, including data transfer, to complete the basic control of starting and stopping the machine learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

A universal interconnect interface for transferring data and control instructions between machine learning computing devices and other processing devices. The machine learning computing device obtains required input data from other processing devices, and writes it into a storage device on-chip of the machine learning computing device; it can obtain control instructions from other processing devices and write it into the control cache on the machine learning computing device chip; The data in the storage module of the machine learning computing device can be read and transmitted to other processing devices.

Fig. 1b shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 1b, the combined processing device may further include a storage device, and the storage device is respectively connected to the machine learning computing device and other processing devices. The storage device is used to save data in the machine learning computing device and other processing devices, and is especially suitable for data that cannot be fully stored in the internal storage of the machine learning computing device or other processing devices.

The combined processing device can be used as an SOC system for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnection interface of the combined processing device is connected to certain components of the apparatus. Some components such as camera, monitor, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above-mentioned machine learning computing device or combined processing device.

The present disclosure provides a machine learning chip packaging structure, and the machine learning chip packaging structure includes the above-mentioned machine learning chip.

The present disclosure provides a board, and FIG. 2 shows a schematic structural diagram of the board according to an embodiment of the present disclosure. As shown in FIG. 2 , the board includes the above-mentioned machine learning chip packaging structure or the above-mentioned machine learning chip. In addition to the machine learning chip 389 , the board may also include other supporting components, including but not limited to: a storage device 390 , an interface device 391 and a control device 392 .

The storage device 390 is connected to the machine learning chip 389 (or the machine learning chip in the machine learning chip package structure) through a bus for storing data. The memory device 390 may include groups of memory cells 393 . Each group of storage units 393 is connected to the machine learning chip 389 through a bus. It can be understood that each group of storage units 393 may be DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, the memory device 390 may include four sets of memory cells 393 . Each set of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include four 72-bit DDR4 controllers inside, where 64 bits of the 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 393, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each set of memory cells 393 includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling the DDR is provided in the machine learning chip 389 for controlling data transmission and data storage of each storage unit 393 .

The interface device 391 is electrically connected to the machine learning chip 389 (or the machine learning chip within the machine learning chip package structure). The interface device 391 is used to realize data transmission between the machine learning chip 389 and an external device (such as a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted by the server to the machine learning chip 289 through a standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0 X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 391 may also be other interfaces, and the present disclosure does not limit the specific expression forms of the other interfaces, as long as the interface device can realize the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (such as a server) by the interface device.

The control device 392 is electrically connected to the machine learning chip 389 . The control device 392 is used to monitor the state of the machine learning chip 389 . Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a Micro Controller Unit (MCU). For example, the machine learning chip 389 may include multiple processing chips, multiple processing cores or multiple processing circuits, and may drive multiple loads. Therefore, the machine learning chip 389 can be in different working states such as multi-load and light-load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and/or multiple processing circuits in the machine learning chip.

The present disclosure provides an electronic device including the above-mentioned machine learning chip or board.

Electronic devices may include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, Headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

Vehicles may include aircraft, ships and/or vehicles. Household appliances may include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods. Medical equipment may include MRI machines, ultrasound machines and/or electrocardiographs.

FIG. 3 shows a block diagram of an apparatus for processing a matrix mirroring instruction according to an embodiment of the present disclosure. As shown in FIG. 3 , the device includes a control module 11 and a processing module 12 .

The control module 11 is configured to parse the received matrix mirroring instruction, obtain the operation code and operation field of the matrix mirroring instruction, and determine the matrix to be mirrored and the target address required to execute the matrix mirroring instruction according to the operation code and the operation field, and Determine the mirroring strategy required for mirroring. The operation code is used to indicate that the processing performed by the matrix mirroring instruction on the matrix data is mirror processing, and the operation domain includes the address of the matrix to be mirrored and the target address.

The processing module 12 performs mirroring processing on the to-be-mirrored matrix according to the mirroring strategy, obtains the mirrored matrix, and stores the mirrored matrix in the target address.

In this embodiment, the matrix to be mirrored may be a data set formed by a plurality of numbers and/or characters arranged in an array. The mirroring process is a transformation process on the matrix, and the matrix to be mirrored is folded along a specific inverted straight line (in a two-dimensional plane) or a specific inverted plane (in a three-dimensional space) to obtain a mirrored matrix. For example, if the matrix to be mirrored is in a two-dimensional plane, the mirroring strategy may include at least one of folding the matrix to be mirrored along the horizontal direction of the matrix to be mirrored and folding the matrix to be mirrored along the vertical direction of the matrix to be mirrored . If the matrix to be mirrored is in three-dimensional space, the mirroring strategy may include folding the matrix to be mirrored along the horizontal plane of the matrix to be mirrored, folding the matrix to be mirrored along the vertical plane of the matrix to be mirrored, and folding the matrix to be mirrored along the vertical plane of the matrix to be mirrored, and the vertical plane of the horizontal plane. The plane will be mirrored matrix into at least one of the folds. The mirroring strategy may include parameters required for mirroring, such as flipped straight lines and flipped planes required for mirroring the matrix to be mirrored. The matrix mirroring instruction may perform one or more mirroring processes on the matrix, which is not limited in the present disclosure.

For example, it is assumed that the matrix to be mirrored is [[1,4,7],[2,5,8],[3,6,9]]. If the mirroring strategy is determined to be "horizontal mirroring" according to the matrix mirroring instruction, the device can obtain the mirrored matrix [[3,6,9],[2,5,8],[1, 4,7]]. If the symmetric strategy is determined to be "vertical mirroring" according to the matrix mirroring instruction, after the device performs vertical mirroring processing on the matrix to be mirrored, the symmetric post-matrix [[9,6,3],[8,5,2],[7 ,4,1]].

In this embodiment, the control module may acquire the matrix to be mirrored from the address of the matrix to be mirrored. The address of the matrix to be mirrored may be a physical address such as the first address for storing the matrix to be mirrored, or a logical address or a linear address. The control module may store the matrix to be mirrored in the target address. The target address can be a physical address such as the first address of the matrix after storing the mirror, or a logical address or a linear address. The present disclosure does not limit the representation of the mirror matrix address and the target address. . The control module can obtain the matrix mirroring instruction and the matrix to be mirrored through the data input and output unit, and the data input and output unit can be one or more data I/O interfaces or I/O pins.

In this embodiment, an operation code and an operation field may be included for a matrix mirroring instruction. The opcode may be the part of the instruction or field (usually represented by code) specified in the computer program to perform the operation, and the instruction sequence number, which is used to inform the device that executes the instruction which instruction needs to be executed. The operation domain can be the source of all data required to execute the corresponding instruction. All the data required to execute the corresponding instruction includes the matrix to be mirrored, the corresponding mirroring strategy, or the address of the matrix to be mirrored and the corresponding mirroring strategy, etc. . For example, the operation domain may include the address of the matrix to be mirrored and the target address.

It should be understood that those skilled in the art can set the instruction format of the matrix mirroring instruction and the included operation codes and operation fields as required, which is not limited in the present disclosure.

In this embodiment, the apparatus may include one or more control modules and one or more processing modules, and the number of the control modules and the processing modules may be set according to actual needs, which is not limited in the present disclosure. When the device includes a control module, the control module can receive a matrix mirroring instruction and control one or more processing modules to perform mirroring processing. When the device includes multiple control modules, the multiple control modules can respectively receive the matrix mirroring instructions, and control one or more corresponding processing modules to perform mirroring processing.

The matrix mirror instruction processing apparatus provided by the embodiment of the present disclosure includes a control module and a processing module. The control module is used to parse the received matrix mirroring instruction, obtain the opcode and operation field of the matrix mirroring instruction, and determine the matrix to be mirrored and the target address required to execute the matrix mirroring instruction according to the opcode and operation field, and determine the The mirroring policy required for mirroring. The processing module performs mirroring processing on the mirroring matrix according to the mirroring strategy, obtains the mirrored matrix, and stores the mirrored matrix in the target address. The apparatus for processing a matrix mirroring instruction provided by the embodiment of the present disclosure has a wide range of applications, and performs mirroring processing on a matrix according to the matrix mirroring instruction with high processing efficiency and high processing speed.

In a possible implementation, the operation domain may further include the input shape of the matrix to be mirrored. The processing module 12 may also be configured to perform mirror processing on the matrix to be mirrored according to the input shape and the mirroring strategy to obtain a mirrored matrix.

In this implementation manner, it is convenient to perform symmetric processing on the matrix according to the input shape of the matrix to be mirrored, and the shape of the symmetric matrix can also be determined according to the input shape of the matrix to be mirrored. The shape of the matrix can be represented by the number of numbers and/or characters on the rows and columns of the matrix to be mirrored. For example, the matrix 1 to be mirrored is [[0,1,1],[0,1,-1]], and the shape of the matrix 1 to be mirrored is 3×2, that is, the matrix 1 to be processed has 3 rows, 2 Column, consisting of 6 numbers.

In a possible implementation manner, the default input shape of the matrix to be mirrored may be preset. When the input shape of the matrix to be mirrored is not included in the operation domain, the default input shape of the matrix to be mirrored may be determined as the input shape of the matrix to be mirrored of the current matrix mirroring instruction. This disclosure does not limit this.

In one possible implementation, the operation domain may further include the output shape of the mirrored matrix. The processing module 12 is further configured to perform mirror processing on the matrix to be mirrored according to the output shape and the mirroring strategy to obtain a mirrored matrix.

In this implementation, the output shape may be the shape of the mirrored matrix. For example, the mirrored matrix is [[1,0],[0,1],[-1,0]], and the shape of the mirrored matrix is 2×3, that is, the mirrored matrix has 2 rows and 3 columns , which consists of 6 numbers.

In a possible implementation, the default output shape of the mirrored matrix can be preset. When the output shape of the mirrored matrix is not included in the operation domain, the default output shape of the mirrored matrix can be determined as the output shape of the mirrored matrix of the current matrix mirroring instruction. This disclosure does not limit this.

In a possible implementation, the operation domain may also be used to indicate a mirroring policy.

In one possible implementation, the opcode may also be used to indicate a mirroring strategy.

In a possible implementation manner, the mirroring strategy may be determined according to the opcode or operation domain of the matrix mirroring instruction. The default mirroring policy of the matrix to be mirrored can also be preset. When the operation domain does not contain the mirroring strategy of the matrix to be mirrored, the default mirroring strategy of the matrix to be mirrored may be determined as the mirroring strategy of the matrix to be mirrored of the current matrix mirroring instruction.

FIG. 4 shows a block diagram of a matrix mirror instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 4 , the apparatus for processing a matrix mirroring instruction may further include: a storage module 13 for storing the matrix to be mirrored.

In this implementation, the storage module may include one or more of a memory, a cache, and a register, and the cache may include a temporary cache. The matrix to be mirrored can be stored in the memory, cache and/or register in the storage module as required, which is not limited in the present disclosure.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In a possible implementation manner, as shown in FIG. 4 , the control module 11 may include an instruction storage sub-module 111 , an instruction processing sub-module 112 and a queue storage sub-module 113 .

The instruction storage sub-module 111 is used for storing matrix mirroring instructions.

The instruction processing sub-module 112 is used for parsing the matrix mirroring instruction to obtain the operation code and operation domain of the matrix mirroring instruction.

The queue storage sub-module 113 is used to store an instruction queue, and the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include matrix mirroring instructions. The plurality of instructions to be executed may include and may also include other computational instructions related to the matrix mirroring instructions.

In this implementation manner, the execution order of the plurality of to-be-executed commands can be arranged according to the receiving time and priority level of the to-be-executed commands to obtain the command queue, so as to execute the plurality of to-be-executed commands in sequence according to the command queue.

In a possible implementation manner, as shown in FIG. 4 , the control module 11 may further include a dependency relationship processing sub-module 114 .

The dependency relationship processing sub-module 114 is configured to, when it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has a dependency relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the dependency relationship processing sub-module 114 can process the first to-be-executed instruction. A to-be-executed instruction is cached in the instruction storage sub-module 112 , and after the execution of the zeroth to-be-executed instruction is completed, the first to-be-executed instruction is extracted from the instruction storage sub-module 112 and sent to the processing module 12 . Wherein, the first to-be-executed instruction and the zeroth to-be-executed instruction are instructions in a plurality of to-be-executed instructions.

The dependency relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: a first storage address range for storing data required by the first instruction to be executed and data required for storing the zeroth instruction to be executed The zeroth memory address range of has overlapping regions. Conversely, if there is no dependency between the first instruction to be executed and the zeroth instruction to be executed, it may be that the first storage address interval and the zeroth storage address interval have no overlapping area.

In this way, according to the dependencies between the instructions to be executed, after the execution of the previous instruction to be executed is completed, the subsequent instruction to be executed is executed to ensure the accuracy of the operation result.

In a possible implementation manner, the instruction format of the matrix mirroring instruction may be:

Rotate2 type dst src src_shape dst_shape

Among them, Rotate2 is the operation code, and type, dst, src, src_shape, and dst_shape are the operation fields. Rotate2 is used to indicate that the instruction is a matrix mirroring instruction. type is the mirroring strategy. dst is the target address. src is the address of the matrix to be mirrored. src_shape is the input shape. dst_shape is the output shape.

Rotate2_type dst src src_shape dst_shape

In a possible implementation manner, the instruction format of the matrix mirroring instruction may be:

Among them, Rotate2_type is the operation code, and dst, src, src_shape, and dst_shape are the operation fields. Rotate2 in Rotate2_type is used to indicate that the instruction is a matrix mirroring instruction, and type in Rotate2_type is a mirroring strategy. dst is the target address. src is the address of the matrix to be mirrored. src_shape is the input shape. dst_shape is the output shape.

It should be understood that those skilled in the art can set the operation code of the matrix mirroring instruction, the operation code in the instruction format and the position of the operation field as required, which is not limited in the present disclosure.

In a possible implementation manner, the apparatus may be provided in a graphics processing unit (Graphics Processing Unit, GPU for short), a central processing unit (Central Processing Unit, CPU for short), and an embedded neural-network processing unit (Neural-network Processing Unit, abbreviated as NPU) among one or more of them.

It should be noted that although the above embodiments are used as examples to describe the matrix mirroring instruction processing apparatus as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preferences and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

Application example

In the following, an application example according to the embodiment of the present disclosure is given in conjunction with "using a matrix mirroring instruction processing apparatus to perform mirroring processing on a matrix image to be mirrored" as an exemplary application scenario, so as to facilitate the understanding of the flow of the matrix mirroring instruction processing apparatus. Those skilled in the art should understand that the following application examples are only for the purpose of facilitating the understanding of the embodiments of the present disclosure, and should not be regarded as limitations of the embodiments of the present disclosure.

FIG. 5 shows a schematic diagram of an application scenario of an apparatus for processing a matrix mirroring instruction according to an embodiment of the present disclosure. As shown in FIG. 5 , the process of processing the matrix mirroring instruction by the apparatus for processing the matrix mirroring instruction is as follows.

Example 1

After receiving the matrix mirroring instruction 1 (Rotate2_type 200 100 S1 S2 ), the control module 11 parses the matrix mirroring instruction, and obtains the operation code and operation domain of the matrix mirroring instruction 1 . The opcode of this matrix mirror instruction 1 is Rotate2_type. According to the opcode, it can be determined that the instruction is a matrix mirroring processing instruction, and the mirroring strategy is type. According to the operation field, it can be determined: the address of the matrix to be mirrored is 100, the input shape is S1, the target address is 200, and the output shape is S2. Further, the control module 11 obtains the matrix 1 to be mirrored whose input shape is S1 from the address 100 of the matrix to be mirrored.

The processing module 12 performs mirror processing on the mirror matrix 1 to be mirrored according to the mirroring strategy, obtains the mirror matrix 1', and stores the mirror matrix 1' in the target address 200.

Among them, the matrix mirroring instruction 1 can be the above Rotate2_type 200 100 S1 S2, and it can also be Rotate2 type 200 100 S1 S2, the two are instructions of different instruction formats and represent the same processing process, the matrix mirroring instruction device for the two The processing process is similar and will not be repeated here.

The above processing process is detailed in the above related description.

In this way, the apparatus for processing the matrix mirroring instruction can quickly and efficiently perform mirroring processing on the matrix according to the matrix mirroring instruction.

FIG. 6 shows a flowchart of a method for processing a matrix mirroring instruction according to an embodiment of the present disclosure. As shown in FIG. 6 , the method is applied to the above-mentioned matrix mirror instruction processing apparatus, and the method includes step S51 and step S52.

In step S51, the received matrix mirroring instruction is parsed, the operation code and operation field of the matrix mirroring instruction are obtained, and the matrix to be mirrored and the target address required to execute the matrix mirroring instruction are determined according to the operation code and the operation field, and the The mirroring policy required for mirroring. The operation code is used to indicate that the processing performed by the matrix mirroring instruction on the matrix is mirror processing, and the operation domain includes the address of the matrix to be mirrored and the target address.

In step S52, mirroring is performed on the to-be-mirrored matrix according to the mirroring strategy to obtain the mirrored matrix, and the mirrored matrix is stored in the target address.

In a possible implementation, the operation domain may further include the input shape of the matrix to be mirrored. Wherein, performing mirror processing on the to-be-mirrored matrix according to the mirroring strategy to obtain the mirrored matrix may include: performing mirroring processing on the to-be-mirrored matrix according to the output shape and the mirroring strategy to obtain the mirrored matrix.

In a possible implementation manner, the operation domain may further include the output shape of the mirrored matrix, wherein performing mirroring processing on the to-be-mirrored matrix according to the mirroring strategy to obtain the mirrored matrix may include: according to the output shape and the mirroring strategy, the mirrored matrix is to be mirrored. The matrix is mirrored to obtain the mirrored matrix.

In a possible implementation, the operation domain may also be used to indicate a mirroring policy.

In one possible implementation, the opcode may also be used to indicate a mirroring strategy.

In a possible implementation manner, the method may further include: storing the matrix to be mirrored.

In a possible implementation manner, the received matrix mirroring instruction is parsed to obtain the opcode and operation field of the matrix mirroring instruction, which may include:

Store matrix mirroring instructions;

Analyze the matrix mirroring instruction to obtain the opcode and operation domain of the matrix mirroring instruction;

An instruction queue is stored, and the instruction queue includes multiple instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include matrix mirroring instructions.

In a possible implementation, the method may further include:

When it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has a dependency relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the first to-be-executed instruction is cached, and after it is determined that the zeroth to-be-executed instruction is executed , control the execution of the first instruction to be executed,

Wherein, the dependency relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

It should be noted that although the above embodiments are used as examples to describe the matrix mirror instruction processing method as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

The matrix mirroring instruction processing method provided by the embodiment of the present disclosure has a wide range of applications, and has high processing efficiency and high processing speed for the matrix mechanical energy mirroring.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Because in accordance with the present application, certain steps may be performed in other orders or concurrently. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

In the embodiments provided in the present disclosure, it should be understood that the disclosed systems and devices may be implemented in other manners. For example, the system and device embodiments described above are only illustrative, for example, the division of devices, devices, and modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules may be combined. Or it may be integrated into another system or device, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices, devices or modules, which may be in electrical or other forms.

Modules described as separate components may or may not be physically separated, and components shown as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present disclosure may be integrated into one processing unit, or each module may exist physically alone, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, or can be implemented in the form of software program modules.

The integrated modules, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer-readable memory. Based on such understanding, the technical solutions of the present disclosure essentially or the parts that contribute to the prior art or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a memory, Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash disk , Read-only memory (English: Read-Only Memory, referred to as: ROM), random access device (English: Random Access Memory, referred to as: RAM), magnetic disk or optical disk, etc.

The embodiments of the present application have been introduced in detail above, and the principles and implementations of the present application are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; at the same time, for Persons of ordinary skill in the art, based on the idea of the present application, will have changes in the specific implementation manner and application scope. In summary, the contents of this specification should not be construed as limitations on the present application.

Claims (17)

1. A matrix mirroring instruction processing apparatus, the apparatus comprising:

the control module is used for analyzing the received matrix mirror image instruction, obtaining an operation code and an operation domain of the matrix mirror image instruction, determining a matrix to be mirrored and a target address required by executing the matrix mirror image instruction according to the operation code and the operation domain, and determining a mirror image strategy required by mirror image processing;

a processing module for carrying out mirror image processing on the matrix to be mirror image according to the mirror image strategy to obtain a matrix after mirror image and storing the matrix after mirror image into the target address,

the operation code is used for indicating that the matrix mirroring instruction processes the matrix data to be mirrored, and the operation domain comprises the matrix address to be mirrored and the target address.

2. The apparatus of claim 1, wherein the operation domain further comprises input shapes of a matrix to be mirrored,

the processing module is further configured to perform mirror image processing on the matrix to be mirrored according to the input shape and the mirror image policy to obtain a matrix after mirror image processing.

3. The apparatus of claim 1, wherein the operation domain further comprises an output shape of a mirrored matrix,

the processing module is further configured to perform mirror image processing on the matrix to be mirrored according to the output shape and the mirror image policy to obtain a matrix after mirror image processing.

4. The apparatus of claim 1, wherein the operation domain is further configured to indicate a mirroring policy.

5. The apparatus of claim 1, wherein the opcode is further configured to indicate the mirroring policy.

6. The apparatus of claim 1,

the device further comprises: a storage module for storing the matrix to be mirrored,

wherein the control module comprises:

the instruction storage submodule is used for storing the matrix mirror image instruction;

the instruction processing submodule is used for analyzing the matrix mirror image instruction to obtain an operation code and an operation domain of the matrix mirror image instruction;

a queue storage submodule, configured to store an instruction queue, where the instruction queue includes multiple instructions to be executed that are sequentially arranged according to an execution order, where the multiple instructions to be executed include the matrix mirroring instruction,

wherein, the control module further comprises:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the dependency relationship between the first instruction to be executed in the plurality of instructions to be executed and a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the processing module,

wherein the dependency relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

7. A machine learning arithmetic device, the device comprising:

one or more matrix mirroring instruction processing devices according to any one of claims 1 to 6, configured to obtain a matrix to be mirrored and control information from another processing device, perform a specified machine learning operation, and transmit an execution result to the other processing device through an I/O interface;

when the machine learning arithmetic device comprises a plurality of matrix mirroring instruction processing devices, the plurality of matrix mirroring instruction processing devices can be connected through a specific structure and transmit data;

the matrix mirroring instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; the matrix mirror image instruction processing devices share the same control system or own respective control systems; the matrix mirror image instruction processing devices share a memory or own memories; the interconnection mode of the matrix mirror image instruction processing devices is any interconnection topology.

8. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 7;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

9. A machine learning chip, the machine learning chip comprising:

the machine learning arithmetic device according to claim 7 or the combined processing device according to claim 8.

10. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 9.

11. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface apparatus and a control device and a machine learning chip according to claim 9;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

12. A matrix mirroring instruction processing method is applied to a matrix mirroring instruction processing device, and comprises the following steps:

analyzing a received matrix mirror image instruction to obtain an operation code and an operation domain of the matrix mirror image instruction, determining a matrix to be mirrored and a target address required by executing the matrix mirror image instruction according to the operation code and the operation domain, and determining a mirror image strategy required by mirror image processing;

performing mirror image processing on the matrix to be mirrored according to the mirror image strategy to obtain a matrix after mirror image, storing the matrix after mirror image into the target address,

the operation code is used for indicating that the matrix mirror image instruction processes the matrix as mirror image processing, and the operation domain comprises the address of the matrix to be mirrored and the target address.

13. The method of claim 12, wherein the operation domain further comprises input shapes of a matrix to be mirrored,

performing mirror image processing on the matrix to be mirrored according to the mirror image strategy to obtain a matrix after mirror image, including:

and carrying out mirror image processing on the matrix to be mirror image according to the input shape and the mirror image strategy to obtain the matrix after mirror image.

14. The method of claim 12, wherein the operation domain further comprises an output shape of the mirrored matrix,

performing mirror image processing on the matrix to be mirrored according to the mirror image strategy to obtain a matrix after mirror image, including:

and carrying out mirror image processing on the matrix to be mirror image according to the output shape and the mirror image strategy to obtain the matrix after mirror image.

15. The method of claim 12, wherein the operation domain is further configured to indicate a mirroring policy.

16. The method of claim 12, wherein the opcode is further used to indicate the mirroring policy.

17. The method of claim 12,

the method further comprises the following steps: the matrix to be mirrored is stored and,

the method for analyzing the received matrix mirror image instruction to obtain the operation code and the operation domain of the matrix mirror image instruction comprises the following steps:

storing the matrix mirroring instruction;

analyzing the matrix mirror image instruction to obtain an operation code and an operation domain of the matrix mirror image instruction;

storing an instruction queue, the instruction queue comprising a plurality of instructions to be executed arranged in sequence according to an execution order, the plurality of instructions to be executed comprising the matrix mirroring instruction,

wherein the method further comprises:

when determining that a first to-be-executed instruction in the plurality of to-be-executed instructions has a dependency relationship with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling execution of the first to-be-executed instruction,

wherein the dependency relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

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