CN111813373B - Random code generator with floating gate transistor type memory cell - Google Patents

Abstract

A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first programming path, a second programming path, a first reading path and a second reading path. The first programming path is connected between the first source line and the first bit line, the second programming path is connected between the first source line and the second bit line, the first reading path is connected between the second source line and the third bit line, and the second reading path is connected between the third source line and the fourth bit line. The two write buffers are connected to the first bit line and the second bit line, respectively. The two sensing circuits are respectively connected to the third bit line and the fourth bit line. The two sensing circuits generate a first output signal and a second output signal according to the read current on the read path, and the first output signal and the second output signal are respectively transmitted to the corresponding write-in buffer.

Description

Random code generator with floating gate transistor type memory cell

Technical field

The present invention is a random code generator, and in particular, it relates to a random code generator having a floating gate transistor type memory cell.

Background technique

Generally speaking, non-volatile memory can be divided into one-time programmable memory (OTP memory) and multi-time programmable memory (MTP memory). OTP memory is composed of multiple OTP storage units, and MTP memory is composed of multiple MTP storage units. In addition, OTP memory cells or MTP memory cells can be composed of floating gate transistors.

U.S. Patent No. 8,941,167 introduces OTP memory cells and MTP memory cells composed of floating gate transistors. Please refer to FIG. 1A and FIG. 1B , which illustrates a schematic diagram of a well-known OTP memory cell composed of a floating gate transistor and a bias voltage.

The OTP memory cell 100 includes a selection transistor Ms and a floating gate transistor Mf. The first terminal of the selection transistor Ms is connected to a source line SL, the control terminal of the selection transistor Ms is connected to the word line WL, the first terminal of the floating gate transistor Mf is connected to the second terminal of the selection transistor Ms, and the floating gate transistor The second end of Mf is connected to bit line BL. Among them, a program path and a read path can be provided between the source line SL and the bit line BL of the OTP memory cell 100 . That is, after providing appropriate bias voltage to the word line WL, the source line SL and the bit line BL, the floating gate transistor Mf in the OTP memory cell 100 can be programmed or read. Operation (readoperation).

As shown in FIG. 1B , during the programming operation (PGM), the source line SL receives the programming voltage Vpp, and the word line WL and the bit line BL receive the ground voltage (0V). For example, the programming voltage Vpp is 8V.

At this time, the selection transistor Ms is turned on, and the programming path between the source line SL and the bit line BL generates a program current (program current). Furthermore, in the floating gate transistor Mf, electrons are injected into the floating gate from the channel region of the floating gate transistor Mf, and the programming operation is completed.

In addition, during the read operation (READ), the source line SL receives the read voltage Vr, and the word line WL and the bit line BL receive the ground voltage (0V). For example, the read voltage Vr is 3.0V.

At this time, the selection transistor Ms is turned on, and a read current (readcurrent) is generated in the read path between the source line SL and the bit line BL. Furthermore, the size of the read current can be determined depending on whether the floating gate in the floating gate transistor Mf stores electrons. For example, when no electrons are stored in the floating gate, the read current is very small and approaches zero. In addition, when electrons are stored in the floating gate, the read current is larger. Therefore, the storage state of the OTP memory cell 100 can be determined according to the read current on the bit line BL.

For example, a sense amplifier (not shown) is provided connected to the bit line BL, and a reference current is set in the sense amplifier. When the read current is less than the reference current, the sense amplifier may determine that the floating gate transistor Mf in the OTP memory unit 100 is in the first storage state. When the read current is greater than the reference current, the sense amplifier may determine that the floating gate transistor Mf in the OTP memory unit 100 is in the second storage state.

Please refer to FIGS. 2A and 2B , which illustrate a schematic diagram of a conventional MTP memory cell composed of a floating gate transistor and its bias voltage.

The MTP memory cell 200 includes a selection transistor Ms, a floating gate transistor Mf, and a capacitor Ce. The first terminal of the selection transistor Ms is connected to a source line SL, the control terminal of the selection transistor Ms is connected to the word line WL, the first terminal of the floating gate transistor Mf is connected to the second terminal of the selection transistor Ms, and the floating gate transistor The second end of Mf is connected to bit line BL. Furthermore, the capacitor Ce is connected between the floating gate and the erase line EL. Among them, the source line SL and the bit line BL of the MTP memory cell 200 can be used as a programming path and a read path, and the space between the floating gate and the erase line EL can be used as an erase path.

As shown in FIG. 2B , during the programming operation (PGM), the source line SL receives the programming voltage Vpp, and the word line WL, the bit line BL and the erase line EL receive the ground voltage (0V). For example, the programming voltage Vpp is 8V.

At this time, the selection transistor Ms is turned on, and the programming path between the source line SL and the bit line BL generates a program current (program current). Furthermore, in the floating gate transistor Mf, electrons are injected into the floating gate from the channel region of the floating gate transistor Mf, and the programming operation is completed.

In addition, during the read operation (READ), the source line SL receives the read voltage Vr, and the word line WL, the bit line BL and the erase line EL receive the ground voltage (0V). For example, the read voltage Vr is 3.0V.

At this time, the selection transistor Ms is turned on, and a read current (readcurrent) is generated in the read path between the source line SL and the bit line BL. Furthermore, whether the floating gate stores electrons can determine the size of the read current and determine the storage state of the MTP memory cell 200 . Similarly, a sense amplifier is provided connected to the bit line BL and receives the read current. According to the size of the read current, the sense amplifier can determine whether the floating gate transistor Mf in the MTP memory unit 200 is in the first storage state or the second storage state.

In addition, during the erase operation (ERS), the source line SL, the word line WL, and the bit line BL receive the ground voltage (0V), and the erase line EL receives the erase voltage Vee. For example, the erasure voltage Vee is 12.0V.

At this time, the electrons stored on the floating gate will exit to the erase line EL through the erase path. That is, the electrons stored on the floating gate will exit through the capacitor Ce to the erase line and leave the floating gate transistor Mf.

Physically unclonable function (PUF technology for short) is an innovative way to protect the data inside the semiconductor chip and prevent the internal data of the semiconductor chip from being stolen. According to PUF technology, the semiconductor chip can provide a random code. This random code can be used as a unique ID code on the semiconductor chip to protect the internal data.

Generally speaking, PUF technology uses the manufacturing variation of semiconductor chips to obtain unique random codes. This manufacturing variation includes process variation of semiconductors. In other words, even if there are precise process steps to produce a semiconductor chip, its random code is almost impossible to duplicate. Therefore, semiconductor chips with PUF technology are usually used in applications with high security requirements.

US Patent No. 9,613,714 discloses a random code generator with an antifuse transistor type memory cell, and uses the storage state of the memory cell as a random code. The purpose of the present invention is to use other types of storage units as random code generators.

Contents of the invention

The main purpose of the present invention is to propose a random code generator, including: a memory unit including a first programming path, a second programming path, a first reading path and a second reading path, wherein the The first programming path is connected between a first source line and a first bit line, the second programming path is connected between the first source line and a second bit line, and the first read path is connected Between a second source line and a third bit line, the second read path is connected between a third source line and a fourth bit line; a first write buffer is connected to the a first bit line; a second write buffer connected to the second bit line; a first sensing circuit connected to the third bit line, wherein the first sensing circuit is based on the first read path A first read current on the second write buffer generates a first output signal to the second write buffer; and a second sensing circuit is connected to the fourth bit line, wherein the second sensing circuit is based on the first A second read current on the two read paths generates a second output signal to the first write buffer; wherein, during a registration operation, the first programming path and the second programming path perform a programming operation, the first read path and the second read path perform a read operation, and when a logic level of the first output signal and the second output signal is different, the first programming path and the third One of the two programming paths stops performing the programming operation.

Description of drawings

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

1A and 1B are schematic diagrams of a known OTP memory cell composed of a floating gate transistor and its bias voltage.

2A and 2B are schematic diagrams of a known MTP memory cell composed of a floating gate transistor and its bias voltage.

Figure 3A shows the first embodiment of the random code generator of the present invention.

FIG. 3B is a flow chart of the random code generator during registration operation of the present invention.

4A to 4C are schematic diagrams of bias voltages when the random code generator of the present invention performs registration operations.

Figure 5 is a schematic diagram of a random code generator generating random codes.

FIG. 6 is another flow chart of the random code generator during registration operation of the present invention.

Figure 7 is a second embodiment of the random code generator of the present invention.

Figure 8 is a third embodiment of the random code generator of the present invention.

Detailed ways

The present invention utilizes the characteristics of the floating gate transistor to design a floating gate transistor type memory unit, and uses it as a PUF memory unit in a random code generator. Please refer to FIG. 3A , which illustrates a first embodiment of the random code generator of the present invention. The random code generator 300 includes a PUF storage unit c1, two write buffers 302 and 304 and two sensing circuits 312 and 314. Among them, the sensing circuits 312 and 314 may be sensing amplifiers.

According to the first embodiment of the present invention, the PUF memory cell c1 includes two programming paths and two reading paths. A first programming path is formed between the source line SLw and the bit line BLw, a second programming path is formed between the source line SLw and the bit line BLw', and a first reading path is formed between the source line SLr and the bit line BLr. path, a second read path is formed between the source line SLr' and the bit line BLr'. Furthermore, each path includes a floating gate transistor.

As shown in FIG. 3A, the first programming path includes a selection transistor Ms1 and a floating gate transistor Mf1. The first terminal of the selection transistor Ms1 is connected to a source line SLw, the control terminal of the selection transistor Ms1 is connected to the word line WL, and the second terminal of the selection transistor Ms1 is connected to the node a. The first terminal of the floating gate transistor Mf1 is connected to the node a, and the second terminal of the floating gate transistor Mf1 is connected to the bit line BLw.

The second programming path includes the selection transistor Ms1 and the floating gate transistor Mf2. The first terminal of the floating gate transistor Mf2 is connected to the node a, and the second terminal of the floating gate transistor Mf2 is connected to the bit line BLw'.

The first read path includes the selection transistor Ms2 and the floating gate transistor Mf3. The first terminal of the selection transistor Ms2 is connected to a source line SLr, the control terminal of the selection transistor Ms2 is connected to the word line WL, the first terminal of the floating gate transistor Mf3 is connected to the second terminal of the selection transistor Ms2, and the floating gate transistor The second end of Mf3 is connected to bit line BLr. In addition, the floating gate transistor Mf1 of the first programming path and the floating gate transistor Mf3 of the first read path have a shared floating gate. That is, the floating gate of the floating gate transistor Mf1 is connected to the floating gate of the floating gate transistor Mf3.

The second read path includes the selection transistor Ms3 and the floating gate transistor Mf4. The first terminal of the selection transistor Ms3 is connected to a source line SLr', the control terminal of the selection transistor Ms3 is connected to the word line WL, the first terminal of the floating gate transistor Mf4 is connected to the second terminal of the selection transistor Ms3, and the floating gate The second terminal of transistor Mf4 is connected to bit line BLr'. In addition, the floating gate transistor Mf2 of the second programming path and the floating gate transistor Mf4 of the second read path have a shared floating gate. That is, the floating gate of the floating gate transistor Mf2 is connected to the floating gate of the floating gate transistor Mf4.

Furthermore, the write buffer 302 in the random code generator 300 is connected to the bit line BLw, the write buffer 304 is connected to the bit line BLw', the sensing circuit 312 is connected to the bit line BLr, and the sensing circuit 314 is connected to the bit line BLr. Line BLr'.

According to the first embodiment of the present invention, when the random code generator 300 performs an enrolling operation, the sensing circuit 312 can generate an output signal Out to the write buffer 304 to interrupt the write buffer 304 operation. Similarly, the sensing circuit 314 can generate an output signal Out' to the write buffer 302 to interrupt the write buffer 302 operation.

Please refer to FIG. 3B , which shows a flow chart of the random code generator of the present invention during the registration operation.

First, the registration operation is started (step S320). During the registration operation, the first programming path and the second programming path of the random code generator 300 perform programming operations, and the first reading path and the second reading path perform reading operations.

Next, when the output signal Out and the output signal Out' are different (step S322), the random code generator 300 only uses a single programming path to perform the programming operation (step S324). That is, when one of the output signal Out and the output signal Out' changes the logic level, the random code generator 300 uses one of the first programming path and the second programming path to continue the programming operation, while the other programming path Stop programming operation. After that, the random code generator 300 completes the registration operation (step S326). It is explained in detail below.

Please refer to FIGS. 4A to 4C , which are schematic diagrams of bias voltages when the random code generator of the present invention performs a registration operation.

As shown in FIG. 4A, during the registration operation, the word line WL receives the ground voltage (0V), the source line SLw receives the programming voltage Vpp, and the source line SLr and the source line SLr' receive the read voltage Vr. In addition, the write buffer 302 provides a ground voltage (0V) to the bit line BLw, the write buffer 304 provides a ground voltage (0V) to the bit line BLw', and the sensing circuit 312 provides a first voltage (eg, 0.4V) to the bit line. BLr, the sensing circuit 314 provides a first voltage (eg, 0.4V) to the bit line BLr'. For example, the programming voltage Vpp is 7.25V, the read voltage Vr is 3.6V, and the first voltage is 0.4V. Of course, the first voltage may also be equal to the ground voltage (0V). That is, the programming voltage Vpp is greater than the read voltage Vr, the read voltage Vr is greater than the first voltage, and the first voltage is greater than or equal to the ground voltage (0V).

At this time, the selection transistors Ms1 to Ms3 are turned on, and the PUF memory unit c1 starts the registration operation. That is, the first programming path and the second programming path start to perform programming operations, and the first reading path and the second reading path start to perform reading operations.

According to the first embodiment of the present invention, in the early stage of the registration operation of the PUF memory unit c1, since the shared floating gates of the floating gate transistors Mf1 and Mf3 do not store electrons, the first read current of the first read path Ir1 is very small, close to zero. Similarly, since the shared floating gate of the floating gate transistors Mf2 and Mf4 does not store electrons, the second read current Ir2 of the second read path is very small, close to zero. Therefore, the reference current in the sensing circuit 312 is greater than the first read current Ir1, so that the output signal Out generates the first logic level "1", indicating that the floating gate transistors Mf1 and Mf3 are in the first storage state. in addition. The reference current in the sensing circuit 314 is also greater than the second read current Ir2, so that the output signal Out' generates a first logic level "1", indicating that the floating gate transistors Mf2 and Mf4 are in the first storage state. For example, the reference current in the sensing circuits 312 and 314 can be set to 2 μA.

As shown in FIG. 4B , due to manufacturing variation in the semiconductor process, the floating gate transistor Mf1 of the first programming path and the floating gate transistor Mf2 of the second programming path may be slightly different. This difference will cause most of the electrons to be injected into one of the two floating gate transistors Mf1 and Mf2 during the registration operation.

Taking FIG. 4B as an example, during the registration operation, the first programming current Ip1 on the first programming path is greater than the second programming current Ip2 on the second programming path. In other words, most of the electrons are injected into the floating gate transistor Mf1.

Since the shared floating gate of the floating gate transistors Mf1 and Mf3 begins to store electrons, and as the number of stored electrons increases, the first read current Ir1 generated by the floating gate transistor Mf3 on the first read path also increases. The bigger. In addition, since the shared floating gate of the floating gate transistors Mf2 and Mf4 only stores a small amount of electrons, the second read current Ir2 generated by the floating gate transistor Mf4 on the second read path rises much faster than the first read current. The speed at which current Ir1 rises.

Since the first read current Ir1 and the second read current Ir2 are rising but have not yet exceeded the reference currents in the sensing circuits 312 and 314, the output signal Out of the sensing circuit 312 and the output signal Out' of the sensing circuit 314 are are maintained at the first logic level "1".

As shown in FIG. 4C , after a specific amount of electrons are injected into the shared floating gate of the floating gate transistors Mf1 and Mf3, the first read current Ir1 on the first read path will be greater than the reference current in the sensing circuit 312, The output signal Out is caused to generate a second logic level "0", indicating that the floating gate transistors Mf1 and Mf3 change to the second storage state.

Furthermore, the sensing circuit 312 generates an output signal Out of the second logic level "0" to the write buffer 304, causing the write buffer 304 to stop operating, and further controls the bit line BLw' to be in a floating state. . Therefore, the second programming path stops the programming operation, and electrons are no longer injected into the floating gate of the floating gate transistor Mf2, so that the floating gate transistors Mf2 and Mf4 remain in the first storage state. At the same time, since the output signal Out' of the sensing circuit 314 is still maintained at the first logic level "1", the floating gate transistor Mf1 on the first programming path will continue to inject electrons.

In other words, when the output signal Out of the sensing circuit 312 is different from the output signal Out' of the sensing circuit 134, only a single programming path is left in the PUF memory unit c1 to continue the programming operation, and the other programming path stops the programming operation. Therefore, after the registration operation is completed, the floating gate transistors Mf1 and Mf3 change to the second storage state, and the floating gate transistors Mf2 and Mf4 remain in the first storage state.

In another situation, when the random code generator 300 performs a registration operation, the second programming current Ip2 of the second programming path may be greater than the first programming current Ip1 of the first programming path, causing most electrons to be injected into the floating gate transistor Mf2 . Therefore, after the registration operation is completed, the floating gate transistors Mf2 and Mf4 change to the second storage state, and the floating gate transistors Mf1 and Mf3 remain in the first storage state. The detailed operating principles are similar and will not be described again here.

From the above description, it can be seen that due to the manufacturing variation of the semiconductor process, the random code generator 300 cannot predict which floating gate transistor in the PUF memory unit c1 will be injected with a large number of electrons during the registration operation. Therefore, the first embodiment of the present invention The random code generator 300 can indeed use PUF technology to generate random codes.

After completing the registration operation, the random code generator 300 can perform the reading operation again and obtain the random code. According to an embodiment of the present invention, the random code generator 300 only performs a reading operation through the first reading path or the second reading path, so that the random code generator can generate a random code.

For illustration, the reading operation is performed using the first read path and the sensing circuit 312 as an example. Please refer to FIG. 5 , which shows a schematic diagram of a random code generator generating a random code. When the random code generator 300 performs a read operation after the registration operation is completed. The word line WL receives the ground voltage (0V), the source line SLr receives the read voltage Vr, and the sensing circuit 312 provides a first voltage (eg, 0.4V) to the bit line BLr. In addition, since the first programming path, the second programming path and the second reading path are not in operation, the write buffers 302, 304 and the sensing circuit 314 remain in standby, so that the bit lines BLw, BLw', BLr' in floating state.

As shown in Figure 5, when electrons are stored in the shared floating gate of the floating gate transistors Mf1 and Mf3, the first read current Ir1 generated on the first read path is greater than the reference current in the sensing circuit 312, and the sensing The circuit 312 generates the output signal Out of the second logic level "0" and serves as a bit in the random code.

On the contrary, if no electrons are stored in the shared floating gate of the floating gate transistors Mf1 and Mf3, the first read current Ir1 generated on the first read path is less than the reference current in the sensing circuit 312, and the sensing circuit 312 is An output signal Out of the first logic level "1" is generated and serves as a bit in the random code.

Furthermore, in an actual design, the word line WL of the random code generator 300 can be connected to multiple PUF memory cells, such as 8 PUF memory cells. Furthermore, when a column of PUF memory cells connected to the word line WL is first registered and then read, an 8-bit (one byte) random code can be generated.

In addition, the flow chart of the registration operation shown in FIG. 3B of the present invention can also be further modified. For example, during the registration operation and the output signal Out and the output signal Out' are the same, the random code generator 300 provides the programming voltage Vpp to the source line SLw. After confirming that the output signal Out is different from the output signal Out', when the random code generator 300 performs a programming operation on a single write path (step S324), the programming voltage Vpp can be increased, for example (from 7.25V to 7.5V). ), which can improve the programming efficiency of this single writing path and inject more electrons into the floating gate transistor on this single programming path.

In addition, after the random code generator 300 completes the registration operation, the storage states of the floating gate transistors Mf1 to Mf4 in the PUF storage unit c1 have been fixed and will not change. Therefore, interested parties can use electron beam inspection to scan the PUF memory unit c1 and further deduce the storage status and random code of the floating gate transistors Mf1 to Mf4. In this way, the random code of the random code generator 300 may be cracked, causing the data inside the semiconductor chip to be stolen.

Please refer to FIG. 6 , which shows another flow chart of the random code generator of the present invention during the registration operation. Compared with FIG. 3B , a scramble operation (scramble operation) is performed on the second programming path (step S610 ).

Because the random code generator 300 uses the first reading path and the sensing circuit 312 to perform a reading operation and generate a random code. That is, the storage states of the floating gate transistors Mf2 and Mf4 in the second read path and the second programming path can be changed arbitrarily without affecting the content of the random code. Therefore, the random code generator 300 can perform a scrambling action for the second programming path. For example, disruptive actions include random program operations.

For example, the random code generator 300 includes 8 PUF storage units. The random code generator 300 performs a random program operation on the second programming path in the eight PUF memory cells. That is, the storage state of the floating gate transistor Mf2 in the second programming path is randomly changed. After completing the random programming operation, even if electron beam inspection is used to scan the contents of the eight PUF memory cells, it is not easy to deduce the random code. Therefore, theft of data inside the semiconductor chip can be more effectively prevented.

Of course, if the random code generator 300 uses the second reading path and the sensing circuit 314 to perform a reading operation and generate a random code. Then the random code generator 300 can perform a scrambling action for the first programming path.

Please refer to FIG. 7 , which shows a second embodiment of the random code generator of the present invention. The difference between the random code generator 700 of the second embodiment and the random code generator 300 of the first embodiment lies in the structure of the sensing circuits 312 and 314. Only this difference is described below.

The sensing circuit 312 includes a switch 702 and a sensing amplifier 704. The first terminal of the switch 702 is connected to the bit line BLr. The second terminal of the switch 702 is connected to the sensing amplifier 704. The control terminal of the switch 702 receives the output. Signal Out'.

The sensing circuit 314 includes a switch 712 and a sensing amplifier 714. The first terminal of the switch 712 is connected to the bit line BLr', the second terminal of the switch 712 is connected to the sensing amplifier 714, and the control terminal of the switch 712 receives the output signal Out. . Among them, the switches 702 and 712 may be transmission gates.

According to the second embodiment of the present invention, when the random code generator 700 performs a registration operation, the switches 702 and 712 are in a closed state, and the sense amplifiers 704 and 714 respectively receive the first read current Ir1 and the second read current Ir1. Take the current Ir2 and generate the output signals Out and Out'.

In addition, when one of the two output signals Out and Out' changes the output logic level, the controlled switch becomes an open state. For example, when the output signal Out of the sense amplifier 704 changes from the first logic level "1" to the second logic level "0", in addition to causing the write buffer 304 to stop operating, the sense amplifier 704 further controls the output signal Out. The switch 712 in the test circuit 314 becomes open, causing the second read path to stop operating. That is, the second read path no longer generates the second read current Ir2. In this way, the random code generator 700 can reduce energy consumption.

Similarly, when the output signal Out' of the sense amplifier 714 changes from the first logic level "1" to the second logic level "0", in addition to causing the write buffer 302 to stop operating, the sense amplifier 714 further controls the output signal Out'. The switch 702 in the test circuit 312 becomes open, causing the first read path to stop operating.

Please refer to FIG. 8 , which shows a third embodiment of the random code generator of the present invention. The difference between the random code generator 800 of the third embodiment and the random code generator 300 of the first embodiment lies in the structure of the PUF storage unit ca, and two control paths are added to the PUF storage unit ca. Only this difference is described below.

The PUF storage unit ca further includes two capacitors C1 and C2. The first end of the capacitor C1 is connected to the shared floating gate of the floating gate transistors Mf1 and Mf3, and the second end of the capacitor C1 is connected to a control line CL1 and forms a first control path. The first end of the capacitor C2 is connected to the shared floating gate of the floating gate transistors Mf2 and Mf4, and the second end of the capacitor C2 is connected to a control line CL2 and forms a second control path.

Furthermore, the control lines CL1 and CL2 can receive the erase voltage Vee so that the control path in the PUF memory unit ca becomes an erase path to exit the electrons in the floating gate transistors Mf1˜Mf4. Therefore, the PUF storage unit ca is the MTP storage unit. Among them, the first erasure path is between the shared floating gate of the floating gate transistors Mf1 and Mf3 and the control line CL1, and the second erasure path is between the shared floating gate of the floating gate transistors Mf2 and Mf4 and the control line CL2. path. For example, the erasure voltage Vee is 12.0V.

As can be seen from the above description, the random code generator 800 can further perform an erase operation, so that the electrons stored in the floating gate transistors Mf1 and Mf3 exit the PUF memory unit ca through the first erasure path, and the floating gate transistors Mf1 and Mf3 The electrons stored in the transistors Mf2 and Mf4 exit the PUF memory unit ca through the second erasure path.

In addition, since the PUF storage unit ca of the random code generator 800 is an MTP storage unit. Therefore, during the registration operation of the random code generator 800, the scrambling operation of the second programming path may further include an erasure operation.

It is assumed that the random code generator 800 uses the first read path and the sensing circuit 312 to perform a read operation and generate a random code. The random code generator 800 can perform a scrambling action for the second programming path without changing the random code. Furthermore, disruptive actions include erasure operations and random programming operations.

For example, the random code generator 800 includes 8 PUF storage units. The random code generator 800 first performs an erase operation on the second erase path in the eight PUF memory cells, so that the floating gate transistors in the second programming path return to the first storage state. Then, the random code generator 800 performs a random programming operation on the second programming path of the eight PUF memory cells. Therefore, after completing the random programming operation, even if electron beam detection is used to scan the contents of the eight PUF memory cells, it is not easy to deduce the random code. Therefore, theft of data inside the semiconductor chip can be more effectively prevented.

Of course, if the random code generator 800 uses the second reading path and the sensing circuit 314 to perform a reading operation and generate a random code. Then the random code generator 800 can perform an erasure operation for the first erasure path. Afterwards, a random programming operation is performed on the first programming path.

It is particularly noted here that the structures of the random code generators 300, 700 and 800 described above can also be adjusted due to external requirements (such as area considerations). For example, the source lines SLr and SLr in the random code generators 300, 700, and 800 can share a well region so that the source lines are connected, thereby achieving the purpose of reducing the area.

As can be seen from the above description, the present invention proposes a random code generator with a floating gate transistor type memory unit. The PUF memory cell includes two programming paths and two read paths. After the registration operation, the two floating gate transistors on the two programming paths can have different storage states. Since the storage states of the two floating gate transistors on the two programming paths cannot be accurately predicted. Therefore, the random code generator of the present invention can indeed use PUF technology to generate random codes.

In summary, although the present invention has been disclosed through embodiments, they are not intended to limit the present invention. Those with ordinary skill in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

【Symbol Description】

100,200:storage unit

300,700,800: Random code generator

302,304: Write buffer

312,314: Sensing circuit

702,712: switch

704,714: Sense amplifier

S320～S326, S610: step process

Claims (18)

1. A random code generator comprising:

the memory cell comprises a first programming path, a second programming path, a first reading path and a second reading path, wherein the first programming path is connected between a first source line and a first bit line, the second programming path is connected between the first source line and a second bit line, the first reading path is connected between a second source line and a third bit line, and the second reading path is connected between a third source line and a fourth bit line;

a first write buffer connected to the first bit line;

a second write buffer connected to the second bit line;

a first sensing circuit connected to the third bit line, wherein the first sensing circuit generates a first output signal to the second write buffer according to a first read current on the first read path; and

a second sensing circuit connected to the fourth bit line, wherein the second sensing circuit generates a second output signal to the first write buffer according to a second read current on the second read path;

wherein, during a registration operation, the first programming path and the second programming path perform a programming operation, the first reading path and the second reading path perform a reading operation, and when the first output signal is different from the second output signal, one of the first programming path and the second programming path stops performing the programming operation;

after the registration operation, the first reading path is utilized to perform the reading operation, and a logic level of the first output signal is used as a bit of a random code.

2. The random code generator of claim 1, wherein the first programming path comprises:

a first select transistor, wherein a first end of the first select transistor is connected to the first source line, a second end of the first select transistor is connected to a node, and a control end of the first select transistor is connected to a word line; and

a first floating gate transistor, wherein a first end of the first floating gate transistor is connected to the node and a second end of the first floating gate transistor is connected to the first bit line.

3. The random code generator of claim 2, wherein the second programming path comprises:

the first selection transistor; and

a second floating gate transistor, wherein a first end of the second floating gate transistor is connected to the node and a second end of the second floating gate transistor is connected to the second bit line.

4. The random code generator of claim 3, wherein the first read path comprises:

a second select transistor, wherein a first terminal of the second select transistor is connected to the second source line, and a control terminal of the second select transistor is connected to the word line; and

a third floating gate transistor, wherein a first terminal of the third floating gate transistor is connected to a second terminal of the second select transistor, and a second terminal of the third floating gate transistor is connected to the third bit line;

wherein a floating gate of the first floating gate transistor is connected to a floating gate of the third floating gate transistor.

5. The random code generator of claim 4, wherein the second read path comprises:

a third select transistor, wherein a first terminal of the third select transistor is connected to the third source line, and a control terminal of the third select transistor is connected to the word line; and

a fourth floating gate transistor, wherein a first terminal of the fourth floating gate transistor is connected to a second terminal of the third select transistor, and a second terminal of the fourth floating gate transistor is connected to the fourth bit line;

wherein a floating gate of the second floating gate transistor is connected to a floating gate of the fourth floating gate transistor.

6. The random code generator of claim 5, wherein during the registration operation, the word line is provided with a ground voltage, the first source line is provided with a programming voltage, the second source line and the third source line are provided with a read voltage, the first bit line and the second bit line are provided with the ground voltage, the third bit line and the fourth bit line are provided with a first voltage, so that the first programming path and the second programming path perform the programming operation, and the first read path and the second read path perform the reading operation.

7. The random code generator of claim 6, wherein the programming voltage is greater than the reading voltage, the reading voltage is greater than the first voltage, and the first voltage is greater than or equal to the ground voltage.

8. The random code generator of claim 6, wherein the first output signal is at a first logic level when the first read current is less than a reference current; when the first reading current is larger than the reference current, the first output signal is at a second logic level; when the second reading current is smaller than the reference current, the second output signal is at the first logic level; when the second read current is greater than the reference current, the second output signal is at the second logic level.

9. The random code generator of claim 8, wherein the second write buffer receives the first output signal and stops the second programming path from performing the programming operation when the first output signal changes from the first logic level to the second logic level and the second output signal remains at the first logic level, and the first write buffer receives the second output signal and continues to perform the programming operation on the first programming path.

10. The random code generator of claim 9, wherein the programming voltage is increased as the first write buffer continues the programming operation on the first programming path.

11. The random code generator of claim 5, further comprising a first control path connected between a first control line and the floating gate of the first floating gate transistor and a second control path connected between a second control line and the floating gate of the second floating gate transistor.

12. The random code generator of claim 11, wherein the first control path includes a first capacitor connected between the first control line and the floating gate of the first floating gate transistor; and the second control path comprises a second capacitor connected between the second control line and the floating gate of the second floating gate transistor.

13. The random code generator of claim 12, wherein an erase operation and a random program operation are performed on the second program path before ending the registration operation.

14. The random code generator of claim 5, wherein the first sensing circuit comprises a first switch and a first sense amplifier, a first end of the first switch being connected to the third bit line, a second end of the first switch being connected to the first sense amplifier; the second sensing circuit comprises a second switch and a second sensing amplifier, wherein a first end of the second switch is connected to the fourth bit line, and a second end of the second switch is connected to the second sensing amplifier; the first sense amplifier generates the first output signal to the second switch and the second write buffer, and the second sense amplifier generates the second output signal to the first switch and the first write buffer.

15. The random code generator of claim 14, wherein when the first output signal changes from a first logic level to a second logic level and the second output signal remains at the first logic level, the second write buffer receives the first output signal and stops the second programming path from performing the programming operation, the second switch receives the first output signal and stops the second read path from performing the reading, and the first write buffer receives the second output signal and continues to perform the programming operation on the first programming path.

16. The random code generator of claim 1, wherein a scrambling operation is performed on the second programming path prior to ending the registration operation.

17. The random code generator of claim 16, wherein the scrambling operation comprises a random programming operation.

18. The random code generator of claim 1, wherein the second source line and the third source line are connected.