CN111816563B - Semiconductor device and method for forming the same - Google Patents
Semiconductor device and method for forming the same Download PDFInfo
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- CN111816563B CN111816563B CN201910295434.1A CN201910295434A CN111816563B CN 111816563 B CN111816563 B CN 111816563B CN 201910295434 A CN201910295434 A CN 201910295434A CN 111816563 B CN111816563 B CN 111816563B
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- 238000000034 method Methods 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000007789 gas Substances 0.000 claims description 23
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 20
- 229910000077 silane Inorganic materials 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 16
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 12
- 239000012495 reaction gas Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 6
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 5
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- 229910052751 metal Inorganic materials 0.000 description 3
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- 238000004380 ashing Methods 0.000 description 2
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- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device and a forming method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a device dense region and a device sparse region, and a fin part is formed on the substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans across the fin portion; forming first grooves in the fin parts on two sides of the pseudo gate structure of the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure of the device sparse region; forming a first stress layer in the first groove and the second groove; forming a sacrificial side wall on the side wall of the pseudo gate structure; forming a second stress layer on the first stress layer of the second trench; removing the sacrificial side wall; and (3) carrying out secondary epitaxial growth of a stress layer in the sparse region of the device, balancing the contact resistance of the sparse region and the dense region of the device, and improving the stability of the performance of the semiconductor device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin field effect transistor includes: the isolation structure covers part of the side wall of the fin part and is positioned on the substrate and spans the gate structure; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as semiconductor devices shrink in size, device density increases, resulting fin field effect transistors do not perform as stably.
Disclosure of Invention
The invention solves the problem of providing a semiconductor device and a forming method thereof, so that the performance of the formed semiconductor device is stable.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, wherein the substrate comprises a device dense region and a device sparse region, and a fin part is formed on the substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans across the fin portion; forming first grooves in the fin parts on two sides of the pseudo gate structure of the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure of the device sparse region; forming a first stress layer in the first groove and the second groove; forming a sacrificial side wall on the side wall of the pseudo gate structure; forming a second stress layer on the first stress layer of the second trench; and removing the sacrificial side wall.
Optionally, in the device dense region, the sacrificial sidewall covers the first stress layer in the first trench.
Optionally, the material of the sacrificial sidewall includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, organic matters or metals.
Optionally, the second stress layer is formed by an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas is silane.
A semiconductor device formed by the method includes: a substrate comprising a device dense region and a device sparse region; a fin located on the substrate; the dummy gate structure is positioned on the substrate and spans across the fin part; the first grooves are positioned in the fin parts at two sides of the pseudo gate structure of the device dense region; the second grooves are positioned in the fin parts at two sides of the pseudo gate structure of the device sparse region; a first stress layer located within the first trench and the second trench; and the second stress layer is positioned on the first stress layer in the second groove.
The invention also provides another method for forming the semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a device dense region and a device sparse region, and a fin part is formed on the substrate; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans across the fin portion; forming first grooves in the fin parts on two sides of the pseudo gate structure of the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure of the device sparse region; forming a sacrificial side wall on the side wall of the pseudo gate structure of the device dense region; forming a second stress layer in the second groove; removing the sacrificial side wall; and forming a first stress layer in the first groove and on the second stress layer.
Optionally, in the device dense region, the sacrificial sidewall covers the first trench.
Optionally, the semiconductor device is a POMS device, the method used for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas comprises silane and germanide gas.
Optionally, the semiconductor device is a NOMS device, the method used for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas comprises silane and phosphine gas.
A semiconductor device formed by the method includes: a substrate comprising a device dense region and a device sparse region; a fin located on the substrate; the dummy gate structure is positioned on the substrate and spans across the fin part; the first grooves are positioned in the fin parts at two sides of the pseudo gate structure of the device dense region; the second grooves are positioned in the fin parts at two sides of the pseudo gate structure of the device sparse region; a second stress layer located in the second trench; and a first stress layer positioned in the first groove and on the second stress layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
Forming a stress layer twice in the groove of the device sparse region, increasing the volume of the stress layer formed in the groove of the device sparse region, and facilitating the increase of the contact area between the contact hole and the source drain when the contact hole is formed subsequently, thereby reducing the contact resistance; meanwhile, after the stress layer is formed in the groove of the device sparse region twice, the contact resistance formed in the device sparse region and the contact resistance formed in the device dense region can be balanced in the subsequent use process of the semiconductor device, so that the stability of the semiconductor device is improved, and the contact resistance is reduced.
Drawings
Fig. 1 to 4 are schematic structural views of a semiconductor device forming process;
Fig. 5 to 12 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention;
Fig. 13 to 20 are schematic structural views of a semiconductor device forming process in the second embodiment of the present invention;
Fig. 21 to 30 are schematic structural views of a semiconductor device forming process in a third embodiment of the present invention;
Detailed Description
The performance stability of the semiconductor devices formed at present is poor.
Fig. 1 to 4 are schematic structural views of a semiconductor device forming process.
Referring to fig. 1, a substrate 100 is provided, including a device dense region 110, a device sparse region 120, a fin 130.
Referring to fig. 2, a dummy gate structure 140 is formed on the substrate 100.
The dummy gate structure 140 spans across the fin 130.
Referring to fig. 3, a first trench 111 and a second trench 121 are formed in the fin 130 at both sides of the dummy gate structure 140.
Referring to fig. 4, a first stress layer 112 and a second stress layer 122 are epitaxially grown in the first trench 111 and the second trench 121, respectively.
The inventor researches have found that when the first stress layer 112 is epitaxially grown inside and outside the first trench 111, the first stress layer 112 grows at a high speed, and the first stress layer 112 is formed to have a large volume, because the first stress layer 112 grows on the bottom and the side wall of the first trench 111 at the same time; when the second stress layer 122 is epitaxially grown in the second trench 121, the volume of the second stress layer 122 is smaller, because the second stress layer 122 is grown only at the bottom of the second trench 121 when the second stress layer 122 is epitaxially grown in the second trench 121, the growth speed is slower, the volume of the second stress layer 122 is smaller, the growth speeds of the first stress layer 112 and the second stress layer 122 are unbalanced, so that when the contact hole is subsequently reformed, the contact resistance formed in the device dense region 110 is smaller, the contact resistance formed in the device sparse region 120 is larger, the contact resistance of the device sparse region and the device dense region is unbalanced, and the use performance of the semiconductor device is easily unstable in the use process of the semiconductor device.
The inventor researches and discovers that the volume of the stress layer in the sparse region of the device can be increased by carrying out the growth of the stress layer twice in the groove of the sparse region of the device, and when the contact hole is formed subsequently, the contact area between the contact hole and the source drain can be increased due to the increase of the volume of the stress layer formed in the sparse region of the device, and the contact resistance formed in the sparse region of the device is smaller as the contact area is larger, so that the contact resistance of the sparse region of the device and the dense region of the device can be balanced, and the stability of the performance of the semiconductor device can be improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
First embodiment
Fig. 5 to 12 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention.
Referring first to fig. 5, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
Referring to fig. 6, a fin 300 is formed on the substrate 200.
The method of forming the fin 300 includes: forming a photoresist layer on the substrate 200; after exposure and development processes, forming a photoresist pattern in the photoresist layer; and etching the substrate 200 by taking the patterned photoresist layer as a mask, thereby forming the fin 300 on the substrate 200.
Referring to fig. 7, a dummy gate structure 400 is formed on the substrate 200, the dummy gate structure 400 crossing the fin 300.
In this embodiment, the material of the dummy gate structure 400 is polysilicon; in other embodiments, the material of the dummy gate structure 400 may also be amorphous carbon or silicon nitride.
The method of forming the dummy gate structure 400 includes: forming a gate oxide layer (not shown) on the surface of the substrate 200, forming a gate layer on the gate oxide layer, and forming a patterned layer on the gate layer, wherein the patterned layer covers a corresponding region where the dummy gate structure 400 needs to be formed; and etching the gate electrode layer and the gate oxide layer by taking the patterned layer as a mask until the substrate 200.
The gate oxide layer is made of silicon oxide; the gate oxide layer may be formed in a thermal oxidation process, an atomic deposition process, or a chemical vapor deposition process.
In this embodiment, the gate layer is removed later, and replaced with a gate dielectric layer of a high-K dielectric material and a gate layer of a metal material.
Referring to fig. 8, a first trench 211 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device dense region 210, while a second trench 221 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device sparse region 220.
In this embodiment, the method of forming the first trench 211 and the second trench 221 is dry etching; the parameters of the dry etching include: the etching gas comprises HBr and Ar, wherein the flow rate of the HBr is 10 sccm-1000 sccm, and the flow rate of the Ar is 10 sccm-1000 sccm.
In other embodiments, the method of forming the first trench 211 and the second trench 221 is anisotropic wet etching, and an appropriate etching method is selected according to actual needs.
Referring to fig. 9, a first stress layer 230 is formed in the first trench 211 and in the second trench 221.
In this embodiment, the first stress layer 230 is formed by using an epitaxial growth method; in other embodiments, the method of forming the first stress layer 230 is not limited to epitaxial growth.
In this embodiment, when the semiconductor device is a POMS device, the process condition for forming the first stress layer 230 is to control the temperature to be in the range of 500-800 ℃, the pressure to be in the range of 1-100 torr, and the selected gas includes a mixed gas of silane (SiH 4) and germanide gas (GeH 4), and the gas flow is controlled to be in the range of 70-300 sccm and the time is controlled to be in the range of 3-120 s.
In this embodiment, when the semiconductor device is a NOMS device, the process condition for forming the first stress layer 230 is to control the temperature to be 500-800 ℃, the pressure to be 1-100 torr, the selected gas to include a mixed gas of silane (SiH 4) and phosphine gas (PH 3), and the gas flow to be 70-300 sccm and the time to be 3-120 s.
Referring to fig. 10, sacrificial sidewall spacers 500 are formed on sidewalls of the dummy gate structure 400.
In this embodiment, the sacrificial sidewall 500 covers the first stress layer 230 in the first trench 211.
In this embodiment, the thickness of the sacrificial sidewall 500 in the device dense region is between 15 and 30 nm; when the thickness of the sacrificial sidewall 500 is smaller than 15 nm, the sacrificial sidewall 500 adjacent to the sidewall of the dummy gate structure 400 cannot cover the entire surface of the first stress layer 230 formed in the first trench 211, so that a stress layer is formed again in the first trench 211 when the subsequent epitaxial growth is performed again, thereby increasing the volume of the first stress layer 230; when the subsequent thickness of the sacrificial sidewall 500 is greater than 30 nm, the sacrificial sidewall 500 is formed too thick, resulting in waste of resources.
In this embodiment, the thickness of the sacrificial sidewall 500 formed in the device dense region 210 and the device sparse region 220 is different; in other embodiments, the thickness of the sacrificial sidewall 500 may be the same in the device dense region 210 and the device sparse region 220.
In this embodiment, the material of the sacrificial sidewall 500 is silicon nitride; in other embodiments, the material of the sacrificial sidewall 500 may be one or more of silicon oxide, silicon carbide, silicon carbonitride, organic matters, or metals.
In this embodiment, the purpose of the sacrificial sidewall 500 is to cover the first stress layer 230 formed in the first trench 211, so as to prevent the stress layer from being grown again in the first trench 211 when the epitaxial growth is performed again in the subsequent process.
Referring to fig. 11, a second stress layer 240 is formed on the first stress layer 230 of the second trench 221.
In this embodiment, the second stress layer 240 is formed by epitaxial growth, and the reaction gas includes silane (SiH 4) or a combination gas of silane (SiH 4) and germanide gas (GeH 4) or a combination gas of silane (SiH 4) and phosphine gas (PH 3).
In this embodiment, the second stress layer 240 is formed by an epitaxial growth method, in which the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, the reaction gas is silane (SiH 4), and the reaction time is controlled to be 3-120 s.
In this embodiment, the reaction gas for forming the second stress layer 240 is silane (SiH 4), so as to simplify the process and improve the production efficiency, and this is to use silane (SiH 4) to form the second stress layer 240 without applying stress, and to form the second stress layer 240 in both the device sparse region of the POMS device and the device sparse region of the NOMS device, so that the production process can be simplified and the production efficiency can be improved; while the use of silane (SiH 4) does not affect the pressure at which the POMS device or NOMS device is grown epitaxially.
In this embodiment, the purpose of forming the second stress layer 240 on the first stress layer 230 of the second trench 221 is to increase the volume of the stress layer in the second trench 221 in the device sparse region 220, so that when the contact hole is formed later, the contact area between the contact hole and the source drain is increased, and the contact resistance in the device sparse region 220 is reduced, so that the contact resistance with the device dense region is balanced, and thus, in the process of using the semiconductor device, the stability of using the semiconductor device is not affected because the contact resistances of the device sparse region and the device dense region are too different.
Referring to fig. 12, the sacrificial sidewall 500 is removed.
In this embodiment, the method for removing the sacrificial sidewall 500 may use ashing; in other embodiments, a wet etching process may be used to remove the sacrificial sidewall 500.
A semiconductor device formed by the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 located on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; the first trenches 211 are located in the fin 300 at two sides of the dummy gate structure 400 of the device dense region 210; a second trench 221 located in the fin 300 at two sides of the dummy gate structure 400 of the device sparse region 220; a first stress layer 230 located within the first trench 211 and the second trench 221; a second stress layer 240 is located on the first stress layer 230 in the second trench 221.
Second embodiment
Fig. 13 to 20 are schematic structural views of a semiconductor device forming process in the second embodiment of the present invention.
Referring to fig. 13, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.
Referring to fig. 14, a fin 300 is formed on the substrate 200.
In this embodiment, the step of forming the fin 300 is the same as the method in the first embodiment; in other embodiments, the fin 300 may be formed by a different method.
Referring to fig. 15, a dummy gate structure 400 is formed on the substrate 200, the dummy gate structure 400 crossing the fin 300.
In this embodiment, the method of forming the dummy gate structure 400 is the same as that of the first embodiment; in other embodiments, other methods may be used to form the dummy gate structure 400.
Referring to fig. 16, a first trench 211 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device dense region 210, while a second trench 221 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device sparse region 220.
In this embodiment, the fin 300 is etched by a wet method, and parameters of the wet etching process include: an aqueous solution of HNO 3 and HF, wherein the volume ratio of HNO3, HF and H 2 O is 1:3: (10 to 800) and the temperature is 40 to 90 ℃.
In other embodiments, the method of etching the fin 300 may be set according to actual process requirements.
Referring to fig. 17, sacrificial spacers 500 are formed on sidewalls of the dummy gate structure 400 of the device dense region 210.
In this embodiment, the sacrificial sidewall 500 is used to cover and fill the first trench 211, so as to cover the first trench 211 first, and a stress layer is not formed in the first trench 211 in the subsequent epitaxial growth process.
In this embodiment, the material of the sacrificial sidewall 500 is silicon carbonitride; in other embodiments, the material of the sacrificial sidewall 500 may be one or more of silicon oxide, silicon carbide, silicon nitride, organic matters, or metals.
Referring to fig. 18, a second stress layer 240 is formed within the second trench 221.
In this embodiment, the second stress layer 240 is formed by epitaxial growth, and the reaction gas includes silane (SiH 4) or a combination gas of silane (SiH 4) and germanide gas (GeH 4) or a combination gas of silane (SiH 4) and phosphine gas (PH 3).
In this embodiment, the process temperature, the reaction chamber pressure, and the reaction time for forming the second stress layer 240 are the same as those in the first embodiment; in other embodiments, different process conditions may also be employed.
Referring to fig. 19, the sacrificial sidewall 500 is removed.
In this embodiment, a chemical reagent is used to remove the sacrificial sidewall 500.
Referring to fig. 20, a first stress layer 230 is formed in the first trench 211; a first stress layer 230 is formed on the second stress layer 240.
In this embodiment, the process conditions for forming the first stress layer 230 are the same as those in the first embodiment; in other embodiments, different process conditions may be used to form the first stress layer 230.
A semiconductor device formed by the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 located on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; the first trenches 211 are located in the fin 300 at two sides of the dummy gate structure 400 of the device dense region 210; a second trench 221 located in the fin 300 at two sides of the dummy gate structure 400 of the device sparse region 220; a second stress layer 240 located in the second trench 221; a first stress layer 230 is located within the first trench 211 and on the second stress layer 240.
Third embodiment
Fig. 21 to 30 are schematic structural views of a semiconductor device forming process in a third embodiment of the present invention.
In this embodiment, the device is a POMS device.
Referring to fig. 21, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.
Referring to fig. 22, a fin 300 and an isolation structure 600 are formed on the substrate 200.
In this embodiment, an isolation structure 600 is formed on the substrate 200; in other embodiments, the isolation structure 600 may not be formed on the substrate 200.
In this embodiment, the isolation structure 600 may be a shallow trench isolation structure, but is not limited to a shallow trench isolation structure. The isolation structure 600 is used to isolate devices from each other.
The step of forming the isolation structure 600 includes etching the substrate 200 to form an isolation trench (not shown) in the semiconductor substrate 200; and filling isolation materials into the isolation trenches, and flattening the isolation materials to form the isolation structures 600.
The isolation material may be silicon oxide, and the process of filling the isolation trench with silicon oxide may be a chemical vapor deposition method or a physical vapor deposition method.
Referring to fig. 23, a dummy gate structure 400 is formed on the substrate 200, the dummy gate structure 400 crossing the fin 300.
In this embodiment, the method of forming the dummy gate structure 400 is the same as that of the first embodiment.
Referring to fig. 24, a mask layer 401 is formed on the dummy gate structure 400.
In this embodiment, a mask layer 401 is further formed on the dummy gate structure 400; in other embodiments, the mask layer 401 may not be formed on the dummy gate structure 400.
In this embodiment, the material of the mask layer 401 is silicon carbide; in other embodiments, the mask layer 301 may also be silicon oxide or silicon nitride.
Referring to fig. 25, a sidewall 402 is formed on a sidewall of the dummy gate structure 400.
In this embodiment, after forming the dummy gate structure 400, forming a sidewall 402 on a sidewall of the dummy gate structure 400; in other embodiments, the sidewall 402 may not be formed on the sidewall of the dummy gate structure 400.
The sidewall 402 is used for defining the position of the source-drain doped layer formed later, and the sidewall 302 is used for protecting the sidewall of the dummy gate structure 400, so as to avoid appearance defects of the gate layer formed later and influence the electrical performance of the semiconductor structure.
In this embodiment, the material of the sidewall 402 is silicon oxide; in other embodiments, the material of the sidewall 402 may be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
Referring to fig. 26, a first trench 211 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device dense region 210, while a second trench 221 is formed in the fin 300 on both sides of the dummy gate structure 400 of the device sparse region 220.
Referring to fig. 27, sacrificial spacers 500 are formed on sidewalls of the sidewalls 402 of the device dense region 210.
In this embodiment, the sacrificial sidewall 500 covers the first trench 211.
Referring to fig. 28, a second stress layer 240 is formed in the second trench 221.
In this embodiment, the second stress layer 240 is formed by an epitaxial growth method, and the reaction gas is a combination gas of silane (SiH 4) and germanide gas (GeH 4); wherein the reaction temperature is controlled between 500 ℃ and 800 ℃, the pressure of the chamber is controlled between 1 Torr and 100 Torr, and the reaction time is controlled between 3 s and 120 s.
In this embodiment, the first epitaxial growth is performed in the second trench 221 in the device sparse region 220 to increase the volume of the stress layer in the second trench 221, so that the volume of the stress layer epitaxially grown in the second trench 221 can be balanced with the volume of the stress layer in the first trench 211 during the subsequent second epitaxial growth, and when the contact hole is formed, the contact resistance of the device sparse region 220 can be balanced with the contact resistance of the device dense region 210, thereby improving the stability of the service performance of the semiconductor device.
Referring to fig. 29, the sacrificial sidewall 500 is removed.
In this embodiment, the sacrificial sidewall 500 is removed by ashing.
Referring to fig. 30, a first stress layer 230 is formed in the first trench 211; a first stress layer 230 is formed on the second stress layer 240.
In this embodiment, the second epitaxial growth is performed in the device sparse region 220 to form the first stress layer 230 on the second stress layer 240, so that the volume of the growth of the stress layer in the second trench 221 and the volume of the growth of the stress layer in the first trench 211 are balanced, thereby balancing the contact resistance formed in the device sparse region 220 and the device dense region 210 and improving the performance stability of the semiconductor device.
A semiconductor device formed by the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 located on the substrate 200; an isolation structure 600 located on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; a mask layer 401 located on top of the dummy gate structure 400; a sidewall 402, located on a sidewall of the dummy gate structure 400; the first trenches 211 are located in the fin 300 at two sides of the sidewall 402 of the device dense region 210; a second trench 221 located in the fin 300 at two sides of the dummy gate structure 400 of the device sparse region 220; a second stress layer 240 located in the second trench 221; a first stress layer 230 is located within the first trench 211 and on the second stress layer 240.
Fourth embodiment
The fourth embodiment differs from the third embodiment only in the method of forming the second stress layer 240.
In this embodiment, the device is a NOMS device.
In this embodiment, the second stress layer is formed by an epitaxial growth method, in which the process temperature is 50-800 ℃, the pressure of the reaction chamber is 1-100 torr, the reaction gas includes silane (SiH 4) and phosphine gas (PH 3), and the reaction time is 3-120 s.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
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