CN111816562B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a pseudo gate structure and a hard mask layer positioned on the top of the pseudo gate structure are formed on the substrate; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed by the pseudo gate structure; performing first planarization treatment on the dielectric material layer by taking the highest position at the top of the etching stop layer as a stop position; after the first planarization treatment is carried out, etching treatment is carried out on the etching stop layer and the dielectric material layer, and the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer are removed; and after etching treatment, carrying out second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo gate structure as a stop position, wherein the residual dielectric material layer is used as an interlayer dielectric layer. The embodiment of the invention is beneficial to improving the flatness of the top surface of the interlayer dielectric layer and reducing the probability of damaging the grid structure.

Description

Semiconductor structure and method of forming the same

Technical Field

The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same.

Background technique

With the development of highly integrated semiconductor devices, the gate length of metal oxide semiconductor (MOS) devices is being scaled down to smaller sizes. Correspondingly, the manufacturing process of semiconductor devices is also being continuously improved to meet people's requirements for device performance.

Depending on the type and function of the semiconductor device, the number of wiring layers of the manufactured semiconductor device will be different. Semiconductor devices usually include a device layer located on and within a semiconductor substrate, an interlayer dielectric layer (ILD) located above the device layer, and a wiring structure located within the interlayer dielectric layer for connecting active devices and passive devices within the device layer. The interlayer dielectric layer is usually made of insulating material to prevent short circuits between active devices or passive devices and the wires that constitute the wiring structure.

Summary of the invention

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a dummy gate structure being formed on the substrate, and a hard mask layer being formed on the top of the dummy gate structure; forming an etch stop layer conformally covering the top and sidewalls of the hard mask layer, the sidewalls of the dummy gate structure, and the substrate exposed by the dummy gate structure; forming a dielectric material layer on the substrate exposed by the dummy gate structure, the dielectric material layer covering the etch stop layer on the hard mask layer; performing a first planarization process on the dielectric material layer with the highest point of the top of the etch stop layer as a stop position; after performing the first planarization process, performing an etching process on the etch stop layer and the dielectric material layer to remove the etch stop layer and the dielectric material layer above the top of the hard mask layer; after performing the etching process, performing a second planarization process on the dielectric material layer and the hard mask layer with the top of the dummy gate structure as a stop position, and the remaining dielectric material layer serves as an interlayer dielectric layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a semiconductor structure formed by the above-mentioned formation method.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

In the embodiment of the present invention, the highest point on the top of the etching stop layer is used as the stop position, and the dielectric material layer is subjected to the first planarization treatment. Therefore, in the step of the first planarization treatment, only the dielectric material layer is subjected to the first planarization treatment, and other film layer structures are not contacted, which is conducive to preventing the problem of different grinding amounts caused by different pattern densities in different regions or different top surface heights of different film layer structures, and reduces the probability of the problem of dishing at the top of the dielectric material layer, so that the height consistency of the top of the dielectric material layer after the first planarization treatment is better, and at the same time, the thickness of the dielectric material layer to be removed in the subsequent etching treatment can be reduced, so that the process time required for the etching treatment is shorter, and by adopting an anisotropic etching process, it is easy to remove different materials. Removing in the same step at a similar etching rate is beneficial to reducing the difference in the etching amount of the dielectric material layer in different pattern density areas by the etching process. Therefore, after completing the etching process, the height consistency of the top of the remaining dielectric material layer is also good, and it is also beneficial to reduce the probability of the etch stop layer on the side wall of the pseudo gate structure being lost due to the difference in the etching amount of the dielectric material layer, thereby ensuring the protective effect of the etch stop layer on the side wall of the formed gate structure in the subsequent process flow and preventing the side wall of the gate structure from being lost. In summary, the embodiment of the present invention, combined with the first planarization process and the etching process, can reduce the probability of damage to the gate structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 7 are schematic structural diagrams corresponding to various steps in a method for forming a semiconductor structure;

FIG8 is an electron microscope scanning image of a semiconductor structure;

9 to 19 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

In the semiconductor field, the steps of forming an interlayer dielectric layer generally include: forming a dielectric material layer on the substrate where the pseudo gate structure is exposed, wherein the dielectric material layer covers the top of the pseudo gate structure; flattening the top of the dielectric material layer, and the remaining dielectric material layer is used as an interlayer dielectric layer, wherein the interlayer dielectric layer exposes the top of the pseudo gate structure.

In the semiconductor field, according to the design requirements of the integrated circuit, the graphic density of different areas on the substrate is usually different. For example, the substrate usually includes a graphic-dense area and a graphic-sparse area. Compared with the graphic-dense area, the number of pseudo-gate structures on the graphic-sparse area is smaller, the distance between adjacent pseudo-gate structures is farther, and the opening size surrounded by adjacent pseudo-gate structures and the substrate is larger.

Due to the load effect, the larger the size of the opening, the faster the flattening rate, and the more the amount removed in the same time. Therefore, in the step of flattening the top of the dielectric material layer in the formation method, the flattening rate of the dielectric material layer in the sparse pattern area is faster, which easily leads to poor height consistency of the top surface of the interlayer dielectric layer, and the probability of the top surface of the interlayer dielectric layer being concave is higher.

In order to solve the above problems, a method for forming a semiconductor structure is currently proposed. Referring to FIG. 1 to FIG. 7 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to Figure 1, a substrate 1 is provided, on which a dummy gate structure 2 is formed, a hard mask layer 3 is formed on the top of the dummy gate structure 2, and a first etch stop layer 4 is also formed on the substrate 1 to conformally cover the top and sidewalls of the hard mask layer 3, the sidewalls of the dummy gate structure 2, and the exposed portion of the substrate 1 by the dummy gate structure 2.

2 , a bottom dielectric material layer 5 is formed on the substrate 1 where the dummy gate structure 2 is exposed, and the bottom dielectric material layer 5 covers the first etch stop layer 4 located on the hard mask layer 3 .

3 , a portion of the bottom dielectric material layer 5 is etched, and the remaining bottom dielectric material layer 5 exposes a portion of the sidewall of the dummy gate structure 2 .

4 , a second etch stop layer 6 is formed to conformally cover the dummy gate structure 2 exposed from the remaining bottom dielectric material layer 5 and the remaining bottom dielectric material layer 5 .

5 and 6 , a top dielectric material layer 7 is formed on the second etch stop layer 6 ; the top of the second etch stop layer 6 on the dummy gate structure 2 is used as a stop position, and the top dielectric material layer 7 is planarized.

Referring to Figure 7, after planarizing the top dielectric material layer 7, the top of the hard mask layer 3 is used as the stopping position to grind away the top dielectric material layer 7, the second etch stop layer 6 and the first etch stop layer 4 that are higher than the hard mask layer 3, and the remaining top dielectric material layer 7, the second etch stop layer 6 and the bottom dielectric material layer 5 located between the adjacent pseudo gate structures 2 are used as an interlayer dielectric layer (not marked).

In the formation method, by forming a second etch stop layer 6 on the remaining bottom dielectric material layer 5, the second etch stop layer 6 can define the position of the flattening treatment in the subsequent step of flattening the top dielectric material layer 7, which is conducive to reducing the problem of difference in flattening treatment rate caused by different graphic densities in different regions, thereby improving the flatness and height consistency of the top of the interlayer dielectric layer.

However, in the step of etching a partial thickness of the bottom dielectric material layer 5, the formation method is prone to cause loss of the first etch stop layer 4 located on the side wall of the pseudo gate structure 2, making it difficult to ensure the protective effect of the first etch stop layer 4 on the subsequently formed gate structure in the subsequent process flow. The probability of damage to the gate structure is high, and the performance of the formed semiconductor structure is poor.

Referring to FIG. 8 , an electron microscope scan of a semiconductor structure is shown. As can be seen from the figure, the first etch stop layer 4 is greatly damaged and it is difficult to protect the sidewall of the gate structure, so the semiconductor structure formed is poor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a dummy gate structure being formed on the substrate, and a hard mask layer being formed on the top of the dummy gate structure; forming an etch stop layer conformally covering the top and sidewalls of the hard mask layer, the sidewalls of the dummy gate structure, and the substrate exposed by the dummy gate structure; forming a dielectric material layer on the substrate exposed by the dummy gate structure, the dielectric material layer covering the etch stop layer on the hard mask layer; performing a first planarization process on the dielectric material layer with the highest point of the top of the etch stop layer as the stop position; after performing the first planarization process, performing an etching process on the etch stop layer and the dielectric material layer to remove the etch stop layer and the dielectric material layer above the top of the hard mask layer; after performing the etching process, performing a second planarization process on the dielectric material layer and the hard mask layer with the top of the dummy gate structure as the stop position, and the remaining dielectric material layer serves as an interlayer dielectric layer.

In the embodiment of the present invention, the highest point on the top of the etching stop layer is used as the stop position to perform the first planarization process on the dielectric material layer. Therefore, in the step of the first planarization process, only the dielectric material layer is subjected to the first planarization process without contacting other film layer structures, which is conducive to preventing the problem of different grinding amounts caused by different pattern densities in different regions or different top surface heights of different film layer structures, and reduces the probability of the top of the dielectric material layer being sunken, so that the height consistency of the top of the dielectric material layer after the first planarization process is better, and at the same time, the thickness of the dielectric material layer to be removed in the subsequent etching process can be reduced, so that the process time required for the etching process is shorter, and by adopting an anisotropic etching process, it is easy to separate different materials at similar heights. The etching rate is removed in the same step, which is beneficial to reducing the difference in the etching amount of the dielectric material layer in different pattern density areas by the etching process. Therefore, after completing the etching process, the height consistency of the top of the remaining dielectric material layer is also good, and it is also beneficial to reduce the probability of the etch stop layer on the side wall of the pseudo gate structure being lost due to the difference in the etching amount of the dielectric material layer, thereby ensuring the protective effect of the etch stop layer on the formed gate structure side wall in the subsequent process flow and preventing the gate structure side wall from being lost; in summary, the embodiment of the present invention, combined with the first planarization process and the etching process, can reduce the probability of damage to the gate structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.

In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

9 to 19 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention.

9 , a substrate 100 is provided, a dummy gate structure 101 is formed on the substrate 100 , and a hard mask layer 102 is formed on the top of the dummy gate structure 101 .

The substrate 100 is used to provide a process platform for subsequently forming a semiconductor structure.

In this embodiment, the substrate 100 is used to form a planar transistor, and the substrate 100 accordingly only includes a substrate (not shown). In other embodiments, when the substrate is used to form a fin field effect transistor, the substrate accordingly includes a substrate and a fin protruding from the substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

The dummy gate structure 101 is used to occupy a space for the subsequent formation of a gate structure.

In this embodiment, the dummy gate structure 101 is a polysilicon gate structure, and the dummy gate structure 101 accordingly includes a dummy gate oxide layer 1011 located on the substrate 100 , and a dummy gate layer 1012 located on the dummy gate oxide layer 1011 .

The material of the dummy gate layer 1012 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, carbon silicon oxynitride or amorphous carbon. The material of the dummy gate oxide layer 1011 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer 1012 is polysilicon. The material of the dummy gate oxide layer 1011 is silicon oxide.

In other embodiments, the dummy gate structure may also include only a dummy gate layer.

In this embodiment, a sidewall 103 is formed on the sidewall of the dummy gate structure 101. The sidewall 103 is used to protect the sidewall of the dummy gate structure 101, and is also used to define a formation region of a source-drain doping layer.

The material of the spacer 103 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride.

The sidewall 103 may be a single-layer structure or a laminated structure. In this embodiment, the sidewall 103 is a laminated structure.

Specifically, the sidewall spacer 103 is an ONO (Oxide Nitride Oxide, oxide-silicon nitride-oxide) structure, and the sidewall spacer 103 includes a first sidewall spacer (not shown) located on the sidewall of the pseudo gate structure 101, a second sidewall spacer (not shown) located on the sidewall of the first sidewall spacer, and a third sidewall spacer (not shown) located on the sidewall of the second sidewall spacer. Accordingly, the material of the first sidewall spacer is silicon oxide, the material of the second sidewall spacer is silicon nitride, and the material of the third sidewall spacer is silicon oxide.

It should be noted that, in the design of integrated circuits, different film layer structures will be formed on the side walls and top surfaces of the pseudo gate structures 101 of different devices according to the design requirements. For example: In this embodiment, the substrate 100 includes an NMOS device region (not marked) and a PMOS device region (not marked), and the top surface and side walls of the pseudo gate structure 101 on the substrate at the junction of the NMOS device region and the PMOS device region are also formed with a low dielectric constant layer 1051, and an N/P boundary layer 1052 located on the top surface and side walls of the low dielectric constant layer 1051. Among them, the low dielectric constant layer 1051 is used to reduce the leakage current of the device, and the N/P boundary layer 1052 is used to define the boundary between the NMOS device region and the PMOS device region.

The hard mask layer 102 is used as an etching mask for forming the dummy gate structure 101 . The hard mask layer 102 is also used to protect the top of the dummy gate structure 101 in subsequent process steps.

The subsequent process also includes: forming an etch stop layer that conformally covers the top and side walls of the hard mask layer 102, the side walls of the dummy gate structure 101, and the substrate 100 exposed by the dummy gate structure 101; forming a dielectric material layer on the substrate 100 exposed by the dummy gate structure 101, the dielectric material layer covering the etch stop layer on the hard mask layer 102; taking the highest point of the top of the etch stop layer as the stop position, performing a first planarization treatment on the dielectric material layer; after performing the first planarization treatment, etching the etch stop layer and the dielectric material layer using an anisotropic etching process to remove the etch stop layer and the dielectric material layer that are higher than the top of the hard mask layer 102.

The hard mask layer 102 is used to define an etching stop position in the subsequent step of etching the etching stop layer and the dielectric material layer.

In this embodiment, the hard mask layer 102 includes a bottom hard mask layer 1021 and a top hard mask layer 1022 located on the bottom hard mask layer 1021 . The material of the bottom hard mask layer 1021 is silicon nitride, and the material of the top hard mask layer 1022 is silicon oxide.

In the subsequent step of etching the etch stop layer and the dielectric material layer 107, the top surface of the top hard mask layer 1022 is used to define the etching stop position. The material of the top hard mask layer 1022 is silicon oxide, which has good adhesion to other material layers, facilitating the formation of subsequent film layers.

The subsequent step also includes a step of performing a third planarization process, wherein the bottom hard mask layer 1021 is used to define a stop position of the third planarization process, thereby improving the flatness of the top surface of the material layer to be ground after the third planarization process. The material of the bottom hard mask layer 1021 is silicon nitride, which has high density and hardness, and plays a significant role in defining the stop position of the third planarization process.

In this embodiment, source-drain doping layers 104 are further formed in the substrate 100 on both sides of the dummy gate structure 101. Specifically, the source-drain doping layers 104 are located in the substrate 100 on both sides of the dummy gate structure 101.

When an NMOS transistor is formed, the source-drain doping layer 104 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress for the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doping layer 104 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

10 , an etch stop layer 106 is formed to conformally cover the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the substrate 100 exposed by the dummy gate structure 101. Specifically, the etch stop layer 106 conformally covers the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the source-drain doping layer 104.

The etch stop layer 106 is a contact hole etch barrier layer (Contact Etch Stop Layer, CESL). The etch stop layer 106 located on the top surface of the source-drain doped layer 104 is used to define the etching stop position in the subsequent contact hole etching process, which is beneficial to reduce the damage of the contact hole etching process to the source-drain doped layer 104; the etch stop layer 106 located on the side wall of the dummy gate structure 101 is used to protect the dummy gate structure 101 in the subsequent process. After the gate structure is formed at the dummy gate structure 101, the etch stop layer 106 is also used to protect the gate structure in the subsequent process.

In this embodiment, the material of the etch stop layer 106 is silicon nitride. Silicon nitride has a high density and hardness, thereby ensuring that the etch stop layer 106 can play a role in defining the etching stop position and a corresponding protective role.

In this embodiment, an atomic layer deposition (ALD) process is used to form the etch stop layer 106. The ALD process has good step coverage capability, which is conducive to making the etch stop layer 106 conformally cover the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the substrate 100 exposed by the dummy gate structure 101; moreover, the ALD process includes performing multiple ALD cycles to form a thin film of a desired thickness, which is conducive to improving the thickness uniformity and density of the etch stop layer 106.

It should be noted that, in this embodiment, the top surface and sidewalls of the dummy gate structure 101 at the junction of the first device region and the second device region are formed with a low dielectric constant layer 1051, and an N/P boundary layer 1052 located on the top surface and sidewalls of the low dielectric constant layer 1051. Therefore, in the step of forming the etch stop layer 106, the etch stop layer 106 also conformally covers the N/P boundary layer 1052. After the etch stop layer 106 is formed, the top surface of the etch stop layer 106 has different heights.

11 , a dielectric material layer 107 is formed on the substrate 100 where the dummy gate structure 101 is exposed. The dielectric material layer 107 covers the etch stop layer 106 located on the hard mask layer 102 .

The dielectric material layer 107 is used to subsequently form an interlayer dielectric layer, thereby achieving isolation between adjacent devices.

Therefore, the material of the dielectric material layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the dielectric material layer 107 is a single-layer structure, and the material of the dielectric material layer 107 is silicon oxide.

In this embodiment, a flowable chemical vapor deposition (FCVD) process is used to form the dielectric material layer 107. The flowable chemical vapor deposition process has good filling ability and is suitable for filling openings with high aspect ratios, which is beneficial to reducing the probability of defects such as voids being formed in the dielectric material layer 107, and correspondingly is beneficial to improving the film quality of the subsequent interlayer dielectric layer.

12 , the dielectric material layer 107 is subjected to a first planarization process with the highest point on the top of the etch stop layer 106 being the stop position.

It should be noted that the top surface of the etch stop layer 106 has different heights. The highest point on the top of the etch stop layer 106 refers to the farthest distance from the top surface of the etch stop layer 106 to the surface of the substrate 100 in a direction perpendicular to the surface of the substrate 100 .

By taking the highest point of the top of the etching stop layer 106 as the stop position, the dielectric material layer 107 is subjected to the first planarization treatment. Therefore, in the step of the first planarization treatment, only the dielectric material layer 107 is subjected to the first planarization treatment, and other film layer structures are not contacted. This is beneficial to preventing the problem of different grinding amounts caused by different graphic densities in different regions or different top surface heights of each film layer structure, and reduces the probability of a depression problem occurring at the top of the remaining dielectric material layer 107. This makes the height consistency of the top of the dielectric material layer 107 after the first planarization treatment better, which is correspondingly beneficial to improving the height consistency of the top of the subsequent interlayer dielectric layer.

Moreover, the subsequent step also includes etching the etch stop layer 106 and the dielectric material layer 107 to remove the etch stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102. Compared with the solution of not performing the first planarization treatment and directly etching the dielectric material layer, the first planarization treatment reduces the thickness of the dielectric material layer 107 to be removed in the subsequent etching treatment, so that the process time required for the etching treatment is shorter, which is beneficial to reducing the difference in the etching amount of the dielectric material layer 107 in different pattern density areas by the etching treatment. This is not only beneficial to improving the height consistency of the top of the subsequent interlayer dielectric layer, but also beneficial to reducing the probability of the etch stop layer 106 on the side wall of the pseudo gate structure 101 being lost due to the difference in the etching amount of the dielectric material layer 107, thereby ensuring the protective effect of the etch stop layer 106 on the side wall of the formed gate structure 101 in the subsequent process, preventing the side wall of the gate structure 101 from being lost, and improving the performance of the semiconductor structure.

In this embodiment, a low dielectric constant layer 1051 is formed on the top surface and side wall of the pseudo gate structure 101 at the junction of the first device area and the second device area, and an N/P boundary layer 1052 is located on the top surface and side wall of the low dielectric constant layer 1051. Therefore, the highest point of the top of the etch stop layer 106 refers to the top of the etch stop layer 106 located on the top of the N/P boundary layer 1052.

In this embodiment, the first planarization process is performed by a chemical-mechanical polishing (CMP) process. By adopting the chemical-mechanical polishing process, it is helpful to accurately locate the highest point on the top of the etch stop layer 106, thereby accurately controlling the stop position of the first planarization process, reducing the process difficulty of the first planarization process, and further helping to further improve the flatness of the top surface of the dielectric material layer 107 after the first planarization process.

Specifically, during the process of performing the first planarization process by using the chemical mechanical polishing process, an endpoint detection (EPD) method is adopted, with the highest point on the top of the etch stop layer 106 being used as the polishing stop position.

In other embodiments, the first planarization process may further include sequentially performing an etchback process and a chemical mechanical polishing process.

13 , after the first planarization process is performed, the etch stop layer 106 and the dielectric material layer 107 are etched to remove the etch stop layer 106 and the dielectric material layer 107 that are higher than the top of the hard mask layer 102 .

By adopting the etching treatment method, it is easy to remove different materials at a similar etching rate in the same step, which is beneficial to reducing the difference in the etching amount of the dielectric material layer 107 in different pattern density areas caused by the etching treatment. Therefore, after completing the etching treatment, the height consistency of the top of the remaining dielectric material layer 107 is also good, and it is also beneficial to reduce the probability of the etch stop layer 106 on the side wall of the pseudo gate structure 101 being lost due to the difference in the etching amount of the dielectric material layer 107, thereby ensuring the protective effect of the etch stop layer 106 on the side wall of the formed gate structure in the subsequent process and preventing the side wall of the gate structure from being lost.

In this embodiment, the etch stop layer 106 and the dielectric material layer 107 above the top of the top hard mask layer 1022 are removed. The top hard mask layer 1022 is used to define an etching stop position in the step of etching the etch stop layer 106 and the dielectric material layer 107, thereby improving the height consistency of the top of the dielectric material layer 107 after the etching process.

Moreover, the material of the top hard mask layer 1022 is silicon oxide, and the adhesion between the silicon oxide layer and other film layers is high, which facilitates the subsequent formation of other film layers on the top hard mask layer 1022 and the dielectric material layer 107, and is correspondingly beneficial to improving the quality of the subsequently formed film layers.

In this embodiment, the Siconi process is used for the etching process. As a low-intensity and high-precision chemical etching method, the Siconi process generally includes the following steps: first, generating etching gas; etching the material layer to be etched by the etching gas to form by-products; performing an annealing process to sublimate and decompose the by-products into gaseous products; and removing the gaseous products by exhausting.

In this embodiment, the etching _gas of the _Siconi process includes _CxFy gas and _{CxHyFz gas} .

The use of the Siconi process makes it easy to make the etching rates of the silicon nitride material and the silicon oxide material of the etching process closer, so that the etching stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102 can be removed in the same step. Moreover, the use of the Siconi process is also beneficial to improving the etching load effect of the etching process, thereby further improving the height consistency of the top surface of the dielectric material layer 107 after the etching process; in addition, the Siconi process is easy to obtain a higher etching selectivity, which is beneficial to reduce the probability of damage to other film layer structures during the etching process.

In other embodiments, according to actual process requirements, a dry etching process may also be used to perform the etching process.

The bias voltage of the Siconi process should not be too small or too large. If the bias voltage is too small, it is easy to reduce the plasma concentration of the etching process, thereby reducing the etching rate; if the bias voltage is too large, it is easy to reduce the uniformity of the etching rate, thereby reducing the height consistency of the top surface of the dielectric material layer 107 after the etching process. For this reason, in this embodiment, the bias voltage of the Siconi process is 15 volts to 25 volts.

In this embodiment, in the step of performing the etching treatment, by reasonably setting the process parameters of the etching treatment, after the etching treatment, the height difference of the top surface of the dielectric material layer 107 in each area is less than 10nm, thereby improving the height consistency of the top surface of the dielectric material layer 107.

In this embodiment, in the step of removing the etch stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102 , the N/P boundary layer 1052 and the low dielectric constant layer 1051 above the top of the hard mask layer 102 are also removed.

In this embodiment, after the etching process is performed, the process further includes:

Referring to Figure 14, a cross-sectional view of the semiconductor structure along the extension direction of the pseudo gate structure 101 is shown. In this embodiment, after the etching process is performed, it also includes: cutting off the pseudo gate structure 101 through an etching process, forming an opening 200 in the dielectric material layer 107 to expose the substrate 100, and the opening 200 is distributed in the extension direction of the pseudo gate structure 101.

By cutting off the dummy gate structure 101 , unnecessary dummy gate structures 101 are removed, so that the layout of the dummy gate structure 101 meets the design requirements of the integrated circuit.

In this embodiment, the step of forming the opening 200 includes: forming a mask pattern layer 108 on the hard mask layer 102; using the mask pattern layer 108 as a mask, adopting a dry etching process to cut off the pseudo gate structure 101, and forming an opening 200 in the dielectric material layer 107 to expose the substrate 100.

In this embodiment, the material of the mask pattern layer 108 is silicon oxide. The mask pattern layer 108 is formed on the top hard mask layer 1022. The mask pattern layer 108 has good adhesion to the top hard mask layer 1022, which is beneficial to improving the process effect of pattern transfer.

The dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the accuracy of pattern transfer and making the cross section of the opening 200 meet the process requirements.

15 to 17 , an isolation material layer 111 is formed to fill the opening 200 (as shown in FIG. 17 ). The isolation material layer 111 also covers the dielectric material layer 107 and the hard mask layer 102 .

By filling the opening 200 with an isolation material layer 111, the remaining pseudo gate structures 101 are isolated from each other in the extension direction of the pseudo gate structure 101. After a gate structure is subsequently formed at the position of the pseudo gate structure 101, the isolation material layer 111 located in the opening 200 can also electrically isolate the gate structures on both sides of the opening 200.

Therefore, the material of the isolation material layer 111 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the isolation material layer 111 is a single-layer structure, and the material of the isolation material layer 111 is silicon oxide.

In this embodiment, the isolation material layer 111 is formed by a flowable chemical vapor deposition process, which is beneficial to reducing the probability of defects such as voids being formed in the isolation material layer 111 .

Specifically, the isolation material layer 111 covers the mask pattern layer 108 .

It should be noted that, in conjunction with reference to FIGS. 15 and 16 , in this embodiment, after forming the opening 200 and before forming the isolation material layer 111 , the process further includes: forming a protection layer 110 on the sidewall of the opening 200 .

After the dielectric material layer 107 above the top of the dummy gate structure 101 is subsequently removed to form an interlayer dielectric layer, the method further includes: removing the dummy gate structure 101, forming a gate opening in the dielectric material layer 107; and forming a gate structure in the gate opening. The protective layer 110 is used to protect the isolation material layer 111 located in the opening 200 during the step of forming the gate opening, thereby reducing the probability of damage to the isolation material layer 111 located in the opening 200.

In this embodiment, the material of the protection layer 110 is silicon nitride. Silicon nitride has high density and hardness, which is conducive to ensuring the protection effect of the protection layer 110 on the isolation material layer 111.

Specifically, the step of forming the protective layer 110 includes: forming a protective material layer 109 that conformally covers the bottom and side walls of the opening 200, and the top of the hard mask layer 102 and the dielectric material layer 107 (as shown in Figure 15); using an anisotropic etching process to remove the protective material layer 109 located at the top of the hard mask layer 102 and the dielectric material layer 107, and the bottom of the opening 200, and retaining the remaining protective material layer 109 on the side walls of the opening 200 as the protective layer 110.

By making the protective material layer 109 conformally cover the bottom and side walls of the opening 200, as well as the top of the hard mask layer 102 and the dielectric material layer 107, a maskless etching process can be subsequently used to remove the protective material layer 109 located at the top of the hard mask layer 102 and the dielectric material layer 107, as well as the bottom of the opening 200, so that the process of forming the protective layer 110 does not require a photomask, which is beneficial to reducing process costs.

In this embodiment, the protection material layer 109 is formed by an atomic layer deposition process. The use of the atomic layer deposition process is conducive to improving the conformal coverage of the protection material layer 109, so that it can be formed on the sidewall of the opening 200. Moreover, the atomic layer deposition process is also conducive to improving the thickness uniformity and density of the protection material layer 109, thereby ensuring the protection of the protection material layer 109 on the isolation material layer 111 located in the opening 200.

The anisotropic etching process in this embodiment is a dry etching process, which is easy to implement anisotropic etching, and is beneficial to reducing damage to the protective material layer 109 located on the side wall of the opening 200, so that the protective layer 110 can play a corresponding protective effect.

18 , with the top of the hard mask layer 102 as a stop position, a third planarization process is performed on the isolation material layer 111 and the dielectric material layer 107 .

In this embodiment, the materials of the isolation material layer 111 and the bottom hard mask layer 1021 are different. Therefore, in the step of the third planarization treatment, the bottom hard mask layer 1021 is used as the stopping position, which is beneficial to improve the top height consistency of the isolation material layer 111 after the third planarization treatment.

In this embodiment, the third planarization process is performed by using a chemical mechanical polishing process.

Specifically, an endpoint detection (EPD) method is adopted, with the highest point on the top of the bottom hard mask layer 1021 being used as the grinding stop position.

19 , after the etching process, the dielectric material layer 107 and the hard mask layer 102 are subjected to a second planarization process with the top of the dummy gate structure 101 as a stop position, and the remaining dielectric material layer 107 serves as an interlayer dielectric layer 120 .

From the above, it can be seen that the top height consistency of the dielectric material layer 107 after the first planarization treatment and the etching treatment is good. Therefore, in the step of the second planarization treatment, the uniformity of the grinding rate is good. After the interlayer dielectric layer 120 is formed, the top height consistency of the interlayer dielectric layer 120 is improved.

Moreover, the grinding rate uniformity of the second planarization treatment is good, which is also beneficial to reducing the probability of damage to the etch stop layer 106 on the side wall of the pseudo gate structure 101 during the second planarization treatment step. Therefore, after a gate structure is subsequently formed at the position of the pseudo gate structure 101, the etch stop layer 106 can play a corresponding protective effect on the gate structure in subsequent process steps, thereby reducing the probability of damage to the side wall of the gate structure and improving the performance of the semiconductor structure.

In this embodiment, the second planarization process is performed by chemical mechanical polishing, which is conducive to accurately positioning the stop position of the second planarization process, reducing the process difficulty of the second planarization process, and further improving the flatness of the top surface of the interlayer dielectric layer 120 .

Specifically, during the process of performing the second planarization process by using the chemical mechanical polishing process, an endpoint detection method is adopted, with the top of the dummy gate structure 101 being used as the polishing stop position.

In the present embodiment, an isolation material layer 111 (as shown in FIG. 18 ) is also formed on the substrate 100 and is located in the opening 200 (as shown in FIG. 18 ), and the top of the isolation material layer 111 is higher than the top of the pseudo gate structure 101. Therefore, in the step of performing the second planarization treatment, the isolation material layer 111 is also subjected to the second planarization treatment, and the remaining isolation material layer 111 after the second planarization treatment is used as an isolation structure (not shown).

After a gate structure is subsequently formed at the position of the dummy gate structure 101 , the isolation structure is used to achieve electrical isolation between adjacent gate structures along the extension direction of the gate structure.

Correspondingly, the present invention also provides a semiconductor structure formed by the above method.

As can be seen from the foregoing, the top height consistency of the interlayer dielectric layer formed by the foregoing method is good, and the etch stop layer located on the dummy gate structure is less damaged, which is conducive to ensuring the protective effect of the etch stop layer on the subsequent gate structure sidewall, thereby reducing the probability of the gate structure sidewall being damaged in the subsequent process. In summary, the performance of the semiconductor structure formed by the foregoing method is improved.

The semiconductor structure can be formed by the formation method described in the above embodiment. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a plurality of dummy gate structures are formed on the substrate, hard mask layers are formed on the tops of the dummy gate structures, and the heights of the highest parts of the hard mask layers on the tops of different dummy gate structures are the same;

forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure;

Forming a dielectric material layer on the substrate exposed by the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer;

Taking the highest position at the top of the etching stop layer as a stop position, and carrying out first planarization treatment on the dielectric material layer;

After the first planarization treatment is carried out, taking the highest position of the hard mask layer as a stop position, carrying out etching treatment on the etching stop layer and the dielectric material layer, and removing the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer;

after the etching treatment, forming an isolation material layer covering the top of the dielectric material layer;

taking the highest position at the top of the hard mask layer as a stop position, and carrying out third planarization treatment on the isolation material layer and the dielectric material layer;

And after the third planarization treatment, taking the top of the pseudo gate structure as a stop position, carrying out second planarization treatment on the dielectric material layer and the hard mask layer, and taking the rest of the dielectric material layer as an interlayer dielectric layer.

2. The method of claim 1, wherein the first planarization process is performed using a chemical mechanical polishing process.

3. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a dry etching process.

4. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a sicoi process.

5. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed with a difference in height of the top surface of the dielectric material layer in each region of less than 10 nm.

6. The method of claim 1, wherein the second planarization process is performed using a chemical mechanical polishing process.

7. The method of forming a semiconductor structure of claim 1, wherein after performing the etching process, before performing the second planarization process, further comprising:

Cutting off the pseudo gate structure through an etching process, and forming openings exposing the substrate in the dielectric material layer, wherein the openings are distributed in the extending direction of the pseudo gate structure;

The forming of the isolation material layer covering the top of the dielectric material layer includes:

Forming an isolation material layer filled in the opening, wherein the isolation material layer also covers the dielectric material layer and the hard mask layer;

and in the step of carrying out the second planarization treatment, carrying out the second planarization treatment on the isolation material layer, wherein the remaining isolation material layer after the second planarization treatment is used as an isolation structure.

8. The method of claim 7, wherein the hard mask layer comprises a bottom hard mask layer and a top hard mask layer on the bottom hard mask layer, the bottom hard mask layer being made of silicon nitride and the top hard mask layer being made of silicon oxide;

Removing the etching stop layer and the dielectric material layer which are higher than the top of the top hard mask layer in the step of etching the etching stop layer and the dielectric material layer;

in the third planarization step, the bottom hard mask layer is used as a stop position.

9. The method of claim 7, wherein the third planarization process is performed using a chemical mechanical polishing process.

10. The method of forming a semiconductor structure of claim 7, wherein after forming the opening, prior to forming the isolation material layer, further comprising:

A protective layer is formed on the sidewalls of the opening.

11. The method of forming a semiconductor structure of claim 10, wherein in the step of forming the protective layer, the material of the protective layer is silicon nitride.

12. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises an atomic layer deposition process.

13. The method of forming a semiconductor structure of claim 10, wherein the step of forming the protective layer comprises: forming a protective material layer which conformally covers the bottom and the side wall of the opening and the tops of the hard mask layer and the dielectric material layer;

And removing the protective material layer positioned at the top of the hard mask layer and the dielectric material layer and at the bottom of the opening by adopting an anisotropic etching process, and reserving the rest protective material layer on the side wall of the opening as the protective layer.

14. A semiconductor structure formed by the method of any of claims 1-13.