CN111816556A - Transistor and preparation method - Google Patents

Abstract

The application relates to the technical field of semiconductors, in particular to a preparation method of a transistor, which comprises the following steps: providing a semiconductor substrate; forming a trench on a semiconductor substrate; forming a gate oxide layer on the surface of the groove by using an atomic layer deposition process; filling a gate electrode layer in the groove; wherein, the silicon precursor used by the atomic layer deposition process does not contain Cl element. According to the method, the Br or I series silicon precursor with weaker bonding force than Cl or C and N series silicon precursors which are easy to decompose at low temperature are used for forming the gate oxide layer, the Br or I series silicon precursor does not contain Cl and has weaker bonding force, so that the Br or I series silicon precursor can be easily decomposed, and in addition, the C and N series silicon precursors are easy to decompose at low temperature, so that impurities in the gate oxide layer are greatly reduced. The method improves the thermalization of the gate oxide layer caused by the accumulation effect of the silicon semiconductor substrate and the gate oxide interface, and solves the problem of electric leakage of the gate oxide layer.

Description

Transistor and preparation method

technical field

The present application relates to the technical field of semiconductors, and in particular, to a transistor and a preparation method thereof.

Background technique

Dynamic Random Access Memory (DRAM for short) is a semiconductor memory device commonly used in computers. It consists of many repeated DRAM memory cells. Each DRAM memory cell includes a single capacitor (Capacitor) and a single capacitor coupled in series with it. transistor. The gate oxide layer (GateOxide, GOX) of the existing DRAM memory cell is HCDS (Si ₂ Cl ₆ ) and H ₂ /O ₂ through thermal atomic layer deposition (thermal ALD), annealing process (In -situ steam generation, ISSG) method to oxidation (oxidation) formed. However, the Cl atoms from the HCDS of the silicon precursor (Si precursor) will produce a pile-up at the interface between the silicon semiconductor substrate (Si sub) and the gate oxide layer (GOX), forming a negative fixed current of Cl ions. (Cl-related negative fixed charge), so that the threshold voltage (Cell Vth) of the memory cell increases. Causes the problem of gate oxide leakage (Goxleakage).

SUMMARY OF THE INVENTION

The present application solves the above-mentioned technical problems in the related art at least to a certain extent. To this end, the present application proposes a transistor and a manufacturing method, which reduces impurities in the gate oxide layer, improves the stacking effect at the interface between the silicon semiconductor substrate and the gate oxide layer, and solves the problem of gate oxide layer leakage.

In order to achieve the above purpose, a first aspect of the present application provides a method for preparing a transistor, comprising the following steps:

provide semiconductor substrates;

forming trenches in a semiconductor substrate;

A gate oxide layer is formed on the surface of the trench using an atomic layer deposition process;

filling the gate electrode layer in the trench;

Wherein, the silicon precursor used in the atomic layer deposition process does not contain Cl element.

A second aspect of the present application provides a transistor, comprising:

semiconductor substrate;

forming a trench in the semiconductor substrate;

a gate oxide layer, the gate oxide layer is formed on the surface of the trench;

a gate electrode layer, the gate electrode layer is filled in the trench;

The gate oxide layer does not contain Cl impurities.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for purposes of illustrating preferred embodiments only and are not to be considered limiting of the application. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

1 is a cross-sectional view of a semiconductor substrate after forming trenches according to some embodiments of the present application;

2 is a cross-sectional view after forming a gate oxide layer and a gate electrode layer in the trench of FIG. 1;

Fig. 3 is a partial schematic view of Fig. 2; wherein, A shows the profile of Cl impurities at the interface of the gate oxide layer, and B shows the impurity of Br and I impurities at the interface of the gate oxide layer ) profile curve (profile).

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

The DRAM memory device includes a capacitor and a switching transistor (not shown in the figure), and the structure of the transistor will be described in detail in this embodiment. The transistors in this embodiment may be selected from buried channel array transistors (Buried Channel Array Transistor, BCAT).

Please refer to FIG. 2 , which shows the structure of a part of the transistor. The transistor may include: a semiconductor substrate 10 ; a trench 11 is formed in the semiconductor substrate 10 , a gate oxide layer 12 is formed, and the gate oxide layer 12 is formed in the trench The gate electrode layer 13, the gate electrode layer 13 is filled in the trench 11, the gate oxide layer 12 is located between the inner wall of the trench 11 and the gate electrode layer 13; the gate oxide layer 13 does not contain Cl impurities, specifically , the gate oxide layer 13 is formed by doping C element, N element and Si element, that is, the gate oxide layer 13 may contain impurities such as C element and N element; or the gate oxide layer 13 is Br element or I element and It is formed by doping with Si element, that is, the gate oxide layer 13 may contain impurities such as Br element or I element.

Specifically, a trench 11 is opened in the semiconductor substrate 10 , a gate electrode layer 13 is formed on the sidewall and bottom wall of the trench; the gate oxide layer 12 is sandwiched between the gate electrode layer 13 and the semiconductor substrate 10 . The gate oxide layer 12 may include titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (k) dielectric materials, other suitable materials, or combinations thereof. In addition, the gate electrode layer 13 may include conductive materials such as metals (eg, tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), metal silicides (eg, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide) ), metal nitrides (eg, titanium nitride, tantalum nitride), doped polysilicon, other conductive materials, combinations thereof, and the like. In embodiments where gate electrode layer 13 is polysilicon, it may be formed by depositing doped or undoped polysilicon using low pressure chemical vapor deposition (LPCVD).

According to an embodiment disclosed in the present application, a method for fabricating a transistor is described in detail below.

A method for preparing a transistor, specifically comprising the following steps:

a: Referring to FIG. 1 , an isolation technique (eg, local oxidation of semiconductor (LOCOS), trench isolation, etc.) is used in the semiconductor substrate 10 to form a device isolation structure 14 to define at least one active region. The semiconductor substrate 10 may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) semiconductor substrate. Typically, SOI semiconductor substrate 10 includes a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other semiconductor substrates 10 that may be used include multilayer semiconductor substrates, gradient semiconductor substrates, or hybrid orientation semiconductor substrates.

b: Continuing to refer to FIG. 1, use deposition (eg, chemical vapor deposition (CVD) fabrication process or spin-on coating fabrication process), photolithography, and etching (eg, A mask pattern layer 15 is formed on the semiconductor substrate 10 by a fabrication process such as dry etching or wet etching). After that, the semiconductor substrate 10 is etched by using the mask pattern layer 15 as an etch mask to form trenches 11 in the semiconductor substrate in the active region, and then the mask pattern layer 15 is removed.

c: Referring to FIG. 2 , a gate oxide layer 12 is formed in the trench 11 (ie, the semiconductor substrate) by using a silicon precursor. The gate oxide layer 12 can be formed by a CVD fabrication process or a thermal oxidation fabrication process. Specifically, the gate oxide layer 12 can be formed in the trench 11 using a thermal atomic layer deposition process, the reaction temperature is 600-750° C., and the gas used in the atomic layer deposition process is selected from: H ₂ O ₂ and O ₂ or _NH3 and _O2 .

d: Please continue to refer to FIG. 2 , after the gate oxide layer 12 is formed, a gate electrode layer 13 may be formed on the surface of the gate oxide layer 12 in each trench 11 . The gate electrode layer 13 may be formed by a physical vapor deposition (PVD) fabrication process, a CVD fabrication process or other suitable fabrication processes. After the gate electrode layer 13 is formed, the gate oxide layer 12 and the gate electrode layer 13 may be etched back sequentially, so that the gate oxide layer 12 and the gate electrode layer 13 do not completely fill the trench 11 .

Specifically, the gate electrode layer 13 may contain conductive materials such as metals (eg, tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), metal silicides (eg, titanium silicide, cobalt silicide, nickel silicide, silicide) tantalum), metal nitrides (eg, titanium nitride, tantalum nitride), doped polysilicon, other conductive materials, or a combination of any of these. In embodiments where gate electrode layer 13 is polysilicon, it may be formed by depositing doped or undoped polysilicon using low pressure chemical vapor deposition (LPCVD).

It is worth mentioning that the silicon precursor in this embodiment includes Br element or I element, and specifically, the silicon precursor can be selected from SiBr ₄ , SiBr ₂ H ₂ , Si ₂ Br ₆ , Si ₂ Br ₄ H ₂ , SiI ₄ , SiI ₂ H ₂ , Si ₂ I ₆ , or Si ₂ Br ₄ H ₂ .

It should be noted that the covalent bond energies and bond lengths formed by Si and F, Cl, Br, and I are shown in Table 1:

Table 1

As can be seen from Table 1 and referring to Figure 3, the covalent bond energy of Br, I and silicon atom is less than that of Cl and silicon atom, and the binding force of Br, I and silicon atom is less than that of Cl and silicon atom, such as As shown in FIG. 2 , when the gate oxide layer 12 is deposited using the silicon precursor containing Br and I, since the bonding force between Br and I and silicon atoms is weaker than that of Cl, the silicon precursor containing Br and I can easily After being decomposed, the gate oxide layer 12 finally deposited only contains a small amount of impurities such as Br and I. The stacking effect caused by the residual Cl ions in the gate oxide layer 12 and the semiconductor substrate at the interface is avoided, and the problem of electric leakage of the gate oxide layer 12 is solved.

In addition, the silicon precursor can also be a silicon precursor including C element and N element, specifically, the silicon precursor is selected from SiH ₃ [N(C ₂ H ₅ ) ₂ ], SiH ₂ [N(C ₂ H ₅ ) ₂ ] ₂ , any of SiH[N(CH ₃ ) ₂ ] ₃ . Specifically, the precursor including the C element and the N element can be decomposed at a low temperature during the deposition reaction, so as to avoid the entry of impurities into the gate oxide layer 12 formed by deposition.

It should be noted that, when the transistors in this embodiment are used in semiconductor devices such as DRAM, Flash, and Logic, capacitors (not shown) coupled in series with the above transistors can be formed by a known fabrication process to complete the process. DRAM production.

Further, DRAM, Flash, and Logic having transistors in this embodiment can be used in various chips.

Further, the chip with the above transistor can be used in various electronic devices, specifically, the electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, a mobile power supply, and the like.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. a preparation method of transistor, is characterized in that, comprises the following steps: provide semiconductor substrates; forming trenches in a semiconductor substrate; A gate oxide layer is formed on the surface of the trench using an atomic layer deposition process; filling the gate electrode layer in the trench; Wherein, the silicon precursor used in the atomic layer deposition process does not contain Cl element. 2 . The method for manufacturing a transistor according to claim 1 , wherein the silicon precursor contains C element and N element. 3 . 3 . The method for manufacturing a transistor according to claim 2 , wherein the silicon precursor is selected from SiH ₃ [N(C ₂ H ₅ ) ₂ ], SiH ₂ [N(C ₂ H ₅ ) ₂ ] _2. Any of SiH[N(CH ₃ ) ₂ ] ₃ . 4 . The method for manufacturing a transistor according to claim 1 , wherein the silicon precursor contains Br element or I element. 5 . 5 . The method for preparing a transistor according to claim 4 , wherein the silicon precursor is selected from SiBr ₄ , SiBr ₂ H ₂ , Si ₂ Br ₆ , Si ₂ Br ₄ H ₂ , SiI ₄ , and SiI ₂ . Any of H ₂ , Si ₂ I ₆ , and Si ₂ Br ₄ H ₂ . 6 . The method for manufacturing a transistor according to claim 1 , wherein the gas used in the atomic layer deposition process is selected from the group consisting of: H ₂ O ₂ and O ₂ or NH ₃ and O ₂ . 7 . The method for manufacturing a transistor according to claim 1 , wherein the reaction temperature of the atomic layer deposition process is 600-750° C. 8 . 8 . The method for manufacturing a transistor according to claim 1 , wherein the gate electrode layer is selected from the group consisting of metal, metal silicide, metal nitride, doped polysilicon, or a combination of any of them. 9 . 9 . The method for fabricating a transistor according to claim 1 , wherein the gate electrode layer is formed on the gate oxide layer using a low pressure chemical vapor deposition process. 10 . 10. A transistor, characterized in that, comprising: semiconductor substrate; forming a trench in the semiconductor substrate; a gate oxide layer, the gate oxide layer is formed on the surface of the trench; a gate electrode layer, the gate electrode layer is filled in the trench; The gate oxide layer does not contain Cl impurities.

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