CN111755500A - Power semiconductor device and method of manufacturing the same - Google Patents

Abstract

The invention discloses a power semiconductor device and a manufacturing method thereof. Part of the shielding conductor of the power semiconductor device is connected to a source electrode, the shielding conductor is at a position electrically connected to the source electrode, and the shielding conductor extends from the bottom of the trench to the trench The position between the gate conductors on the inner two sides, the gate conductor and the shield conductor are separated by an isolation layer, and the shield conductor is connected with the source electrode; part of the shield conductor is not connected with the source electrode, and the shield conductor is not connected with the source electrode. At the position where the pole electrodes are electrically connected, the shield conductor extends from the bottom of the trench to the area below the gate conductor on both sides of the upper part of the trench, which reduces the parasitic resistance of the shield conductor and reduces the parasitic resistance by several tens of times.

Description

Power semiconductor device and method of manufacturing the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a power semiconductor device and a manufacturing method thereof.

Background technique

Power semiconductor devices, also known as power electronic devices, include power diodes, thyristors, VDMOS (Vertical double-diffused metal oxide semiconductor) field effect transistors, LDMOS (Laterally diffused metal oxide semiconductor, laterally diffused metal oxide semiconductor) material semiconductor) field effect transistor and IGBT (Insulated gate bipolar transistor, insulated gate bipolar transistor) and so on. A VDMOS field effect transistor includes source and drain regions formed on opposing surfaces of a semiconductor substrate, and in an on state, current flows mainly along the longitudinal direction of the semiconductor substrate.

In the high frequency application of power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. On the basis of the VDMOS field effect transistor, a trench type MOS field effect transistor is further developed, in which a gate conductor is formed in the trench, and a gate dielectric is formed on the sidewall of the trench to separate the gate conductor and the semiconductor layer , thereby forming a channel in the semiconductor layer along the direction of the sidewall of the trench. The trench (Trench) process eliminates the influence of the parasitic JFET resistance of the planar structure by changing the channel from horizontal to vertical, so that the cell size is greatly reduced. On this basis, increasing the original cell density and increasing the total width of the channel in the chip per unit area can increase the channel width to length ratio of the device on the unit silicon wafer, thereby increasing the current, reducing the on-resistance and related parameters. Optimized to achieve the goal of higher power and high performance in a smaller die size, trench technology is increasingly used in new power semiconductor devices.

However, as the cell density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly. The gate-to-drain capacitance Cgd is directly related to the switching characteristics of the device. In order to reduce the gate-to-drain capacitance Cgd, a split gate trench (SGT) type power semiconductor device has been further developed, in which the gate conductor extends to the drift region, and a thick oxide is used between the gate conductor and the drain. Therefore, the gate-to-drain capacitance Cgd is reduced, the switching speed is improved, and the switching loss is reduced. At the same time, the shield conductor under the gate conductor is connected with the source electrode and is grounded together, thereby introducing a charge balance effect and reducing the surface electric field (Reduced Surface Field, abbreviated as RESURF) in the vertical direction of the power semiconductor device. effect, further reducing the on-resistance Rdson, thereby reducing the conduction loss.

FIG. 1 shows a cross-sectional view of a power semiconductor device in the prior art. As shown in FIG. 1, the power semiconductor device includes a semiconductor substrate 101, a semiconductor layer 102 on the semiconductor substrate 101, and a trench 103 in the semiconductor layer 102, wherein the trench 103 includes The shielding dielectric layer 104 on the sidewall of the lower part of the trench, the shielding conductor 105 on the lower part of the trench, the gate conductor 106 on the upper part of the trench, the gate dielectric layer 107 on the sidewall of the upper part of the trench, and the shielding conductor The isolation layer 108 between the gate conductor 105 and the gate conductor 106 . The power semiconductor device further includes a body region 109 located in the semiconductor layer 102 adjacent to the upper portion of the trench, a source region 110 located in the body region 109, and a contact region 111 formed by concentration doping in the body region 109 to form the body region 109 , a cover dielectric layer 112 covering the semiconductor layer 102 , and a source electrode 121 connected to the contact region 111 . The trench 103 is terminated in the drift region by the body region 109, which refers to the semiconductor layer 102 between the semiconductor substrate 101 and the body region 109. The shield conductor 105 is separated from the semiconductor layer 102 by the shield dielectric layer 104 , and the gate conductor 106 is separated from the semiconductor layer 102 by the gate dielectric layer 107 . The shield conductor 105 and the gate conductor 106 are separated by an isolation layer 108 . The shielding conductor 105 forms a charge-coupled structure through the shielding dielectric layer 104 and the drift region. When the power device is turned off, a high voltage is applied to the drift region, and a low voltage is applied to the shielding conductor to couple holes on the surface of the shielding dielectric layer 104, depleting the drift. area, withstand high voltage. By increasing the withstand voltage, the concentration of the drift region can be increased and the on-resistance can be reduced.

FIG. 2 shows a schematic layout of the power semiconductor device shown in FIG. 1 . The shielding conductor 105 is led out through the contact hole 113, and is connected with the source electrode 121 of the device through the lead; the gate conductor 106 is led out through the contact hole 114 (including the contact holes 114a and 114b) to form the gate electrode. Since the shield conductor 105 is located in the middle and lower part of the trench 103, the gate conductor 106 is located on the top of the trench 103. The shield conductors 105 are drawn out only at both ends of the trenches 103. In a general manufacturing process, the shielding conductor 105 is deposited by using polysilicon, and the shape of the shielding conductor 105 in the trench is very narrow. Therefore, in Fig. 2, a large parasitic resistance occurs between the contact holes 113a and 113b of the shield conductor 105 in one trench. In the process of high-speed switching of power devices, parasitic resistance will cause signal transmission delay in cells far away from the lead-out position of the shielding conductor, and the switching action will be slow. If the power device is subjected to high voltage at this time, there will be an instantaneous large current, which will increase the power consumption of the power device. At the same time, high voltage will cause dynamic avalanche breakdown, which will affect the long-term reliability of power devices.

In order to solve the reliability risk caused by the asynchronous cell switching action of the device in high-speed switching applications. In the trench 103, the positions of the shield conductor 105 and the gate conductor 106 are adjusted, the shield conductor 105 is located in the middle of the trench, and the gate conductor 106 is located on the left and right sides of the upper part of the trench, as shown in FIG. 3 . With this structure, the shield electrode 122 can be formed directly on the top of the shield conductor 105, and the shield conductor can be directly connected to the source metal in the entire trench, which greatly reduces the parasitic resistance of the shield conductor 105. However, this structure also brings problems. The shield conductor 105 and the gate conductor 106 are insulated by a dielectric layer in the horizontal direction, and the two have a large overlapping area, resulting in parasitic capacitance. Since the shield conductor is connected to the source, this part of the parasitic capacitance becomes part of the input capacitance. When the power device is turned on and off, this part of the extra capacitor needs to be charged and discharged, resulting in extra loss.

As the operating frequency of the power supply becomes higher and higher, the loss of the device is proportional to the operating frequency, and it is necessary to consider reducing the loss while ensuring reliability.

SUMMARY OF THE INVENTION

In view of the above problems, an object of the present invention is to provide a power semiconductor device and a method for manufacturing the same.

According to a first aspect of the present invention, there is provided a power semiconductor device, comprising: a substrate; a semiconductor layer on the substrate; a plurality of trenches in the semiconductor layer; a body region in the semiconductor layer, the a body region adjacent to the upper part of the plurality of trenches; a source region located in the body region; a shielding dielectric layer located in the plurality of trenches, wherein the shielding dielectric layer covers the sidewalls of the lower part of the trenches and a bottom; a shield conductor, the shield conductor portion extending from the upper part of the trench to the bottom; a gate conductor on both sides of the upper inner part of the trench; a source electrode connected to the source region; A gate electrode electrically connected to a gate conductor; wherein the gate conductor and the body region are separated by a gate dielectric layer; the shielding conductor and the semiconductor layer are separated by a shielding dielectric layer; The gate conductors on both sides of the upper part of the trench are separated by an isolation layer; part of the shield conductor is connected to the source electrode, and the shield conductor is electrically connected to the source electrode at the position where the shield conductor extends from the trench. The bottom of the trench extends to the position between the gate conductors on both sides of the trench, the gate conductor and the shield conductor are separated by an isolation layer, and the shield conductor is connected to the source electrode; part of the shield conductor is not. In connection with the source electrode, the shield conductor extends from the bottom of the trench to the region below the gate conductor on both sides of the upper part of the trench at a position not electrically connected to the source electrode.

Preferably, the power semiconductor device includes a first region divided along the length of the trench and a plurality of alternating second and third regions.

Preferably, the first region includes a first contact hole located in the first region, wherein the gate electrode is electrically connected to the gate conductor through the first contact hole; The shield conductor is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to the regions below the gate conductor on both sides of the upper part of the trench.

Preferably, the second region includes a second contact hole in the second region, the source electrode is electrically connected to the shielding conductor through the second contact hole, and the shielding conductor of the second region extends from the trench The bottom of the trench extends to a position between the gate conductors on both sides of the trench, and further includes a third contact hole located in the second region and the third region, wherein the source electrode is connected to the source electrode through the third contact hole. The source regions are electrically connected.

Preferably, the third region includes a third contact hole located in the second region and the third region, wherein the source electrode is electrically connected to the source region through the third contact hole, and the third The shield conductor of the region is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to the region below the gate conductor on both sides of the upper portion of the trench.

Preferably, a part of the shield conductor is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to below the isolation layer at a position where the shield conductor is not electrically connected to the source electrode.

Preferably, along the length of the trench, the distance between the plurality of second contact holes is 20um˜500um.

Preferably, the shielding dielectric layer has a thickness of 1000 angstroms to 20000 angstroms, and the gate dielectric layer has a thickness of 600 angstroms to 3000 angstroms.

Preferably, the depth of the groove is 1 um˜45 um.

Preferably, the distance between the top surface of the gate conductor and the first surface of the semiconductor layer is 0um˜0.2um.

Preferably, at the position where the shield conductor is electrically connected to the source electrode, the distance between the top surface of the shield conductor and the first surface of the semiconductor layer is 0um˜0.5um.

Preferably, at the position where the shield conductor is not electrically connected to the source electrode, the distance between the top surface of the shield conductor and the first surface of the semiconductor layer is 0.5um˜1.5um.

Preferably, the depth of the gate conductor is 0.4um˜1.5um.

Preferably, the length of the shield conductors located between the gate conductors along the length of the trench is 3um˜6um.

Preferably, the length of the shield conductor between the gate conductors along the length of the trench is the same as the length of the single second contact hole along the length of the trench.

Preferably, the spacing between the plurality of grooves is 2um˜9um.

Preferably, the thickness of the isolation layer between the shield conductor and the gate conductor is 0.1um˜2um.

Preferably, the width of the shielded conductor is 0.4um˜4um.

Preferably, the gate conductor and the shield conductor are polysilicon.

Preferably, the power semiconductor device further includes: a cover dielectric layer located on the first surface of the semiconductor layer, and the first contact hole, the second contact hole, and the third contact hole pass through the cover dielectric layer.

Preferably, the semiconductor layer is of a first doping type, the source region is of a first doping type, the body region is of a second doping type, and the second doping type is the same as the first doping type Type is the opposite.

Preferably, the power semiconductor device is a MOS device, and the semiconductor layer is a drain region.

Preferably, the power semiconductor device is an IGBT device, and the semiconductor layer is a base region.

Preferably, the power semiconductor device further comprises: a buffer layer located between the substrate and the semiconductor layer.

Preferably, the materials of the shielding dielectric layer, the gate dielectric layer and the isolation layer include any one of silicon dioxide, silicon nitride, a composite structure of silicon dioxide and silicon nitride. The materials of the layers and the isolation layer are the same or different.

According to another aspect of the present invention, a method for manufacturing a power semiconductor device is provided, comprising: forming a semiconductor layer on a substrate; forming a plurality of trenches in the semiconductor layer; forming a shield in the plurality of trenches a dielectric layer, the shielding dielectric layer covers the sidewalls and the bottom of the lower part of the trench; a shielded conductor is formed in the trench, and the shielded conductor part extends from the upper part of the trench to the bottom; in the trench forming a gate conductor on both sides of the inner upper part; forming a body region in the semiconductor layer, the body region being adjacent to the upper part of the plurality of trenches; forming a source region in the body region; forming an electrical connection with the gate conductor a gate electrode connected; and forming a source electrode electrically connected to the shield conductor and the source region; wherein the gate conductor and the body region are separated by the gate dielectric layer; the The shielding conductor and the semiconductor layer are separated by a shielding medium layer; the gate conductors on both sides of the upper part of the trench are separated by an isolation layer; part of the shielding conductor is connected to the source electrode, and the shielding conductor is At the position electrically connected to the source electrode, the shield conductor extends from the bottom of the trench to the position between the gate conductors on both sides of the trench, and the gate conductor and the shield conductor are separated by an isolation layer, so The shielding conductor is connected to the source electrode; part of the shielding conductor is not connected to the source electrode, and the shielding conductor extends from the bottom of the trench at the position where the shielding conductor is not electrically connected to the source electrode to the area under the gate conductor on both sides of the upper part of the trench.

Preferably, the power semiconductor device includes a first region divided along the length of the trench and a plurality of alternating second and third regions.

Preferably, the method further includes: forming a first contact hole on the gate conductor in the first region, wherein the gate electrode is electrically connected to the gate conductor through the first contact hole ; The shield conductor of the first region is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to the regions below the gate conductor on both sides of the upper portion of the trench.

Preferably, the method further comprises: forming a second contact hole on the shield conductor in the second region, wherein the source electrode is electrically connected to the shield conductor through the second contact hole, so The shield conductor of the second region extends from the bottom of the trench to a position between the gate conductors on both sides of the trench; and a third contact hole is formed on the source region, wherein the source electrode passes through the third contact hole. A contact hole is electrically connected to the source region.

Preferably, the method further includes: forming a third contact hole on the source region in the third region and the second region, wherein the source electrode is electrically connected to the source region through the third contact hole ; the shield conductor is located under the gate conductor, the shield conductor in the third region is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to the gates on both sides of the upper part of the trench the area under the conductor.

Preferably, a part of the shield conductor is not connected to the source electrode, and the shield conductor extends from the bottom of the trench to below the isolation layer at a position where the shield conductor is not electrically connected to the source electrode.

Preferably, along the length direction of the trench, the distance between the plurality of second contact holes is 20um˜500um.

Preferably, the shielding dielectric layer has a thickness of 1000 angstroms to 20000 angstroms, and the gate dielectric layer has a thickness of 600 angstroms to 3000 angstroms.

Preferably, the depth of the groove is 1 um˜45 um.

Preferably, the distance between the top surface of the gate conductor and the first surface of the semiconductor layer is 0um˜0.2um.

Preferably, at the position where the shield conductor is electrically connected to the source electrode, the distance between the top surface of the shield conductor and the first surface of the semiconductor layer is 0um˜0.5um.

Preferably, at the position where the shield conductor is not electrically connected to the source electrode, the distance between the top surface of the shield conductor and the first surface of the semiconductor layer is 0.5um˜1.5um.

Preferably, the depth of the gate conductor is 0.4um˜1.5um.

Preferably, the length of the shield conductors located between the gate conductors along the length of the trench is 3um˜6um.

Preferably, the length of the shield conductor between the gate conductors along the length of the trench is the same as the length of the single second contact hole along the length of the trench.

Preferably, the spacing between the plurality of grooves is 2um˜9um.

Preferably, the thickness of the isolation layer between the shield conductor and the gate conductor is 0.1um˜2um.

Preferably, the width of the shielded conductor is 0.4um˜4um.

Preferably, the gate conductor and the shield conductor are polysilicon.

Preferably, the method further comprises: forming a cover dielectric layer on the first surface of the semiconductor layer.

Preferably, the semiconductor layer is of a first doping type, the source region is of a first doping type, the body region is of a second doping type, and the second doping type is the same as the first doping type Type is the opposite.

Preferably, when the power semiconductor device is a MOS device, the semiconductor layer is a drain region.

Preferably, when the power semiconductor device is an IGBT device, the semiconductor layer is a base region.

Preferably, the method further comprises: forming a buffer layer between the substrate and the semiconductor layer.

Preferably, the materials of the shielding dielectric layer, the gate dielectric layer and the isolation layer include any one of silicon dioxide, silicon nitride, a composite structure of silicon dioxide and silicon nitride. The materials of the layers and the isolation layer are the same or different.

In the power semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention, part of the shield conductor is connected to the source electrode, and the shield conductor is electrically connected to the source electrode at the position where the shield conductor extends from the bottom of the trench. It extends to the position between the gate conductors on both sides of the trench, the gate conductor and the shield conductor are separated by an isolation layer, and the shield conductor is connected with the source electrode; part of the shield conductor is not connected with all the shield conductors. The source electrode is connected, and the shield conductor extends from the bottom of the trench to the area below the gate conductor on both sides of the upper part of the trench at the position where the shield conductor is not electrically connected to the source electrode, reducing the shielding. The parasitic resistance of the conductor reduces the parasitic resistance by several tens of times.

Further, the shield conductor only extends from the bottom of the trench to the position between the gate conductors on both sides of the trench in the second region where the second contact holes arranged at intervals are located, and the shield conductor extends from the bottom of the trench to the position between the gate conductors on both sides of the trench in the remaining regions. In the regions below the gate conductor on both sides of the upper part of the trench, the parasitic capacitance between electrodes can be reduced, so that the parasitic resistance can be reduced by several tens of times.

Further, the positions of the second contact holes connected with the shielding conductors are integrated inside the cell, which reduces the area of the chip and improves the integration degree of the chip.

Further, using the power semiconductor device provided by the embodiment of the present invention can not only reduce the switching loss when the device is turned on and off, but also reduce the occurrence of dynamic avalanche of the device and improve the reliability of the device.

Description of drawings

The above-mentioned and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

1 shows a cross-sectional view of a power semiconductor device in the prior art;

FIG. 2 shows a schematic layout of the power semiconductor device shown in FIG. 1;

3 shows a perspective cross-sectional view of another power semiconductor device in the prior art;

FIG. 4 shows a schematic layout diagram of a power semiconductor device provided according to an embodiment of the present invention;

Fig. 5 shows the cross-sectional view taken along line AA' of the top view of the power semiconductor device shown in Fig. 4;

Fig. 6 shows the cross-sectional view taken along the line BB' of the top view of the power semiconductor device shown in Fig. 4;

Fig. 7 shows the cross-sectional view taken along CC' line of the top view of the power semiconductor device shown in Fig. 4;

Figures 8a to 8e show three-dimensional cross-sectional views of different stages of a method for manufacturing a power semiconductor device provided by an embodiment of the present invention;

FIG. 9 shows a three-dimensional cross-sectional view of a power semiconductor device provided by another embodiment of the present invention.

Detailed ways

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are designated by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

In the power semiconductor device described in the following embodiments, the shield conductor in one trench has a plurality of lead-out positions in the longitudinal direction of the trench, which solves the problem of the two ends of the lead-out position of the shield conductor in the longitudinal direction of the trench in the conventional structure. Too long terminal distance leads to the problem that the parasitic resistance of the shielded conductor is too large.

4 shows a schematic layout diagram of a power semiconductor device provided by an embodiment of the present invention; wherein, FIG. 5 is a cross-sectional view taken along line AA' in the schematic layout diagram shown in FIG. 4 , and FIG. 6 is a top view shown in FIG. A cross-sectional view taken along line BB'; FIG. 7 is a cross-sectional view taken along line CC' in the top view shown in FIG. 4 . In this embodiment, the power semiconductor device is a trench type device, which may be a metal oxide semiconductor field effect transistor (MOSFET), an IGBT device or a diode. Hereinafter, an N-type MOSFET is taken as an example for description, however, the present invention is not limited to this.

The power semiconductor device shown in Figures 5-7 only contains one cell structure, but in actual products, the number of cell structures can be one or more. 5-7, the power semiconductor device includes a semiconductor substrate 201, a semiconductor layer 202 on the semiconductor substrate 201, and a trench 203 in the semiconductor layer 202. The power semiconductor device further includes a shield conductor 205 located at the lower part of the trench 203 , a gate conductor 206 located on the left and right sides of the upper part of the trench 203 and an isolation layer 208 sandwiched therebetween, and a sidewall located at the lower part of the trench 203 . and the shielding dielectric layer 204 at the bottom and the gate dielectric layer 207 on the upper sidewall of the trench 203 . The power semiconductor device also includes a body region 209 in the semiconductor layer 202 and a source region 210 in the body region.

In this embodiment, the semiconductor substrate 201 is, for example, a silicon substrate, and its doping type is the first doping type, such as N-type, and the longitudinal doping of the silicon substrate is uniform. The semiconductor substrate 201 has opposing first and second surfaces. The semiconductor layer 202 is, for example, the epitaxial layer 202 formed on the semiconductor substrate 201. The semiconductor layer 202 is of the same doping type as the semiconductor substrate 201 . The semiconductor layer 202 has opposing first and second surfaces. The body region 209 is of the second doping type, such as P-type. The source region 210 is of a first doping type, such as N-type.

In this embodiment, the power semiconductor device is a MOS device, and the semiconductor layer 202 is a drain region.

The shielding conductor 205 is separated from the semiconductor layer 202 by a shielding dielectric layer 204, and the gate conductor 206 and the body region 209 are separated by a gate dielectric layer 207.

In this embodiment, the materials of the shielding dielectric layer 204, the gate dielectric layer 207 and the isolation layer 208 may be any one of the composite structures of silicon dioxide, silicon nitride, silicon dioxide and silicon nitride. Materials can be the same or different.

Further, concentration doping is performed in the body region 209 to form the contact region 211 of the body region 209 . The body region 209 is of the second doping type, eg, P-type.

As shown in Fig. 4, the trenches 203 are spaced along the lateral direction X of the power semiconductor device and extend along the longitudinal direction Y of the power semiconductor device.

The power semiconductor device further includes a cover dielectric layer 212 on the first surface of the semiconductor layer 202, and a first contact hole 213, a second contact hole 214 and a third contact hole 215 penetrating the cover dielectric layer 212; the first contact hole 214 The contact hole 213 extends through the cover dielectric layer 212 to the gate conductor 206; the second contact hole 214 extends through the cover dielectric layer 212 to the shield conductor 205; the third contact hole 215 penetrates the The capping dielectric layer 212 extends to the source region 210 . A metal layer is deposited on the cover dielectric layer 212, the metal layer fills the first contact hole 213 to form the gate electrode 221; the metal layer fills the second contact hole 214 and the third contact hole 215 to form the source region The source electrode 222 is electrically connected to the shield conductor.

In this embodiment, the cover dielectric layer 212 may be undoped silica glass (USG, Undoped silica glass) or borophosphorus-doped silica glass (BPSG, Borophosphorus-doped silica glass). In this embodiment, the material of the metal layer may be titanium, titanium nitride, aluminum copper, aluminum silicon copper or aluminum silicon.

As shown in FIG. 4 , the power semiconductor device includes a first region I, a second region II and a third region III, wherein the first region I, the second region II and the third region III are along the power The longitudinal direction Y of the semiconductor device is divided, and the longitudinal direction Y is the length direction of the trench. The first region I is the lead region of the gate conductor 206, the second region II is the lead region of the shield conductor 205, and the third region III is the lead region of the source region 210.

The first contact hole 213 is located in the first area I, the second contact hole 214 is located in the second area II, and the third contact hole 215 is located in the second area II and the third area III. Specifically, the gate conductor 206 in the trench 203 forms a first contact hole 213 at one end of the trench 203 extending longitudinally; the shield conductor 205 is provided with a plurality of second contact holes 214 at intervals in the longitudinal direction of the trench 203; A third contact hole 215 is formed in the source region 210 from one end to the other end of the source region 210 extending longitudinally.

The shielded conductor 205 has a plurality of lead-out positions in the longitudinal direction of the groove 203, and the plurality of lead-out positions correspond to the plurality of second contact holes 214 one-to-one respectively. The bottom extends to the position between the gate conductors 206 on both sides of the trench 203, and the gate conductor 206 and the shield conductor 205 are separated by the isolation layer 208; and in the non-extracted position, the shield conductor 205 is from the bottom of the trench 203. It extends to the area under the gate conductor 206 on both sides of the upper part of the trench 203 . In the first region I and the third region III, the top surface of the shield conductor 205 is lower than the bottom surface of the gate conductor 206, that is, the shield conductor 205 is located below the gate conductor 206 and is isolated from each other; in the second region II , at the lead-out position of the shield conductor, the top surface of the shield conductor 205 is higher than the bottom surface of the gate conductor 206 and lower than the top surface of the gate conductor 206, that is, the shield conductor 205 extends from the bottom of the trench 203 to the inside of the trench 203 two Between the gate conductors 206 on the side, the gate conductors 206 and the shield conductors 205 are separated by an isolation layer 208 .

As shown in FIG. 5 , in the first region I, the shield conductors 205 are located below the gate conductors 206 and are isolated from each other, and the gate electrodes 221 are electrically connected to the gate conductors 206 through the first contact holes 213.

As shown in FIG. 6 , in the second region II, at the lead-out position of the shield conductor, the shield conductor 205 extends from the bottom of the trench 203 to the position between the gate conductors 206 on both sides of the trench 203, and the gate conductor 206 It is separated from the shield conductor 205 by an isolation layer 208 .

As shown in FIG. 7 , in the third region III, the shield conductors 205 are located under the gate conductors 206 and are isolated from each other, and the source electrodes 222 are electrically connected to the source regions 210 through the third contact holes 215.

In this embodiment, the depth of the trenches 203 is 1um-45um, the center spacing (that is, the spacing between adjacent trenches 203) is 2um-9um, and the width is 0.5um-6um. The length of the groove 203 is described taking 1.5 mm as an example. The width of the shielding conductor 205 is 0.25um, and the distance between its top surface and the first surface of the semiconductor layer 202 in the first and third regions is 0.5um-1.5um; in the second region, the top surface and the semiconductor layer The distance between the first surfaces of the layers 202 is 0˜0.5 μm. Along the length direction of the trench (ie, the longitudinal direction), the spacing distance between the plurality of second contact holes 214 is 20um˜500um. The depth of the gate conductor 206 is 0.4˜1.5 μm, and the distance between the top surface thereof and the first surface of the semiconductor layer 202 is 0˜0.2 μm. The thickness of the shielding dielectric layer 204 ranges from 1000 angstroms to 20000 angstroms. The thickness of the gate dielectric layer 207 is 600 angstroms˜3000 angstroms. The length of the shield conductor 205 between the gate conductors 206 along the length of the trench is the same as the length of the single second contact hole 214 along the length of the trench, generally 3um-6um. The thickness of the isolation layer 208 between the shielding conductor 205 and the gate conductor 206 is 0.1um˜2um. The width of the shield conductor 205 is 0.4um˜4um.

In the power semiconductor device provided by the embodiment of the present invention, a part of the shield conductor is connected to the source electrode, and the shield conductor extends from the bottom of the trench to the trench at the position where the shield conductor is electrically connected to the source electrode. The position between the gate conductors on the inner two sides, the gate conductor and the shield conductor are separated by an isolation layer, and the shield conductor is connected with the source electrode; part of the shield conductor is not connected with the source electrode At the position where the shield conductor is not electrically connected to the source electrode, the shield conductor extends from the bottom of the trench to the area below the gate conductor on both sides of the upper part of the trench, reducing the parasitic resistance of the shield conductor , which reduces the parasitic resistance by several tens of times.

Further, the shield conductor only extends from the bottom of the trench to the position between the gate conductors on both sides of the trench in the second region where the second contact holes arranged at intervals are located, and the shield conductor extends from the bottom of the trench to the position between the gate conductors on both sides of the trench in the remaining regions. In the regions below the gate conductor on both sides of the upper part of the trench, the parasitic capacitance between electrodes can be reduced, so that the parasitic resistance can be reduced by several tens of times.

Further, the positions of the second contact holes connected with the shielding conductors are integrated inside the cell, which reduces the area of the chip and improves the integration degree of the chip.

Further, when the device is turned off, a low voltage needs to be applied to the shield electrode. The low-voltage signal will be conducted to the cell structure near the shield electrode firstly through the metal trace, and the cell structure far away from the shield electrode, due to the influence of parasitic resistance, the transmission of the signal will slow down and not be completely turned off. At this time, if the device is subjected to high voltage, the cell structure that is not completely turned off will have a large current, high voltage and large current, which further increases the power consumption. At the same time, applying high voltage on the cell structures that are not completely turned off will also cause these cell structures to break down instantaneously, resulting in dynamic avalanche and reliability problems. When the device is working, the device is turned on and off by charging and discharging the parasitic capacitance of the gate electrode. As the switching frequency of the device increases, the losses due to parasitic capacitance charging and discharging become non-negligible. With this embodiment, the problem of turn-off delay caused by the parasitic resistance of the shield electrode is effectively avoided, and the extra power consumption of the parasitic capacitance of the gate electrode is also reduced at the same time.

Figures 8a-8e show three-dimensional cross-sectional views of different stages of a method for manufacturing a power semiconductor device provided by an embodiment of the present invention. It should be noted that the manufacturing steps of the power semiconductor device are only illustrative, and are not limited thereto.

As shown in FIG. 8a , a semiconductor layer 202 is formed on the semiconductor substrate 201 . Silicon dioxide or silicon nitride is deposited on the surface of the semiconductor layer 202 as a hard mask, and a processing method such as plasma etching is used to etch the trenches 203 in the semiconductor layer 202. The depth of the grooves 203 is 1-45um, the center-to-center spacing is 2-9um, and the width is 0.5-6um.

In this embodiment, the semiconductor substrate 201 is, for example, a silicon substrate, its doping type is the first doping type, such as N-type, and the longitudinal doping of the silicon substrate is uniform. The semiconductor substrate 201 has opposing first and second surfaces. The semiconductor layer 202 is, for example, an epitaxial layer formed on the first surface of the semiconductor substrate 201. The semiconductor layer 202 is of the same doping type as the semiconductor substrate 201. The semiconductor layer 202 has opposing first and second surfaces.

Further, a shielding dielectric layer 204 is formed by growing an oxide layer in the trench 203 and on the first surface of the semiconductor layer 202 by means of thermal oxidation. The thickness of the shielding dielectric layer 204 is generally 1000 angstroms to 20000 angstroms. The temperature of thermal oxidation is 900°C to 1150°C.

Preferably, the shielding dielectric layer 204 can also be formed by LPCVD (Low Pressure Chemical VaporDeposition, low pressure chemical vapor deposition) or SACVD (Sub-atmospheric Chemical VaporDeposition, sub-atmospheric pressure chemical vapor deposition) or PECVD (Plasma Enhanced Chemical VaporDeposition, plasma chemical vapor deposition) ) direct deposition; it is also possible to thermally oxidize a part of the thickness and then deposit the remaining thickness by LPCVD or SACVD or PECVD. This part of the deposited oxide layer is then densified by a high temperature of 900°C to 1150°C.

As shown in FIG. 8b, polysilicon is deposited on the surface of the shielding dielectric layer 204 and in the trench 203. In order to reduce the resistance of the polysilicon, a high concentration of N-type doping is generally performed on the polysilicon, so that the resistance of the polysilicon is reduced to 5-20 Ohm/square. The polysilicon is etched, the polysilicon on the semiconductor layer 202 is removed, and the polysilicon in the trench 203 is retained. Then, the polysilicon in the trench 203 is etched to form the shield conductor 205, and the etching time is controlled so that the distance between the shield conductor 205 and the first surface of the semiconductor layer 202 is 0.0-0.5um. A photoresist is deposited in the second region II, and the photoresist that retains the contact holes 214 of the shielded conductor 205 is exposed (this photolithography pattern does not appear in the illustration), and then the first region I and the trenches 203 in the first region I and The polysilicon in the third region III is etched so that the distance between the shield conductor 205 in the first region I and the third region III and the first surface of the semiconductor layer 202 is 0.5-1.5um. Therefore, the distance between the shield conductor 205 in the second region II and the first surface of the semiconductor layer 202 is 0.0-0.5um. The width of the shield conductor 205 is 0.4um˜4um.

After removing the surface photoresist, a dielectric is deposited on the surface to fill the gaps exposed by etching on the top of the polysilicon in the trench 203, and an oxide layer is formed on the first surface of the semiconductor layer 202 (this step does not appear in the legend) . The oxide layer on the first surface of the semiconductor layer 202 is removed by CMP (Chemical Mechanical Polishing) method, and finally an oxide layer of 200-500 angstroms remains on the first surface of the semiconductor layer 202.

As shown in Figure 8c, the photoresist is deposited, and after exposure, the photoresist remains on the top of the polysilicon in the trench 203, and extends left and right by 0.1-0.5um, completely covering the oxide layer on the top of the polysilicon (this lithography pattern does not appear on the top of the polysilicon). in the legend). The oxide layer is etched dry or wet, and grooves 231 are etched on the left and right sides of the top of the trench 203 . The depth of the groove 231 is 0.4-1.5um, and the width is 0.2-0.7um.

As shown in Figure 8d, after removing the surface photoresist, a sacrificial oxide layer is grown at a low temperature of 900-1000 °C with a thickness of 200-1000 angstroms to repair the damage to the silicon surface during the etching process, and remove this layer by wet method. After sacrificing oxidation. A gate oxide layer 207 of 500-1000 angstroms is grown at a low temperature of 900-1000°C. In some processes, the gate oxide layer 207 may be grown directly without growing the sacrificial oxide layer. Deposit N-type heavily doped polysilicon, remove the polysilicon on the surface of the semiconductor layer 202 by etching or CMP, continue to etch the polysilicon in the groove 231 to form the gate conductor 206, and then form the isolation layer 208, the gate conductor The distance between the top surface of 206 and the first surface of semiconductor layer 202 is 0-2000 angstroms. The thickness of the isolation layer 208 between the shielding conductor 205 and the gate conductor 206 is 0.1um˜2um.

Depositing photoresist, exposing the photolithography region of the P-type body region, performing P-type doping (ie, implanting P-type doping type ions), after annealing at 950 ° C ~ 1150 ° C for 30 ~ 90 minutes or 900 ° C ~ Rapid annealing at 1150° C. forms a P-type body region 209 . After removing the photoresist, the photolithography area of the N-type source region is exposed again, and N-type concentrated doping is performed (that is, the N-type concentrated doping ions are injected), and N-type is formed after annealing at 850 ° C ~ 1000 ° C for 10 ~ 30 minutes. A heavily doped source region 210 is formed. After removing the photoresist, a covering dielectric layer 212 is deposited, which is generally a composite dielectric layer of NSG (non-doped silica glass) and BPSG (borophosphosilicate glass), and the overall thickness is 4000-8000 angstroms.

As shown in FIG. 8e, photoresist is deposited, exposed, and the dielectric layer 212 is covered by wet or dry etching to form a first contact hole 213 (not shown in the figure), a second contact hole 214 and a third contact hole 214. Contact holes 215 , wherein the first contact hole 213 is connected with the gate conductor 206 , the second contact hole 214 is connected with the shield conductor 205 , and the third contact hole 215 is connected with the source region 210 . P-type concentrated doping is implanted, and a contact region 211 of the P-type body region 209 is formed after rapid annealing at 900-1100°C. After removing the photoresist, deposit titanium, titanium nitride and tungsten in the first contact hole 213, the second contact hole 214 and the third contact hole 215 to form a tungsten plug, deposit metal, and etch to form a gate electrode 221 and the source electrode 222 . The gate electrode 221 is electrically connected to the gate conductor 206 , and the source electrode 222 is electrically connected to the source region 210 and the shield conductor 205 .

For a clearer description, the longitudinal schematic diagram of Fig. 8e taken along BB' is Fig. 6, and the longitudinal schematic diagram of the cross-section taken along CC' is Fig. 7.

In the above embodiment, the doping type of the semiconductor layer 202 is the first doping type, the doping type of the source region 210 is the second doping type, the first doping type is N-type doping, and the second doping type is For P-type doping, N-type power semiconductor devices are formed.

In an alternative embodiment, the doping type of the semiconductor layer 202 and the doping type of the source region 210 are interchanged, that is, the first doping type is P-type doping, the second doping type is N-type doping, A P-type power semiconductor device is formed.

FIG. 9 shows a three-dimensional cross-sectional view of a power semiconductor device provided by another embodiment of the present invention. The power semiconductor device is an IGBTI device. Compared with the power semiconductor device described in FIG. 8e, the main difference lies in that a buffer layer 340 is formed between the semiconductor substrate 301 and the semiconductor layer 302, and a buffer layer 340 is formed on the buffer layer 340, and the semiconductor layer 302 is the base electrode Floor. The semiconductor substrate 301 is, for example, a silicon substrate, and its doping type is the first doping type, such as P-type, and a heavily doped P-type substrate is formed by P-type implantation or diffusion. The doping type of the buffer layer 340 is the second doping type, such as N-type, and the N-type buffer layer is formed by implantation or expansion.

The remaining aspects of this embodiment are the same as those of the previous embodiment, and are not repeated here.

Embodiments in accordance with the present invention are described above, and these embodiments are not intended to be exhaustive in all details, nor do they limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The invention is to be limited only by the claims and their full scope and equivalents.

Claims (50)

1. A power semiconductor device, comprising:

a substrate;

a semiconductor layer on the substrate;

a plurality of trenches in the semiconductor layer;

a body region in the semiconductor layer, the body region adjacent to an upper portion of the plurality of trenches;

a source region located in the body region;

the shielding dielectric layers are positioned in the grooves, and the side walls and the bottoms of the lower parts of the grooves are covered by the shielding dielectric layers;

a shield conductor partially extending from an upper portion to a bottom portion of the trench;

the grid conductors are positioned on two sides of the upper part in the groove;

a source electrode connected to the source region; and

a gate electrode electrically connected to the gate conductor;

the grid conductor and the body region are separated by a grid dielectric layer; the shielding conductor is separated from the semiconductor layer by a shielding medium layer; the grid conductors on two sides of the upper part of the groove are separated by an isolating layer;

part of the shielding conductor is connected with the source electrode, the shielding conductor is electrically connected with the source electrode, extends from the bottom of the groove to a position between the grid conductors at two sides in the groove, the grid conductors and the shielding conductor are separated by the isolating layer, and the shielding conductor is connected with the source electrode;

a portion of the shield conductor is not connected to the source electrode, the shield conductor extending from the bottom of the trench to a region below the gate conductor on both sides of the upper portion of the trench at a position not electrically connected to the source electrode.

2. The power semiconductor device of claim 1, comprising a first region and a plurality of alternating second and third regions divided along a length of the trench.

3. The power semiconductor device of claim 2, wherein the first region includes a first contact hole in the first region, wherein the gate electrode is electrically connected to the gate conductor through the first contact hole; the shield conductor of the first region is not connected to the source electrode, and extends from the bottom of the trench to a region below the gate conductor on both sides of the upper portion of the trench.

4. The power semiconductor device of claim 2, wherein the second region includes a second contact hole in the second region through which the source electrode is electrically connected to the shield conductor, the shield conductor of the second region extending from the bottom of the trench to a position between the gate conductors on both sides within the trench, and a third contact hole in the second region and the third region, wherein the source electrode is electrically connected to the source region through the third contact hole.

5. The power semiconductor device of claim 2, wherein the third region includes a third contact hole in the second and third regions, wherein the source electrode is electrically connected to the source region through the third contact hole, wherein the shield conductor of the third region is not connected to the source electrode, and wherein the shield conductor extends from the bottom of the trench to a region below the gate conductor on both sides of the upper portion of the trench.

6. The power semiconductor device according to any one of claims 1 to 5, wherein a portion of the shield conductor is not connected to the source electrode, the shield conductor being at a position not electrically connected to the source electrode, the shield conductor extending from a bottom of the trench to below the isolation layer.

7. The power semiconductor device according to claim 4, wherein the plurality of second contact holes are spaced apart by a distance of 20um to 500um in a length direction of the trench.

8. The power semiconductor device according to any of claims 1-5, wherein the thickness of the shielding dielectric layer is 1000-20000 angstroms and the thickness of the gate dielectric layer is 600-3000 angstroms.

9. The power semiconductor device of any of claims 1-5, wherein the trench has a depth of 1um to 45 um.

10. The power semiconductor device of any of claims 1-5, wherein a distance between a top surface of the gate conductor and the first surface of the semiconductor layer is between 0um and 0.2 um.

11. The power semiconductor device according to any one of claims 1 to 5, wherein a distance between a top surface of the shielding conductor and the first surface of the semiconductor layer at a position where the shielding conductor is electrically connected to the source electrode is 0um to 0.5 um.

12. The power semiconductor device according to any one of claims 1 to 5, wherein a distance between a top surface of the shield conductor and the first surface of the semiconductor layer at a position where the shield conductor is not electrically connected to the source electrode is 0.5um to 1.5 um.

13. The power semiconductor device of any of claims 1-5, wherein the depth of the gate conductor is between 0.4um and 1.5 um.

14. The power semiconductor device of claim 2, wherein the length of the shield conductor between the gate conductors along the length direction of the trench is between 3um and 6 um.

15. The power semiconductor device of claim 2, wherein a length of the shield conductor between the gate conductors in a direction along a length of the trench is the same as a length of the single second contact hole in the direction along the length of the trench.

16. The power semiconductor device according to any one of claims 1-5, wherein a pitch between the plurality of trenches is 2um to 9 um.

17. The power semiconductor device according to any of claims 1-5, wherein a thickness of the isolation layer between the shield conductor and the gate conductor is 0.1um to 2 um.

18. The power semiconductor device according to any one of claims 1-5, wherein the width of the shielding conductor is 0.4um to 4 um.

19. The power semiconductor device of any of claims 1-5, wherein the gate conductor and the shield conductor are polysilicon.

20. The power semiconductor device of claim 5, further comprising:

and the covering dielectric layer is positioned on the first surface of the semiconductor layer, and the first contact hole, the second contact hole and the third contact hole penetrate through the covering dielectric layer.

21. The power semiconductor device of claim 1, wherein said semiconductor layer is of a first doping type, said source region is of a first doping type, and said body region is of a second doping type, said second doping type being opposite to said first doping type.

22. The power semiconductor device of claim 1, wherein the power semiconductor device is a MOS device and the semiconductor layer is a drain region.

23. The power semiconductor device of claim 1, wherein the power semiconductor device is an IGBT device and the semiconductor layer is a base region.

24. The power semiconductor device of claim 19, further comprising:

a buffer layer between the substrate and the semiconductor layer.

25. The power semiconductor device according to claim 1, wherein the shielding dielectric layer, the gate dielectric layer and the isolation layer are made of any one of silicon dioxide, silicon nitride and a composite structure of silicon dioxide and silicon nitride, and the shielding dielectric layer, the gate dielectric layer and the isolation layer are made of the same or different materials.

26. A method of manufacturing a power semiconductor device, comprising:

forming a semiconductor layer on a substrate;

forming a plurality of trenches in the semiconductor layer;

forming shielding dielectric layers in the grooves, wherein the shielding dielectric layers cover the side walls and the bottoms of the lower parts of the grooves;

forming a shield conductor within the trench, the shield conductor extending partially from an upper portion to a bottom portion of the trench;

forming gate conductors on two sides of the upper part in the groove;

forming a body region in the semiconductor layer, the body region being adjacent to an upper portion of the plurality of trenches;

forming a source region in the body region;

forming a gate electrode electrically connected to the gate conductor; and

forming a source electrode electrically connected to the source region;

the gate conductor is separated from the body region by the gate dielectric layer; the shielding conductor is separated from the semiconductor layer by a shielding medium layer; the grid conductors on two sides of the upper part of the groove are separated by an isolating layer;

part of the shielding conductor is connected with the source electrode, the shielding conductor is electrically connected with the source electrode, extends from the bottom of the groove to a position between the grid conductors at two sides in the groove, the grid conductors and the shielding conductor are separated by the isolating layer, and the shielding conductor is connected with the source electrode;

a portion of the shield conductor is not connected to the source electrode, the shield conductor extending from the bottom of the trench to a region below the gate conductor on both sides of the upper portion of the trench at a position not electrically connected to the source electrode.

27. The method of claim 26 wherein the power semiconductor device comprises a first region and a plurality of alternating second and third regions divided along a length of the trench.

28. The method of claim 27, further comprising:

forming a first contact hole on the gate conductor in the first region, wherein the gate electrode is electrically connected to the gate conductor through the first contact hole; the shield conductor of the first region is not connected to the source electrode, and extends from the bottom of the trench to a region below the gate conductor on both sides of the upper portion of the trench.

29. The method of claim 27, further comprising:

and forming a second contact hole on the shield conductor in the second region, wherein the source electrode is electrically connected with the shield conductor through the second contact hole, and the shield conductor of the second region extends from the bottom of the trench to a position between the gate conductors at two sides in the trench.

30. The method of claim 27, further comprising:

forming a third contact hole on the source region in the third region and the second region, wherein the source electrode is electrically connected to the source region through the third contact hole; the shielding conductor is located below the gate conductor, the shielding conductor of the third region is not connected to the source electrode, and the shielding conductor extends from the bottom of the trench to regions below the gate conductor on both sides of the upper portion of the trench.

31. The method of any of claims 26-30, wherein a portion of the shield conductor is not connected to the source electrode, the shield conductor extending from a bottom of the trench to below the isolation layer at a location not electrically connected to the source electrode.

32. The method of claim 29, wherein the plurality of second contact holes are spaced apart by a distance of 20um to 500um along the length of the trench.

33. The method of any of claims 26-30, wherein the thickness of the shielding dielectric layer is 1000 a to 20000 a, and the thickness of the gate dielectric layer is 600 a to 3000 a.

34. The method of any one of claims 26-30, wherein the trench has a depth of 1um to 45 um.

35. The method of any of claims 26-30, wherein a distance between a top surface of the gate conductor and the first surface of the semiconductor layer is between 0um and 0.2 um.

36. The method of any one of claims 26-30, wherein a distance between a top surface of the shield conductor and the first surface of the semiconductor layer at a location where the shield conductor is electrically connected to the source electrode is between 0um and 0.5 um.

37. The method of any one of claims 26-30, wherein a distance between a top surface of the shield conductor and the first surface of the semiconductor layer is between 0.5um and 1.5um at locations where the shield conductor is not electrically connected to the source electrode.

38. The method of any of claims 26-30, wherein the gate conductor has a depth of 0.4um to 1.5 um.

39. The method of claim 27 wherein the shield conductor between the gate conductors has a length along the length of the trench of 3um to 6 um.

40. The method of claim 27, wherein a length of the shield conductor between the gate conductors along a length of the trench is the same as a length of the single second contact hole along the length of the trench.

41. The method of any one of claims 26-30, wherein a spacing between the plurality of trenches is between 2um and 9 um.

42. The method of any of claims 26-30, wherein the thickness of the spacer between the shield conductor and the gate conductor is between 0.1um and 2 um.

43. The method of any of claims 26-30, wherein the width of the shield conductor is between 0.4um and 4 um.

44. The method of any of claims 26-30, wherein the gate conductor and the shield conductor are polysilicon.

45. The method of claim 30, further comprising:

and forming a covering dielectric layer on the first surface of the semiconductor layer.

46. The method of claim 26 wherein the semiconductor layer is of a first doping type, the source region is of a first doping type, and the body region is of a second doping type, the second doping type being opposite the first doping type.

47. The method of claim 26, wherein the semiconductor layer is a drain region when the power semiconductor device is a MOS device.

48. The method as claimed in claim 26, wherein the semiconductor layer is a base region when the power semiconductor device is an IGBT device.

49. The method of claim 48, further comprising:

a buffer layer is formed between the substrate and the semiconductor layer.

50. The method of claim 26, wherein the material of the shielding dielectric layer, the gate dielectric layer and the isolation layer comprises any one of silicon dioxide, silicon nitride and a composite structure of silicon dioxide and silicon nitride, and the material of the shielding dielectric layer, the material of the gate dielectric layer and the material of the isolation layer are the same or different.

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