CN111737167B - Apparatus, method and system for high performance interconnect physical layer - Google Patents

Abstract

The present invention relates to an apparatus, method and system for a high performance interconnect physical layer. Reinitialization of a link can occur without terminating the link, wherein the link includes a transmitter and a receiver coupled to each lane of a plurality of lanes, and reinitialization of the link includes transmitting a predefined sequence on each lane.

Description

Apparatus, method and system for high performance interconnect physical layer

This application is a divisional application filed again for the divisional application 201710038141.6. The divisional application 201710038141.6 is a divisional application of the invention patent with PCT international application number PCT/US2013/032690, international application date March 15, 2013, application number 201380016998.8 entering the Chinese national phase, and titled "Method, device and system for transmitting data".

Technical Field

The present disclosure relates generally to the field of computer development, and more particularly to software development involving the coordination of constrained systems of interdependencies.

Background technique

Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic present on integrated circuit devices. Computer system configurations have necessarily evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit generally includes a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.

As a result of the higher ability to fit more processing power in a smaller package, smaller computing devices are becoming more and more popular. Smart phones, tablets, ultra-thin laptops, and other user devices are growing exponentially. However, these smaller devices rely on servers for data storage and complex processing beyond specifications. As a result, the demand for the high-performance computing market (i.e., the server space) has also increased. For example, in modern servers, there is generally not only a single processor with multiple cores, but also multiple physical processors (also known as multiple sockets) to increase computing power. But as processing power grows with the number of devices in a computing system, communication between sockets and other devices becomes more critical.

In fact, interconnects have grown from more traditional multi-drop buses that primarily handle electronic communications to comprehensive interconnect infrastructures that facilitate fast communications. Unfortunately, as there is a demand for future processors to run at even higher rates, there is a corresponding demand on the capabilities of existing interconnect infrastructures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 illustrates a simplified block diagram of a system including a series of point-to-point interconnects to connect multiple I/O devices in a computer system according to one embodiment;

FIG2 illustrates a simplified block diagram of a layered protocol stack according to an embodiment;

FIG3 illustrates an embodiment of a transaction descriptor.

FIG. 4 illustrates an embodiment of a serial point-to-point link.

FIG. 5 illustrates several embodiments of potential high performance interconnect (HPI) system configurations.

FIG. 6 illustrates an embodiment of a layered protocol stack associated with HPI.

FIG7 shows a representation of an example state machine.

FIG8 shows an example control supersequence.

FIG. 9 shows a flow diagram of an example transition to a partial-width state.

FIG. 10 illustrates an embodiment of a block diagram of a computing system including a multi-core processor.

FIG. 11 illustrates another embodiment of a block diagram of a computing system including a multi-core processor.

FIG. 12 illustrates an embodiment of a block diagram of a processor.

FIG. 13 illustrates another embodiment of a block diagram of a computing system including a processor.

14 illustrates an embodiment of a block diagram of a computing system including multiple processor sockets.

FIG. 15 illustrates another embodiment of a block diagram of a computing system.

Like reference numbers and names in the various drawings represent like elements.

Detailed ways

In the following description, many specific details are set forth in order to provide a more thorough understanding of the present invention, such as specific processor and system configuration types, specific hardware structures, specific structural and micro-architectural details, specific register configurations, specific instruction types, specific system components, specific processor pipeline stages, specific interconnect layers, specific packet/transaction configurations, specific transaction names, specific protocol exchanges, specific link widths, specific implementations and multiple examples of operations, etc. However, it will be apparent to those skilled in the art that these specific details need not necessarily be employed to implement the subject matter of the present disclosure. In other cases, very detailed descriptions of known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for the algorithms, specific firmware code, low-level interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-down and gating techniques/logic, and other specific operational details of computer systems, have been avoided in order to avoid unnecessarily obscuring the present disclosure.

Although the following embodiments may be described with reference to energy preservation, energy efficiency, etc. in a specific integrated circuit (such as a computing platform or microprocessor), other embodiments may be applied to other types of integrated circuits and logic devices. Similar techniques and principles of the embodiments described herein may be applied to other types of circuits or semiconductor devices that also benefit from these features. For example, the disclosed embodiments are not limited to server computer systems, desktop computer systems, laptop computers, Ultrabooks ^TM , but may be used in other devices, such as handheld devices, smart phones, tablet computers, other thin notebook computers, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Here, similar techniques for high-performance interconnects may be applied to increase performance (or even save power) in low-power interconnects. Embedded applications generally include microcontrollers, digital signal processors (DSPs), systems on chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but are also about software optimization for energy conservation and efficiency. As will become apparent from the following description, embodiments of the methods, apparatus, and systems described herein (whether referred to as hardware, firmware, software, or a combination thereof) may be considered critical to the future of "green technology" balanced with performance considerations.

As computing systems advance, the components therein become more complex. The complexity of the interconnect architecture used to couple and communicate between multiple components has also increased to ensure that bandwidth requirements are met for optimal component operation. Moreover, different market segments require different aspects of the interconnect architecture to suit the corresponding market. For example, servers require higher performance, while the mobile ecosystem can sometimes sacrifice overall performance for power conservation. The single purpose of most configurations remains to provide the highest possible performance with maximum power conservation. Moreover, a variety of different interconnects may potentially benefit from the subject matter described herein.

Examples such as the Peripheral Component Interconnect (PCI) Express (PCIe) interconnect fabric architecture and the Quick Path (QPI) fabric architecture can be potentially improved according to one or more principles described herein. For example, the main goal of PCIe is to enable components and devices from different manufacturers to interoperate in an open architecture, across multiple market segments, clients (desktop and mobile), servers (standard and enterprise), and embedded devices and communication devices. PCI Express is a high-performance, general-purpose I/O interconnect defined for a wide range of future computing and communication platforms. Some PCI attributes (such as its usage model, load storage architecture, and software interface) have been maintained through its revisions, and the previous parallel bus implementation has been replaced by a highly scalable full serial interface. Newer versions of PCI Express utilize point-to-point interconnects, switch-based technology, and advances in packetized protocols to achieve new levels of performance and features. Power management, quality of service (QoS), hot plug/hot swap support, data integrity, and error handling are some of the advanced features supported by PCI Express. Although the primary discussion herein is with reference to a new high performance interconnect (HPI) architecture, aspects of the invention described herein may be applied to other interconnect architectures, such as a PCIe-compatible architecture, a QPI-compatible architecture, a MIPI-compatible architecture, a high performance architecture, or other known interconnect architectures.

Referring to FIG. 1 , an embodiment of a construction consisting of a plurality of point-to-point links interconnecting a set of components is shown. System 100 includes a processor 105 and a system memory 110 coupled to a controller hub 115. Processor 105 may include any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Processor 105 is coupled to controller hub 115 via a front-end bus (FSB) 106. In one embodiment, FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial differential interconnect architecture compatible with different interconnect standards.

System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices within system 100. System memory 110 is coupled to controller hub 115 via memory interface 116. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

In one embodiment, the controller hub 115 may include a root hub, root complex, or root controller such as in a PCIe interconnect hierarchy. Examples of controller hubs 115 include chipsets, memory controller hubs (MCHs), north bridges, interconnect controller hubs (ICHs), south bridges, and root controllers/hubs. The term chipset generally refers to two physically separate controller hubs, such as a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems typically include an MCH integrated with the processor 105, and the controller 115 communicates with I/O devices in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through the root complex 115.

Here, the controller hub 115 is coupled to the switch/bridge 120 via a serial link 119. The input/output modules 117 and 121, which may also be referred to as interfaces/ports 117 and 121, may include/implement a layered protocol stack to provide communication between the controller hub 115 and the switch 120. In an embodiment, multiple devices can be coupled to the switch 120.

The switch/bridge 120 routes packets/messages from the device 125 upstream (i.e., from the hierarchical structure upward toward the root complex) to the controller hub 115, and from the processor 105 or the system memory 110 downstream (i.e., from the hierarchical structure downward away from the root controller) to the device 125. In one embodiment, the switch 120 is referred to as a logical assembly of multiple virtual PCI to PCT bridge devices. The device 125 includes any internal or external device or component to be coupled to the electronic system, such as an I/O device, a network interface controller (NIC), an add-on card, an audio processor, a network processor, a hard drive, a storage device, a CD/DVDROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Usually in PCIe language, such as a device is referred to as an endpoint. Although not specifically shown, the device 125 may include a bridge (e.g., a PCIe to PCI/PCI-X bridge) to support the traditional or other versions of the interconnection structure supported by the device or these devices.

The graphics accelerator 130 may also be coupled to the controller hub 115 via a serial link 132. In one embodiment, the graphics accelerator 130 is coupled to the MCH, which is coupled to the ICH. Thus, the switch 120 and corresponding I/O devices 125 are coupled to the ICH. The I/O modules 131 and 118 are also used to implement a layered protocol stack for communication between the graphics accelerator 130 and the controller hub 115. Similar to the MCH discussion above, the graphics controller or graphics accelerator 130 itself may be integrated within the processor 105.

Turning to FIG. 2 , an embodiment of a layered protocol stack is shown. The layered protocol stack 200 may include any form of a layered communication stack, such as a QPI stack, a PCIe stack, a next generation high performance computing interconnect (HPI) stack, or other layered stacks. In one embodiment, the protocol stack 200 may include a transaction layer 205, a link layer 210, and a physical layer 220. Interfaces (such as interfaces 117, 118, 121, 122, 126, and 131 in FIG. 1 ) may be represented as a communication protocol stack 200. Representation as a communication protocol stack may also be referred to as a module or interface that implements/includes a protocol stack.

Packets can be used to transfer information between multiple components. Packets can be formed in the transaction layer 205 and the data link layer 210 to carry information from a transmitting component to a receiving component. As the transmitted packets flow through the other layers, they are extended with additional information for processing the packets at those layers. The reverse process occurs on the receiving side, where packets are transformed from their physical layer 220 representation to a data link layer 210 representation, and finally (for transaction layer packets) to a form that can be processed by the transaction layer 205 of the receiving device.

In one embodiment, the transaction layer 205 can provide an interface between the processing core of the device and the interconnect architecture, such as the data link layer 210 and the physical layer 220. In this regard, the primary responsibilities of the transaction layer 205 can include the assembly and disassembly of packets (i.e., transaction layer packets, i.e., TLPs). The transaction layer 205 can also manage credit-based flow control of the TLPs. In some implementations, in other examples, split transactions can be utilized, i.e., transactions on requests and transactions on responses are separated in time, allowing the link to carry other traffic while the target device collects data for the response.

Credit-based flow control can be used to implement virtual channels and networks that utilize interconnected structures. In one example, a device can advertise an initial amount of credits for each receive buffer in the transaction layer 205. An external device at the opposite end of the link (such as the controller hub 115 in FIG. 1 ) can count the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction is sent. When a response is received, the number of credits is restored. An example of the advantage of this credit scheme is that, among other potential advantages, if the credit limit is not encountered, the delay in the return of credits does not affect performance.

In one embodiment, the four transaction address spaces may include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory mapped location. In one embodiment, memory space transactions can use two different address formats, such as a short address format (such as a 32-bit address) or a long address format (such as a 64-bit address). Configuration space transactions can be used to access the configuration space of each device connected to the interconnect. Transactions to the configuration space may include read requests and write requests. Message space transactions (or simply messages) may also be defined to support in-band communication between interconnect agents. Therefore, in an example embodiment, the transaction layer 205 can assemble a packet header/payload 206.

Referring quickly to FIG. 3 , an example embodiment of a transaction layer packet descriptor is shown. In one embodiment, a transaction descriptor 300 may be a mechanism for carrying transaction information. In this regard, the transaction descriptor 300 supports identification of transactions in the system. Other potential uses include tracking modifications to the default transaction order and the association of transactions with channels. For example, the transaction descriptor 300 may include a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the example shown, the global identifier field 302 is described as including a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique to all outstanding requests.

According to one implementation, the local transaction identifier field 308 is a field generated by the requesting agent and can be unique to all outstanding requests that the requesting agent requires to be completed. Moreover, in this example, the source identifier 310 uniquely identifies the requestor agent within the interconnect hierarchy. Thus, the local transaction identifier 308 field, together with the source ID 310, provides a global identification of a transaction within the hierarchy domain.

The attribute field 304 specifies the characteristics and relationships of the transaction. In this regard, the attribute field 304 may be used to provide additional information that allows the default handling of the transaction to be modified. In one embodiment, the attribute field 304 includes a priority field 312, a reserved field 314, an order field 316, and a no-snoop field 318. Here, the priority subfield 312 may be modified by the initiator to assign a priority to the transaction. The reserved attribute field 314 is reserved for future use or for use defined by the manufacturer. The reserved attribute field may be used to implement a possible use model that uses priority or security attributes.

In this example, the sorting attribute field 316 is used to provide optional information that can modify the sorting type of the default sorting rule. According to an example implementation, a sorting attribute of "0" indicates that the default sorting rule is to be applied, wherein a sorting attribute of "1" indicates unconstrained sorting, wherein write operations can pass through write operations in the same direction, and read operations can pass through write operations in the same direction. The listening attribute field 318 is used to determine whether the transaction is listened. As shown in the figure, the channel ID field 306 identifies the channel with which the transaction is associated.

Returning to the discussion of FIG. 2 , the link layer 210 (also referred to as the data link layer 210) may act as an intermediate stage between the transaction layer 205 and the physical layer 220. In one embodiment, the responsibility of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components on a link. One side of the data link layer 210 accepts the TLPs assembled by the transaction layer 205, applies a packet sequence identifier 211 (i.e., an identification number or packet number), calculates and applies an error detection code (i.e., CRC 212), and submits the modified TLP to the physical layer 220 for transmission across the physical components to an external device.

In one example, the physical layer 220 includes a logical sub-block 221 and an electrical sub-block 222 to physically send packets to an external device. Here, the logical sub-block 221 is responsible for the "digital" functions of the physical layer 221. In this regard, the logical sub-block may include a transmit portion and a receive portion, the transmit portion being used to prepare outgoing information for transmission by the physical sub-block 222, and the receive portion being used to identify and prepare the received information before passing it to the link layer 210.

Physical block 222 includes a transmitter and a receiver. The transmitter is provided by a logical sub-block 221 with symbols, and the transmitter serializes the symbols and transmits them outward to an external device. The receiver is provided with serialized symbols from an external device and converts the received signal into a bit stream. The bit stream is deserialized and provided to the logical sub-block 221. In an example embodiment, an 8b/10b transmission code is used, in which 10-bit symbols are transmitted/received. Here, special symbols are used to frame the packets with multiple frames 223. In addition, in an example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As described above, although the transaction layer 205, link layer 210, and physical layer 220 are discussed with reference to a specific embodiment of a protocol stack (such as a PCIe protocol stack), the layered protocol stack is not limited thereto. In fact, any layered protocol may be included/implemented, and the layered protocol may employ the features discussed herein. As an example, a port/interface represented as a layered protocol may include: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for serializing packets, i.e., a link layer; and a third layer for transmitting packets, i.e., a physical layer. As a specific example, a high performance interconnect layered protocol as described herein is used.

Next, with reference to FIG. 4 , an example embodiment of a serial point-to-point configuration is shown. A serial point-to-point link may include any transmit path for transmitting serial data. In the illustrated embodiment, the link may include two, low-voltage, differentially driven signal pairs: a transmit pair 406/411 and a receive pair 412/407. Thus, device 405 includes transmit logic 406 for transmitting data to device 410 and receive logic 407 for receiving data from device 410. In other words, two transmit paths (i.e., paths 416 and 417) and two receive paths (i.e., paths 418 and 419) are included in some implementations of the link.

A transmit path refers to any path for transmitting data, such as a transmission line, copper wire, optical line, wireless communication channel, infrared communication link, or other communication path. A connection between two devices (such as device 405 and device 410) is called a link, such as link 415. A link can support one lane, each lane representing a set of differential signal pairs (one pair for transmission and one pair for reception). To scale bandwidth, a link can aggregate multiple lanes labeled by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

A differential pair may refer to two transmission paths, such as lines 416 and 417, for transmitting differential signals. As an example, when line 416 switches from a low voltage level to a high voltage level (i.e., a rising edge), line 417 drives from a high logic level to a low logic level (i.e., a falling edge). Differential signals potentially demonstrate better electronic characteristics, such as better signal integrity, i.e., cross-coupling, voltage overshoot/undershoot, oscillation, and other example advantages. This allows for better timing windows, thereby allowing for faster transmission frequencies.

In one embodiment, a new high performance interconnect (HPI) is provided. HPI may include a next generation cache coherent link-based interconnect. As an example, HPI may be used in a high performance computing platform such as a workstation or server, including in a system where PCIe or another interconnect protocol is generally used to connect processors, accelerators, I/O devices, etc. However, HPI is not limited to this. Instead, HPI may be used in any system or platform described herein. Moreover, the individual concepts developed may be applied to other interconnects and platforms, such as PCIe, MIPI, QPI, etc.

To support multiple devices, in an example implementation, HPI may include an instruction set architecture (ISA) agnostic (i.e., HPI can be implemented in multiple different devices). In another case, HPI can also be used to connect high-performance I/O devices, not just processors or accelerators. For example, a high-performance PCIe device can be coupled to HPI through an appropriate conversion bridge (i.e., HPI to PCIe). In addition, HPI connections can be used by many HPI-based devices (such as processors) in various ways (e.g., star, ring, mesh, etc.). Figure 5 shows an example implementation of multiple potential multi-slot configurations. As shown, a dual-slot configuration 505 may include two HPI links; however, in other implementations, one HPI link may be used. For larger topologies, any configuration can be used as long as an identifier (ID) can be assigned and there is a certain form of virtual path and other additional or alternative features. As shown, in an example, a four-slot configuration 510 has an HPI link from each processor to each other processor. But in the eight-slot implementation shown in configuration 515, not every slot is directly connected to each other through an HPI link. However, if there is a virtual path or channel between multiple processors, the configuration is supported. The range of supported processors includes 2-32 processors in a local domain. In other examples, higher numbers of processors can be achieved by using multiple domains or other interconnects between node controllers.

The HPI architecture includes the definition of a layered protocol architecture, which in some examples includes protocol layers (coherent, incoherent, and optionally other memory-based protocols), routing layers, link layers, and physical layers. Moreover, in other examples, HPI may also include enhancements related to power managers (such as power control units (PCUs)), design for testing and debugging (DFT), error handling, registers, and security. Figure 5 shows an embodiment of an example HPI layered protocol stack. In some implementations, at least some of the layers shown in Figure 5 may be optional. Each layer handles its own level of information granularity or amount of information (protocol layers 605a, b handle packets 630, link layers 610a, b handle flits 635, and physical layers 605a, b handle phase bits (phit) 640). Note that in some implementations, based on the implementation, a packet may include multiple partial flits, a single flit, or multiple flits.

As a first example, the width of the phase bits 640 includes a 1-to-1 mapping of link width to bits (e.g., a 20-bit link width includes a 20-bit phase bit, etc.). Flyers may have larger sizes, such as 184, 192, or 200 bits. Note that if the phase bits 640 are 20 bits wide and the size of the flyer 635 is 184 bits, a fractional number of phase bits 640 are required to transmit one flyer 635 (e.g., 9.2 phase bits at 20 bits to transmit a 184-bit flyer 635, or 9.6 phase bits at 20 bits to transmit a 192-bit flyer, in other examples). Note that the basic link width at the physical layer may vary. For example, the number of lanes in each direction may include 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, etc. In one embodiment, the link layer 610a,b can embed multiple different transactions in a single flyer, and one or more headers (e.g., 1, 2, 3, 4) can be embedded in the flyer. In one example, HPI divides the header into corresponding slots so that multiple messages in the flyer go to different nodes.

In one embodiment, the physical layer 605a, b can be responsible for quickly transmitting information on a physical medium (electrical or optical, etc.). The physical link can be point-to-point between two link layer entities (such as layers 605a and 605b). The link layer 610a, b can abstract the physical layer 605a, b from the upper layer and provide the ability to reliably transmit data (and requests) and manage flow control between two directly connected entities. The link layer can also be responsible for virtualizing the physical channel into multiple virtual channels and message classes. The protocol layer 620a, b relies on the link layer 610a, b to map the protocol message to the appropriate message class and virtual channel before handing it over to the physical layer 605a, b for transmission across the physical link. In other examples, the link layer 610a, b can support multiple messages, such as request, listen, response, write back, non-coherent data.

As shown in FIG6 , the physical layer 605a, b (or PHY) of HPI can be implemented above the electrical layer (i.e., the electrical conductors connecting two components) and below the link layer 610a, b. The physical layer and corresponding logic can reside on each agent and connect the link layers on two agents (A and B) that are separated from each other (e.g., on devices on either side of the link). The local and remote electrical layers are connected by a physical medium (e.g., wires, conductors, optical media, etc.). In one embodiment, the physical layer 605a, b has two main phases, initialization and operation. In the initialization device, the connection is not transparent to the link layer, and the signaling can include a combination of timed status and handshake events. During operation, the connection is transparent to the link layer, and the signaling has a certain speed, where all lanes operate together as a single link. During the operation phase, the physical layer transmits slices from agent A to agent B, and from agent B to agent A. The connection is also called a link, and certain physical aspects including media, width, and speed are abstracted from the link layer, while exchanging currently configured slices and control/status (e.g., width) with the link layer. The initialization phase includes secondary phases, such as polling and configuration. The operation phase also includes secondary phases (e.g., link power management state).

In one embodiment, the link layer 610a, b can be implemented to provide reliable data transmission between two protocols or routing entities. The link layer can abstract the physical layer 605a, b from the protocol layer 620a, b, and can be responsible for the flow control between the two protocol agents (A, B), and provide virtual channel services to the protocol layer (message class) and the routing layer (virtual network). The interface between the protocol layer 620a, b and the link layer 610a, b can generally be at the packet level. In one embodiment, the minimum transmission unit at the link layer is called a flyer, which is a specified number of bits, such as 192 bits or some other amount. The link layer 610a, b relies on the physical layer 605a, b to frame the transmission units (phase bits) of the physical layer 605a, b into the transmission units (flyers) of the link layer 610a, b. In addition, the link layer 610a, b can be logically divided into two parts, a sender and a receiver. A sender/receiver pair on one entity can be connected to a receiver/sender pair on another entity. Flow control is usually performed on the basis of both flyers and packets. It is also possible to perform error detection and correction on a fly-chip level basis.

In one embodiment, the routing layer 615a, b can provide a flexible and distributed method to route HPI transactions from source to destination. Since the routing algorithms of multiple topologies can be specified by the programmable routing table at each router (the programming in one embodiment is performed by firmware, software, or a combination thereof), the scheme is flexible. The routing function can be distributed; routing can be completed by a series of routing steps, and each routing step is defined by a lookup of a table at any one of the source router, intermediate router, or destination router. The lookup at the source can be used to inject the HPI packet into the HPI structure. The lookup at the intermediate router can be used to route the HPI packet from the input port to the output port. The lookup at the destination port can be used to target the destination HPI protocol agent. Note that in some implementations, the routing layer can be thin because the routing table and the routing algorithm therefrom are not specifically defined by the specification. This allows flexibility and a variety of usage models, including flexible platform structure topology logic to be defined by the system implementation. The routing layer 615a,b relies on the link layer 610a,b to provide the use of up to three (or more) virtual networks (VNs) - in one example, two deadlock-free VNs are used: VN0 and VN1, and several message classes are defined in each virtual network. In other features and examples, a shared adaptive virtual network (VNA) can be defined in the link layer, but the adaptive network may not be directly exposed to routing concepts because each message class and virtual network can have dedicated resources and guaranteed progress.

In some implementations, HPI can use an embedded clock. The clock signal can be embedded in the data transmitted using the interconnect. Because the clock signal is embedded in the data, different and dedicated clock lanes can be omitted. This can be useful, for example, because it can allow more pins of a device to be dedicated to data transmission, especially in systems where pin space is at a premium.

A link can be established between two agents on either side of the interconnect. The agent sending data can be a local agent, and the agent receiving data can be a remote agent. Both agents can use state machines to manage various aspects of the link. In one embodiment, the physical layer data path can transmit multiple flying chips from the link layer to the electrical front end. In one implementation, the control path includes a state machine (also called a link training state machine or the like). The actions of the state machine and the exit from the state can depend on internal signals, timers, external signals or other information. In fact, some states (such as a few initialization states) may have a timer to provide a timeout value for exiting a state. Note that in some embodiments, detection refers to detecting events on both legs of a lane, but not necessarily at the same time. However, in other embodiments, detection refers to detecting events by the referenced agent. As an example, debounce refers to the continuous assertion of a signal. In one embodiment, HPI supports operation in the case of non-functional lanes. Here, lanes can be reduced at a specific rate.

The states defined in the state machine may include reset states, initialization states, and operational states, among other categories and subcategories. In one example, some initialization states may have auxiliary timers that are used to exit the state upon a timeout (particularly a suspension due to failure to make progress in the state). Suspension may include updating registers, such as a state register. Some states may also have (multiple) main timers that are used to time the main functions within the state. In other examples, other states may be defined so that internal or external signals (such as a handshake protocol) drive the transition from a state to another state.

The state machine may also support debugging through single step, freeze initialization ports, and use of testers. Here, state exits may be postponed/held until debug software is ready. In some cases, exits may be postponed/held until a secondary times out. In one embodiment, actions and exits may be based on the exchange of training sequences. In one embodiment, the link state machine is to run in the local agent clock domain, and transitions from one state to the next are to be coordinated with transmitter training sequence boundaries. A state register may be used to reflect the current state.

FIG. 7 shows a representation of at least a portion of a state machine used by an agent in an example implementation of HPI. It should be understood that the states included in the state table of FIG. 7 include a non-exhaustive list of possible states. For example, some transitions are omitted to simplify the schematic. Likewise, some states may be combined, split, or omitted, while other states may be added. Such states may include:

Event Reset State : Enters a hot or cold reset event. Restores default values. Initializes counters (e.g., synchronizes counters). May exit to another state, such as another reset state.

Timed Reset State : A timed state with an in-band reset. May drive a predefined electrical ordered set (EOS) so that a remote receiver can also detect the EOS and enter a timed reset. The receiver has a lane to hold the electrical settings. May exit to a proxy to calibrate the reset state.

Calibration Reset State : Calibration is performed with no signaling on the track (e.g., receiver calibration state) or with the driver turned off. Can be a predetermined amount of time in a timer-based state. Can set the speed of operation. Can act as a wait state when the port is not enabled. Can include a minimum dwell time. Receiver adjustments or staggering can occur based on design. Can exit to the receiver detection state after timeout and/or calibration completion.

Receiver Detection State : Detects the presence of a receiver on the lane. May look for receiver termination (e.g., receiver pull-down insertion). May exit to the Calibration Reset State if a specified value is set or another specified value is not set. May exit to the Transmitter Calibration State if a receiver is detected or a timeout is reached.

Transmitter Calibration State : Used for transmitter calibration. May be a timed state assigned for transmitter calibration. May include signaling on the lane. May continuously drive EOS, such as an Electrical Idle Exit Ordered Set (or EIEIOS). May exit to the Comply state upon calibration completion or timer expiration. May exit to the Transmitter Detect state if a counter has expired or a secondary timeout has occurred.

Transmitter Detect State : Qualify for valid signaling. Can be a handshake state where the agent completes an action based on remote agent signaling and exits to the next state. The receiver can qualify for valid signaling from the transmitter. In one embodiment, the receiver looks for wake-up detection and if debounced on one or more lanes, looks for it on other lanes. The transmitter drives a detection signal. In response to debounce and/or timeout completed for all lanes, or if debounce on all lanes is not completed and there is a timeout, it can exit to the polling state. Here, one or more monitoring lanes can remain awake to debounce the wake-up signal. If debounced, other lanes may be debounced. This can achieve power savings in low power states.

Polling state : receiver adapts, initializes drift buffers, and locks on bits/bytes (e.g., identifier symbol boundaries). Lanes may be deskewed. The remote agent may exit to the next state (e.g., link width state) in response to an acknowledgement message. Polling may additionally include a training sequence lock by locking to EOS, and a training sequence header. The lane-to-lane offset at the remote transmitter may be capped to a first length for maximum speed, and a second length for low speed. Deskew may be performed in low mode as well as in operating mode. The receiver may have a specific maximum value to deskew lane-to-lane offsets, such as 8, 16, or 32 offset intervals. Receiver actions may also include delay fixes. In one embodiment, receiver actions may be completed upon successful deskew of a valid lane map. In one example, a successful handshake may be achieved when several consecutive training sequence headers are received with acknowledgement and several training sequences with acknowledgement are transmitted after the receiver has completed its actions.

Link Width State : The agent transmits the final lane map to the remote transmitter. The receiver receives the information and decodes it. The receiver can record the configured lane map in a structure after a checkpoint of the previous lane map value in a second structure. The receiver can also respond with an acknowledgment ("ACK"). An in-band reset can be initiated. As an example, the first state is used to initiate an in-band reset. In one embodiment, the next state, such as the flying chip configuration state, is exited in response to the ACK. Moreover, before entering the low power state, if the frequency of occurrence of the wake-up detection signal falls below a specified value (e.g., 1 per unit interval (UI), such as 4K UI), a reset signal can also be generated. The receiver can maintain the current lane map and the previous lane map. The transmitter can use different lane groups based on training sequences with different values. In some embodiments, the lane map may not modify some state registers.

Flyer Lock Configuration State : Entered by the transmitter, but this state is considered exited when both the transmitter and receiver have exited to the Block Link State or other link state (i.e., a secondary timeout is pending). In one embodiment, the transmitter exits to the link state, including the start of data sequence (SDS) and training sequence (TS) boundary after receiving a planetary alignment signal. Here, the receiver exit can be based on receiving an SDS from a remote transmitter. This state can be a bridge from the agent to the link state. The receiver identifies the SDS. If an SDS is received after initializing the descrambler, the receiver can exit to the Block Link State (BLS) (or control window). If a timeout occurs, it can exit to the Reset state. The transmitter drives the lane with a configuration signal. The transmitter can also exit to the Reset state, the BLS state, or other states based on multiple conditions or timeouts.

Transmit Link State : A link state. Flyers are sent to the remote agent. Can be entered from the Block Link State and returned to the Block Link State on an event (such as a timeout). The transmitter transmits a flyer. The receiver receives a flyer. Can also exit to a low power link state. In some implementations, the Transmit Link State (TLS) may also be referred to as the L0 state.

Blocking Link State : A link state. The transmitter and receiver operate in a unified manner. It can be a timed state during which link layer flyers are held while physical layer information is transmitted to the remote agent. It can exit to a low power link state (or other link state based on design). In one embodiment, the blocking link state (BLS) occurs periodically. The period is called the BLS interval and can be timed and different between low speed and operating speed. Note that the link layer can be periodically prevented from sending flyers so that a certain length of physical layer control sequence can be sent, such as during a transmit link state or a partial width transmit link state. In some implementations, the blocking link state (BLS) can be referred to as the L0 control (or L0c) state.

Partial Width Transmit Link State : Power can be saved by entering a partial width state. In one embodiment, asymmetric partial width refers to two directional links with different widths in each direction that can be supported in some designs. An example of an initiator such as a transmitter is shown in the example of FIG. 9, and the initiator sends a partial width indication to enter a partial width transmit link state. Here, while transmitting on a link with a first width, a partial width indication is sent to convert the link to transmit at a second new width. A mismatch may cause a reset. Note that the speed may not change, but the width may change. Therefore, the flyer may be sent with a different span. It may be logically similar to the transmit link state; since there is a smaller width, it may take longer to transmit the flyer. It is possible to exit to other link states, such as exiting to a low power link state based on specific received and transmitted messages, or exiting to a partial width transmit link state or a link blocking state based on other events. In one embodiment, the transmitter port can turn off idle lanes in an interleaved manner to provide better signal integrity (i.e., noise mitigation), as shown in the timing diagram. Here, during the time period when the link width is changing, non-retry-able flyers, such as null flyers, may be used. The corresponding receiver may discard these null flyers and close the idle lanes in an interleaved manner. Note that the state and associated state registers may remain unchanged. In some implementations, the partial width transmit link state may be referred to as the partial L0 (or L0p) state.

Exiting the Partial Width Transmit Link State : Exiting the partial width state. In some implementations, the blocked link state may or may not be used. In one embodiment, the transmitter initiates the exit by sending a partial width exit pattern on idle lanes in order to train and de-skew them. As an example, the exit pattern begins with EIEOS, which is detected and de-bounced to signal that the lane is ready to begin entering the full transmit link state, and may end with SDS or a fast training sequence (FTS) on an idle lane. Any failure during the exit sequence (receiver action, such as de-skew that was not completed before the timeout) stops the transmission of flying chips to the link layer and insists on a reset, which is handled by resetting the link when the next blocked link state occurs. SDS may also initialize the scrambler/descrambler on multiple lanes to appropriate values.

Low Power Link State : is a lower power state. In one embodiment, it is lower power than the partial width link state because signaling in this embodiment is stopped on all lanes and in both directions. The transmitter can request a low power link state using the blocking link state. Here, the receiver can decode the request and respond with an ACK or NAK; otherwise a reset can be triggered. In some implementations, the low power link state can be referred to as the L1 state.

In some implementations, state transitions can be facilitated to allow states to be bypassed, for example, when state actions for a state (such as specific calibration and configuration) have been completed. Previous state results and configurations of a link can be stored and reused in subsequent initialization and configuration of the link. The corresponding state can be bypassed instead of repeating such configuration and state actions. However, traditional systems that implement state bypasses typically implement complex designs and expensive validation escapes. In one example, instead of using traditional bypasses, HPI can use short timers in specific states, such as when state actions do not need to be repeated. This can potentially allow more uniform and synchronized state machine transitions, as well as other potential advantages.

In one example, a software-based controller (e.g., through an external control point at the physical layer) can enable a short timer for one or more specific states. For example, for a state whose actions have been executed and stored, the state can be short-timed to facilitate a quick exit from the state to the next state. However, if the previous state action fails or cannot be applied during the short timer, a state exit can be performed. Moreover, the controller can disable the short timer, such as when the state action should be re-executed. A long, or default, timer can be set for each corresponding state. If the action in the state cannot be completed within the long timer, a state exit can occur. The long timer can be set to a reasonable duration to allow completion of the state action. On the contrary, in other examples, the short timer can be much shorter, making it particularly impossible to perform a state action in some cases by referring back to a previously executed state action.

In some cases, during link initialization (or reinitialization), as the agent advances through the state machine toward the operational link state, one or more faults or state exits that reset the state (e.g., reset to a reset state or other state) may occur. In practice, the initialization of the link can cycle through one or more states without completing the initialization and entering the link state. In an example, a count can be kept for the number of invalid cycles in the state transition within the link initialization. For example, each time the initialization returns to the reset state without reaching the link state, the counter can be incremented. Once the link successfully enters the link state, the counter can be reset for the link. Such a counter can be maintained by agents on both sides of the link. Moreover, a threshold can be set, such as by using a software-based controller using one or more external control points. When the count of invalid cycles meets (or exceeds) the defined threshold, the initialization of the link can be suspended (e.g., set and maintained at or before the reset state). In some implementations, in order to restart the initialization and release the initialization from the suspended state, a software-based controller can trigger the restart or reinitialization of the link. In some cases, a software-based tool can analyze the nature of the suspended initialization and perform diagnostics, set register values, and perform other operations to prevent further cycles of initialization. Indeed, in some implementations, the controller may set a higher counter threshold or even overwrite the counter in conjunction with restarting a suspended link initialization, among other examples.

In some implementations of HPI, supersequences may be defined, each supersequence corresponding to a corresponding state or entry/exit to/from the corresponding state. A supersequence may include a repeating sequence of data sets and symbols. In some cases, in other examples, the sequence may be repeated until the completion of a state or state transition, or the transmission of a corresponding event. In some cases, the repeating sequence of a supersequence may be repeated according to a defined frequency, such as a defined number of unit intervals (UI). The unit interval (UI) may correspond to a time interval for transmitting a single bit on a link or system track. In some implementations, a repeating sequence may start with an electrical ordered set (EOS). Thus, it is expected that instances of EOS may be repeated according to a predefined frequency. Such an ordered set may be implemented as a defined 16-byte code that may be represented in hexadecimal format, as well as other examples. In one example, the EOS of a supersequence may be EIEIOS. In one example, EIEOS may be similar to a low-frequency clock signal (e.g., a predefined number of repetitions of FF00 or FFF000 hexadecimal symbols, etc.). A predefined data set may follow the EOS, such as a predefined number of training sequences or other data. In other examples, such a supersequence may be used in state transitions including link state transitions and initialization.

In some implementations of the interconnect, such as in QPI, the termination of the serial data link can be turned on and off, such as when the link is reset or initialized. This method can introduce complexity and time into the initialization of the link. In some implementations of HPI, the termination of the link can be maintained during the reset and reinitialization of the link. Moreover, HPI can allow hot plugging of devices. When another device is introduced, either by hot plugging or otherwise, the voltage characteristics of the lane to which the new remote agent is added will change. The local agent can sense these changes in the lane voltage to detect the presence of the remote agent and cause the initialization of the link. State machine states and timers can be defined in the state machine to coordinate the detection, configuration, and initialization of the link without termination.

In one implementation, HPI can support reinitialization on in-band reset without changing the termination value by screening the lane for incoming signaling by the receiving agent. Signaling can be used to identify good lanes. As an example, the lane can be screened for any of a set of predefined signals to be sent by the transmitter device to facilitate recovery and configuration of the link. In one example, a supersequence can be defined corresponding to one or more initialization or reinitialization tasks. The predefined sequence can include EIEOS, followed by additional sequence data. In some cases, as each device on either side of the lane becomes active, the device can begin sending a supersequence corresponding to a specific initialization state, and so on. In one embodiment, two types of pin resets can be supported; power-on (i.e., "cold") resets and hot resets. A reset initiated by software or originated on one agent (in the physical layer or another layer) can be transmitted in-band to another agent. However, because an embedded clock is used, an in-band reset can be handled by transmitting to another agent using an ordered set (such as a specific electrical ordered set, i.e., EIOS).

Ordered sets may be sent during initialization, and PHY control sequences (or "block link state") may be sent after initialization. The block link state may prevent the link layer from sending flyers. As another example, link layer traffic may be prevented from sending a small number of NULL flyers that are discarded at the receiver.

As described above, in one embodiment, initialization can be done with an initial low speed followed by a fast initialization. Initialization at low speed uses default values for registers and timers. Then, the software uses the low-speed link to set registers, timers, and electrical parameters, and clears the calibration arm board signal (semaphore) to pave the way for fast initialization. As an example, in other possible examples, initialization can consist of states or tasks such as Reset, Detect, Polling, and Configuration.

In one example, a link layer blocking control sequence (i.e., blocking link state (BLS) or L0c state) may include a timed state during which link layer flybacks are held while PHY information is transmitted to a remote agent. Here, the transmitter and receiver may start a blocking control sequence timer. And upon expiration of the timer, the transmitter and receiver may exit the blocking state and may take other actions, such as exiting to a reset state, exiting to a different link state (or other state), including a state that allows flybacks to be sent across the link.

In an embodiment, link training may be provided, including sending one or more of a scrambled training sequence, an ordered set, and a control sequence, such as in conjunction with a predefined supersequence. The training sequence symbols may include one or more of a header, a reserved portion, a target delay, a pair number, a physical lane map code reference lane or a group of lanes, and an initialization state. In an embodiment, the header may be sent as an ACK or a NAK, among other examples. As an example, the training sequence may be sent as part of a supersequence and may be scrambled.

In one embodiment, ordered sets and control sequences are not scrambled or interleaved and can be sent identically, simultaneously and completely on all lanes. Valid reception of an ordered set can include checking at least a portion of an ordered set (or all ordered sets of multiple partial ordered sets). An ordered set can include an electrical ordered set (EOS), such as an electrical idle ordered set (EIOS) or an EIEOS. A supersequence can include a start of data sequence (SDS) or a fast training sequence (FTS). Such sets and control supersequences can be predefined and can have any pattern or hexadecimal representation and any length. For example, ordered sets and supersequences can be 8 bytes, 16 bytes, 32 bytes, etc. in length. As an example, during exiting a partial width transmit link state, an FTS can be additionally used for fast bit locking. Note that the FTS definition can be defined by lane and a rotated version of the FTS can be used.

In one embodiment, the supersequence may include inserting an EOS (such as EIEOS) into the training sequence stream. In one embodiment, when signaling begins, multiple lanes are powered up in an interleaved manner. However, this may cause the initial supersequence to be truncated at the receiver on some lanes. However, the supersequence may be repeated at short intervals (e.g., approximately one thousand unit intervals, (or ~1 KUI)). The training supersequence may additionally be used for one or more of correction, configuration, and for transmitting initialization targets, lane maps, etc. EIEOS may be used for one or more of: transitioning a lane from an inactive state to an active state, screening good lanes, identifying symbols and TS boundaries, and other examples.

Turning to FIG8 , a representation of an example supersequence is shown. For example, an exemplary detection supersequence 805 may be defined. The detection supersequence 805 may include a single EIEOS (or other EOS) followed by a repeating sequence of a predefined number of instances of a particular training sequence (TS). In one example, the EIEOS may be sent, followed immediately by seven repeating instances of the TS. When the last of the seven TSs is sent, the EIEOS may be sent again followed by seven additional instances of the TS, and so on. The sequence may be repeated according to a specific predefined frequency. In the example of FIG8 , the EIEOS may be repeated on the lane every thousand UIs (~1 KUI), followed by the remainder of the detection supersequence 805. The receiver may monitor the lane for repeated detection supersequences 805, and upon confirming the supersequence 805, infer that a remote agent is present, has been added (e.g., hot-plugged) to the lane, has been awakened, or is being reinitialized, etc.

In another example, another supersequence 810 may be defined to indicate a polling, configuration, or loopback condition or state. For the example detection supersequence 805, the lanes of the link may be monitored by the receiver for such a Poll/Config/Loop supersequence 810 to identify a polling state, a configuration state, or a loopback state or condition. In one example, the Poll/Config/Loop supersequence 810 may begin with an EIEOS, followed by a predefined number of repeated instances of the TS. For example, in one example, the EIEOS may be followed by thirty-one (31) instances of the TS, where the EIEOS is repeated approximately every four thousand UIs (e.g., ~4KUI).

Moreover, in another example, a partial width transmit state (PWTS) exit supersequence 815 may be defined. In one example, the PWTS exit supersequence may include an initial EIEOS to be repeated so that the lane is pre-repeated before the first empty sequence in the supersequence is sent. For example, the sequence to be repeated in the supersequence 815 may start with EIEOS (to be repeated approximately every 1 KUI). Moreover, a fast training sequence (FTS) may be used instead of other training sequences (TS), and the FTS is configured to help faster bit lock, byte lock, and deskew. In some implementations, the FTS may be descrambled to help bring the idle lane back to active as quickly and non-intrusively as possible. As other supersequences enter the link transmit state, the supersequence 815 may be interrupted and ended by sending the start of a data sequence (SDS). Moreover, a partial FTS (FTSp) may be sent to help synchronize the new lane to the active lane, such as by allowing multiple bits to be subtracted (or added) to the FTSp, and other examples.

Supersequences (such as detection supersequence 805 and polling/configuration/loop supersequence 810, etc.) may potentially be sent during initialization or reinitialization of a link. In some cases, a receiver, upon receiving and detecting a particular supersequence, may respond by echoing the same supersequence to a transmitter on a lane. Receipt and confirmation of a particular supersequence by a transmitter and receiver may act as a handshake to confirm a state or condition transmitted by a supersequence. For example, such as a handshake (e.g., using detection supersequence 805) may be used to identify the reinitialization of a link. In other examples, in another example, this handshake may be used to indicate the end of a power-on reset or low-power state, causing the corresponding lane to be brought back. For example, the end of a power-on reset may be identified by a handshake between a transmitter and a receiver that each transmits a detection supersequence 805.

Among other events, in another example, lanes may be monitored for super sequences, which lanes may use to screen lanes for detection, wakeup, state exit and entry. The predefined and predictable nature and form of super sequences may further be used to perform such initialization tasks as bit lock, byte lock, anti-bounce, descramble, deskew, adapt, delay fixation, negotiated delay, and other potential uses. In fact, lanes may be monitored substantially continuously for these events to accelerate the system's ability to react to or handle such conditions.

In the case of anti-bounce, transients may be introduced on the lane as a result of various conditions. For example, the addition or power-up of a device may introduce transients on the lane. In addition, voltage irregularities may be present on the lane due to poor lane quality or electrical faults. In some cases, a "bounce" on the lane may produce an erroneous determination, such as an erroneous EIEOS. However, in some implementations, although a supersequence may start with an EIEOS, a defined supersequence may also include an additional data sequence and a defined frequency at which the EIEOS will repeat. As a result, even if an erroneous EIEOS appears on the lane, a logic analyzer at the receiver may determine that the EIEOS is an erroneous determination by the data exceeding the erroneous EIEOS. For example, if the expected TS or other data does not follow the EIEOS, or the EIEOS does not repeat within a specific one of the multiple predefined frequencies of one of the predefined supersequences, the receiver logic analyzer may fail the confirmation of the received EIEOS. False determinations may also be produced as bounces occur at startup when a device is added to the lane. For example, after a device is added to a set of lanes, the device may begin sending detection supersequences 705 to alert the other side of the link of its presence and begin initializing the link. However, transients introduced on the lanes may corrupt the initial EIEOS, TS instances, and other data of the supersequence. However, in other examples, a logic analyzer on the receiving device may continue to monitor these lanes and identify EIEOS sent by the new device in repeated detection supersequences 705.

In some implementations, the HPI link can operate at multiple speeds implemented by the embedded clock. For example, a slow mode can be defined. In some instances, the slow mode can be used to help implement the initialization of the link. The calibration of the link can include a software-based controller providing logic to set various calibrated features of the link, including which lanes the link is to use, the configuration of the lanes, the operating speed of the link, synchronization of the lanes and agents, deskew, target delay, and other possible features. Such a software-based controller can use external control points to add data to the physical layer registers to control various aspects of the physical layer facilities and logic.

The operating speed of the link can be much faster than the actual operating speed of the software-based controller used in the initialization of the link. In other examples, the slow mode can be used to allow the use of such a software-based controller, such as during initialization or re-initialization of the link. The slow mode can be applied on the lanes linking the receiver and transmitter, such as when the link is turned on, initialized, reset, etc., to help implement calibration of the link.

In one embodiment, the clock may be embedded in the data so there is no separate clock lane. The flyer sent on the lane may be scrambled to implement clock recovery. As an example, the receiver clock recovery unit may pass the sampling clock to the receiver (i.e., the receiver recovers the clock from the data and uses it to sample the incoming data). The receiver in some implementations continuously adapts to the incoming bit stream. By embedding the clock, pinouts can potentially be reduced. However, embedding the clock in the in-band data can change the way in-band resets are implemented. In one embodiment, a blocking link state (BLS) can be used after initialization. Among other considerations, resets can also be implemented using an electrical ordered set super sequence during initialization. The embedded clock can be shared among multiple devices on the link, and the common operating clock can be set during calibration and configuration of the link. For example, an HPI link can reference a common clock with a drift buffer. Compared with the elastic buffer used in a non-common reference clock, this implementation can achieve lower latency and other potential advantages. Moreover, the reference clock distribution segment can be matched to within specified boundaries.

As described above, the HPI link can operate at multiple speeds, including a "slow mode" for default power-up, initialization, etc. The operating (or "fast") speed or mode of each device can be statically set by the BIOS. The common clock on the link can be configured based on the respective operating speeds of each device on either side of the link. For example, in other examples, the link speed can be based on the slower of the two device operating speeds. Any operating speed change can be accompanied by a hot reset or a cold reset.

In some examples, at power-up, the link is initialized to a slow mode with a transfer rate of, for example, 100 MT/s. The software then sets both sides for the operating speed of the link and begins initialization. In other cases, where there is no slow mode or the slow mode is unavailable, a sideband mechanism can be used to establish the link, including a common clock on the link.

In one embodiment, the slow mode initialization phase may use the same coding, scrambling, training sequence (TS), states, etc. as the operating speed, but may have fewer features (e.g., no power parameter setup, no adaptation, etc.). The slow mode operating node may also use the same coding, scrambling, etc. (although other implementations may differ) but may have fewer states and features (e.g., no low power state) compared to the operating speed.

Moreover, the slow mode can be implemented using the local phase-locked loop (PLL) clock frequency of the device. For example, HPI can support simulated slow mode without changing the PLL clock frequency. Although some designs can use separate PLLs for slow speeds and fast speeds, in some implementations of HPI, simulated slow mode can be implemented by allowing the PLL clock to run at the same fast operating speed during slow mode. For example, a transmitter can simulate a slower clock signal by repeating multiple bits multiple times to simulate a slow high clock signal followed by a slow low clock signal. The receiver can then oversample the received signal to locate multiple edges simulated by the repeated bits and identify the bit. In this implementation, multiple ports sharing a PLL can coexist at slow speeds and fast speeds.

Public slow mode speed can be initialized between two devices.For example, two devices on a link can have different fast operating speeds.Public slow mode speed can be configured during, for example, a discovery phase or a state on a link.In an example, the simulation multiple can be set to an integer (or non-integer) ratio of a fast speed to a slow speed, and different fast speeds can be converted downward to work with the same slow speed.For example, two device agents supporting at least one common frequency can be hot-attached, no matter what speed the host port runs at.Then, software finds that a slow mode link can be used to identify and set up an optimal link operating speed.When the multiple is an integer ratio of a fast speed to a slow speed, different fast speeds can work with the same slow speed, and the same slow speed can be used during (for example, hot-attached) discovery phase.

In some implementations of HPI, adaptation of multiple lanes on a link may be supported. The physical layer may support both receiver adaptation and transmitter (or sender) adaptation. For receiver adaptation, a transmitter on a lane may send sampled data to a receiver, and the receiver logic may process the sampled data to identify shortcomings in the electrical characteristics of the lane and the quality of the signal. The receiver may then make adjustments to the calibration of the lane in order to optimize the lane based on an analysis of the received sampled data. In the case of transmitter adaptation, the receiver may again receive sampled data and develop a metric describing the quality of the lane, but in this case the metric is transmitted to the transmitter (e.g., using a backchannel, such as software, hardware, embedded, sideband or other channel) so that the transmitter can make adjustments to the lane based on feedback. Receiver adaptation may be initiated at the beginning of the polling state using a polling supersequence sent from a remote transmitter. Similarly, transmitter adaptation may be accomplished by repeating the following for each transmitter parameter. Both agents may enter the loopback mode state as a host and transmit the specified mode. Both receivers can measure a metric (e.g., BER) for that particular transmitter setting at the remote agent. Both agents can enter a loopback tag state, then a reset state, and use a back channel (slow mode TLS or sideband) to exchange metrics. Based on these metrics, the next transmitter setting can be identified. Finally, the optimal transmitter setting can be identified and saved for subsequent use.

Since both devices on the link can run the same reference clock (e.g., ref clk), the elastic buffer can be omitted (any elastic buffer can be bypassed or used as a drift buffer with the lowest possible delay). However, a phase adjustment or drift buffer can be used on each lane to transfer the corresponding receiver bit stream from the remote clock domain to the local clock domain. The latency of the drift buffer may be sufficient to handle the sum of drifts from all sources within the electrical specification (e.g., voltage, temperature, residual SSC caused by reference clock routing adaptation, etc.), but should be as small as possible to reduce transmission delay. If the drift buffer is too shallow, drift errors will occur and will appear as a series of CRC errors. Thus, in other examples, in some implementations, a drift warning can be provided, which will initiate a physical layer reset before an actual drift error occurs.

Some implementations of HPI can support two sides running at the same nominal reference clock frequency but with a ppm difference. In other examples, in this case, a frequency adjustment (or elasticity) buffer may be required, and the frequency adjustment buffer may be re-adjusted during an extended BLS window or during a special sequence that may occur periodically.

Among other considerations, the operation of the HPIPHY logical layer can be independent of the underlying transmission medium - provided that latency does not cause delays, fixed errors or timeouts at the link layer.

External interfaces may be provided in the HPI to help manage the physical layer. For example, external signals (from pins, fuses, other layers), timers, control and status registers may be provided. Input signals may change at any time relative to the PHY state and are to be observed by the physical layer at a specific point in the corresponding state. For example, in other examples, after the link has entered the transmit link state, a changing alignment signal (described below) may be received but has no actual effect. Similarly, command register values may be observed by the physical layer entity only at a specific point in time. For example, the physical layer logic may obtain a snapshot of the value and use it in subsequent operations. Thus, in some implementations, updates to the command register may be associated with a limited subset of specific time periods (e.g., when in the transmit link state or when held in reset calibration, in the slow mode transmit link state) to avoid abnormal behavior.

Since the state values track hardware changes, the value readings may depend on when they are read. However, some state values (such as link maps, latency, speed, etc.) may not change after initialization. For example, reinitialization (or low power link state (LPLS), or L1 state, exit) is the only thing that can cause these to change (e.g., hard lane failures in TLS will not cause reconfiguration of the link until reinitialization is triggered, among other examples).

Interface signals may include signals that are external to the physical layer but affect the behavior of the physical layer. As an example, such interface signals may include coding and timing signals. Interface signals may be design specific. These signals may be inputs or outputs. In other examples, some interface signals (such as so-called armboard signals and other examples with prefix EO) may be active each time an edge is asserted, i.e., they may be de-asserted and then re-asserted to be valid again. For example, Table 1 includes an example list of example functions:

Table 1

CSR timer default values can be provided in pairs - one for slow mode and one for operating speed. In some instances, a value of 0 disables the timer (i.e., a timeout does not occur). Timers can include those shown in Table 2 below. The primary timer can be used to time the expected actions in a state. The secondary timer is used to terminate initialization that is not in progress or to advance state transitions at accurate moments in automatic test equipment (i.e., ATE) mode. In some cases, the secondary timer within a state can be much larger than the primary timer. The exponential timer set can be suffixed with exp, and the timer value is doubled to the field value. For linear timers, the timer value is the field value. Any timer can use a different granularity. In addition, some timers in the power management portion can be in a set called timing profiles. These can be associated with timing diagrams of the same name.

Table 2

Command and control registers may be provided. Control registers may be late action and may be read or written by software in some instances. Late action values may be continuously effective upon reset (e.g., from a software facing phase to a hardware facing phase). The control arm board signal (prefixed CP) is RWIS and may be cleared by hardware. Control registers may be used to perform any of the items described herein. They may be modified and accessed by hardware, software, firmware, or a combination thereof.

Status registers may be provided to track hardware changes (written and used by the hardware) and may be read-only (but debugging software may also be able to write to them). Such registers may not affect interoperability and may generally be implemented using many private status registers. Because the status arm-plane signal (prefixed with SP) can be cleared by software, the status arm-plane signal may be forced to redo the action of setting the status. Default means that the initial (at reset) value may be provided as a subset of these status bits related to initialization. This register may be copied into a storage structure when initialization is aborted.

Toolbox registers may be provided. For example, the testability toolbox registers in the physical layer may provide pattern generation, pattern checking, and loopback control mechanisms. Higher-level applications may utilize these registers along with electrical parameters to determine margins. For example, an interconnect built under test may utilize the toolbox to determine margins. In other examples, for transmitter adaptation, these registers may be used in conjunction with the specific registers described in the previous section.

In some implementations, HPI supports the use of reliability, availability, and serviceability (RAS) capabilities of the physical layer. In one embodiment, HPI supports hot plugging and hot removal for one or more layers, which may include software. Hot removal may include silencing the link, and the initialization start state/signal may be cleared to cause the agent to be removed. The remote agent (i.e., the agent that is not being removed (e.g., the host agent)) may be set to a slow speed, and its initialization signal may also be cleared. In other examples and features, an in-band reset (e.g., via BLS) may cause both agents to wait in a reset state (such as a calibration reset state (CRS)); the agent to be removed may be removed (or may be held in a directional pin reset, powered off). In practice, some of the above events may be omitted, and additional events may be added.

Hot add can include that the initialization speed can be defaulted to slow, and the initialization signal can be set on the agent to be added. The software can set the speed to slow, and the initialization signal on the remote agent can be cleared. The link can occur in slow mode, and the software can determine the operating speed. In some cases, the PLL relock of the remote agent is not performed at this time. The operating speed can be set on both agents, and the enable can be set to adapt (if not completed before). The initialization start indicator on both agents can be cleared, and the in-band BLS reset will cause both agents to wait in the CRS. The software can assert the hot reset (e.g., directional reset or self-reset) of the agent (to be added), which can relock the PLL. The software can also set the initialization start signal by any known logic, and further set it on the remote agent (thus pushing it into the receiver detection state (RDS)). The software can de-assert the hot reset of the added agent (thus pushing it into the RDS). Then, in other examples, the link can be initialized to the transmit link state (TLS) at the operating speed (or initialized to the loopback state if the adaptation signal is set). In fact, some of the above events can be omitted, and additional events can be added.

Data lane failure recovery may be supported. In one embodiment, a link in HPI may configure itself to be smaller than full width (e.g., less than half full width) to be resilient to hard errors on a single lane, thereby excluding failed lanes. As an example, configuration may be accomplished by a link state machine, where unused lanes may be shut down. As a result, in other examples, fliers may be sent across a narrower width.

In some implementations of HPI, lane reversal may be supported on some links. For example, lane reversal may refer to lanes 0/1/2... of the transmitter being connected to lanes n/n-1/n-2... of the receiver (e.g., n may be equal to 19 or 7, etc.). Lane reversal may be detected at the receiver as indicated in a field of the TS header. The receiver may implement lane reversal by starting a polling state using physical lane n...0 for logical lanes 0...n. Thus, references to lanes may refer to logical lane numbers. Thus, a wide range of designers may more efficiently specify physical or electrical designs, and HPI may work with virtual lane allocations, as described herein. Additionally, in one embodiment, polarity may be reversed (i.e., when a differential transmitter +/- is connected to a receiver -/+). Polarity may also be detected at the receiver from one or more TS header fields, and implemented in the polling state in one embodiment.

Referring to FIG. 10 , an embodiment of a block diagram for a computing system including a multi-core processor is described. Processor 1000 includes any processor or processing device or other device for executing code, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC). In one embodiment, processor 1000 includes at least two cores, cores 1001 and 1002, which may include asymmetric cores or symmetric cores (illustrated embodiment). However, processor 1000 may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a processing unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element capable of maintaining a state of a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) generally refers to an integrated circuit, which may include any number of other processing elements, such as cores or hardware threads.

A core generally refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread generally refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As shown, when certain resources are shared and other resources are dedicated to an architectural state, the lines between the naming of hardware threads and cores overlap. But often, cores and hardware threads are viewed by the operating system as individual logical processors, where the operating system can schedule operations on each logical processor individually.

As shown in Figure 10, the physical processor 1000 includes two cores, cores 1001 and 1002. Here, cores 1001 and 1002 are regarded as symmetric cores, i.e., cores with the same configuration, functional units and/or logic. In another embodiment, core 1001 includes an out-of-order processor core, and core 1002 includes an in-order processor core. However, cores 1001 and 1002 can be individually selected from any type of core, such as a native core, a software-managed core, a core suitable for executing a native instruction set architecture (ISA), a core suitable for executing a converted instruction set architecture (ISA), a co-designed core, or other known cores. In a heterogeneous core environment (i.e., an asymmetric core), some form of conversion (e.g., binary conversion) can be used to schedule or execute code on one or both cores. For further discussion, the functional units shown in core 1001 are further described in detail below, and the units in core 1002 operate in a similar manner in the embodiment.

As shown in the figure, core 1001 includes two hardware threads 1001a and 1001b, which may also be referred to as hardware thread slots 1001a and 1001b. Therefore, in one embodiment, a software entity such as an operating system may regard processor 1000 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, the first thread is associated with architecture state register 1001a, the second thread is associated with architecture state register 1001b, the third thread may be associated with architecture state register 1002a, and the fourth thread may be associated with architecture state register 1002b. Here, each of architecture state registers (1001a, 1001b, 1002a and 1002b) may be referred to as a processing element, thread slot or thread unit, as described below. As shown in the figure, architecture state register 1001a is replicated in architecture state register 1001b, so that individual architecture states/contexts can be stored for logical processor 1001a and logical processor 1001b. Other smaller resources may also be replicated for threads 1001a and 1001b in core 1001, such as instruction pointers and renaming logic in allocator and renamer block 1030. Some resources may be shared through partitioning, such as reorder buffers, ILTB 1020, load/store buffers, and queues in reorder/retirement unit 1035. Other resources may be fully shared, such as general internal registers, page table base registers, low-level data cache and data TLB 1015, execution units 1040, and portions of out-of-order unit 1035.

Processor 1000 generally includes other resources, and other resources can be fully shared, shared by partitions, or dedicated by/to processor elements. In Figure 10, an embodiment of a pure exemplary processor with a schematic logic unit/resource of a processor is shown. Note that the processor may include or omit any of these functional units, and include any other known functional units, logic or firmware not shown. As shown, core 1001 includes a simplified representative out-of-order (OOO) processor core. But in-order processors can be used in different embodiments. The OOO core includes a branch target buffer 1020 for predicting branches to be executed/taken and an instruction translation buffer (I-TLB) 1020 for storing address translation entries of instructions.

The core 1001 also includes a decoding module 1025 coupled to the fetch unit 1020 to decode the fetched elements. In one embodiment, the fetch logic includes individual sequencers associated with the thread slots 1001a, 1001b, respectively. Typically, the core 1001 is associated with a first ISA that defines/specifies instructions executable on the processor 1000. Typically, a machine code instruction that is part of the first ISA includes a portion of an instruction (referred to as an opcode) that references/specifies an instruction or operation to be executed. The decoding logic 1025 includes circuits for recognizing these instructions from their opcodes and passing decoded instructions on the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, the decoder 1025 includes logic designed or adapted to recognize specific instructions (such as transaction instructions). As a result of the recognition by the decoder 1025, the architecture or core 1001 takes specific, predefined actions to perform tasks associated with the appropriate instructions. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some instructions may be new instructions or old instructions. Note that in one embodiment, decoder 1026 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoder 1026 recognizes a second ISA (either a subset of the first ISA, or a different ISA).

In one example, allocator and renamer block 1030 includes an allocator to reserve resources (such as a register file) to store instruction processing results. However, threads 1001a and 1001b may be capable of out-of-order execution, where allocator and renamer block 1030 also reserves other resources, such as a recorder buffer for tracking instruction results. Unit 1030 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1000. Recorder/retirement unit 1035 includes components, such as the above-mentioned recorder buffer, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

In one embodiment, the scheduler and execution unit block 1040 includes a scheduling unit to schedule instructions/operations on the execution unit. For example, floating point instructions are scheduled on a portion of the execution unit that has an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

A lower level data cache and data translation buffer (D-TLB) 1050 is coupled to the execution unit(s) 1040. The data cache is used to store recently used/operated on elements such as data operands, which may be maintained in a memory consistency state. The D-TLB is used to store recent virtual/linear to physical address translations. As a specific example, the processor may include a page table structure to divide physical memory into multiple virtual pages.

Here, cores 1001 and 1002 share access to a higher level or higher level cache, such as a second level cache associated with on-chip interface 1010. Note that higher level or higher level refers to a cache level that is promoted or further promoted from the execution unit(s). In one embodiment, the higher level cache is a last level data cache - the last cache in the memory hierarchy on processor 1000, such as a second or third level data cache. However, the higher level cache is not limited to this, as it may be associated with or include an instruction cache. Alternatively, a trace cache (a type of instruction cache) may be coupled after decoder 1025 to store recently decoded traces. Here, instructions may refer to macroinstructions (i.e., general instructions recognized by the decoder), which may be decoded into many microinstructions (micro-operations).

In the configuration, the processor 1000 also includes an on-chip interface module 1010. Historically, a memory controller has been included in a computer system external to the processor 1000, and the memory controller is described in more detail below. In this scenario, the on-chip interface 101 is used to communicate with devices external to the processor 1000, such as system memory 1075, a chipset (typically including a memory controller hub for connecting to the memory 1075 and an I/O controller hub for connecting peripheral devices), a memory controller hub, a north bridge, or other integrated circuits. In this scenario, the bus 1005 can include any known interconnect, such as a multi-point bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory 1075 may be dedicated to processor 1000 or shared with other devices in the system. Examples of common types of memory 1075 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1080 may include a graphics accelerator, a processor or card coupled to a memory controller hub, a data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known devices.

However, recently, as more logic and devices are integrated onto a single chip (such as a SOC), each of these devices may be combined onto the processor 1000. For example, in one embodiment, a memory controller hub is on the same package and/or chip as the processor 1000. Here, a portion of the core (on-core portion) 1010 includes one or more controllers for interfacing with other devices such as memory 1075 or a graphics device 1080. A configuration including interconnects and controllers for interfacing with these devices is generally referred to as an on-core (i.e., an uncore configuration). As an example, the on-chip interface 1010 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1005 for off-chip communication. However, in a SOC environment, even more devices (such as a network interface, a coprocessor, memory 1075, a graphics processor 1080, and any other known computer device/interface) may be integrated onto a single chip or integrated circuit to provide a small form factor with high functionality and low power consumption.

In one embodiment, processor 1000 can execute compiler, optimize and/or converter code 1077 to compile, convert and/or optimize application code 1076 to support apparatus and method described herein or interface with apparatus and method described herein. Compiler generally includes program or assembly that source text/code is converted into target text/code. Usually, the compiling done by compiler to program/application code is completed in multiple stages, and multiple passes are made to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compiler can still be utilized for simple compilation. Compiler can use any known compilation count and perform any known compiler operation, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion and code optimization.

Larger compilers typically include multiple phases, but typically these phases are included in two general phases: (1) the front end, i.e., the phase where lexical processing, semantic processing, and some transformations/optimizations generally occur; and (2) the back end, i.e., the phase where analysis, transformations, optimizations, and code generation generally occur. Some compilers are adapted to be in the middle, indicating that the division between the front end and back end of the compiler is blurred. As a result, the insertion of references, associations, generation, or other operations of the compiler may occur in any of the above phases or passes, as well as in any other known phase or pass of the compiler. As an illustrative example, the compiler may insert operations, calls, functions, etc. in one or more phases of compilation, such as inserting calls/operations in the front end phase of compilation and then converting the calls/operations into lower-level code in the transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (compiled code) may be dynamically optimized at runtime. Here, program code may include dynamic optimization code, binary code, or a combination thereof.

Similar to compilers, converters such as binary converters convert code either statistically or dynamically to optimize and/or convert code. Thus, references to code execution, application code, program code, or other software environments may refer to: (1) executing a compiler program, code optimizer, or converter either dynamically or statistically to compile program code, maintain software structure, perform other operations, optimize code, or convert code; (2) executing a main program code including operations/calls, such as application code that has been optimized/compiled; (3) executing other program code associated with the main program code (such as a library) to maintain software structure, perform other software-related operations, or optimize code; or (4) combinations of the above.

Referring to FIG. 11 , a block diagram of an embodiment of a multi-core processor is shown. As shown in the embodiment of FIG. 11 , a processor 1100 includes multiple domains. Specifically, a core domain 1130 includes multiple cores 1130A-1130N, a graphics domain 1160 includes one or more graphics engines with a media engine 1165, and a system proxy domain 1110.

In various embodiments, system agent domain 1110 implements power control events and power management so that individual units (e.g., cores and/or graphics engines) of domains 1130 and 1160 are independently controllable to dynamically operate in an appropriate power mode/level (e.g., active, turbo, sleep, hibernate, deep sleep, or other advanced configuration power interface-like states) based on the activity (or inactivity) occurring within a given unit. Each of domains 1130 and 1160 may operate at different voltages and/or powers, and each individual unit within a domain may operate at independent frequencies and voltages. Note that although only three domains are shown, it is understood that the scope of the present invention is not limited to this, and additional domains may exist in other embodiments.

As shown, in addition to the various execution units and additional processing elements, each core 1130 also includes a low-level cache. Here, the cores are coupled to each other and to a shared cache memory in the form of multiple units or slices 1140A-1140N of a last-level cache (LLC); these LLCs typically include memory and cache controller functions and are shared among multiple cores and possibly among graphics engines.

As shown, a ring interconnect 1150 couples the cores together and provides interconnection between the core domain 1130, the graphics domain 1160, and the system agent circuit 1110 via a plurality of ring stops 1152A-1152N. As shown in FIG. 11 , the interconnect 1150 is used to carry various information, including address information, data information, confirmation information, and snoop/invalidation information. Although a ring interconnect is illustrated, any known on-chip interconnect or construction may be utilized. As an illustrative example, some of the constructions discussed above (e.g., another on-chip interconnect, a system on chip construction (OSF), an advanced microprocessor bus architecture (AMBA) interconnect, a multi-dimensional mesh construction, or other known interconnect architectures) may be used in a similar manner.

As further described, the system agent domain 1110 includes a display engine 1112 for providing control of an interface to an associated display. The system agent domain 1110 may include other units, such as: an integrated memory controller 1120 that provides an interface to system memory (e.g., DRAM implemented in multiple DIMMs); and coherent logic 1122 for performing memory coherent operations. There may be multiple interfaces for interconnecting between processors and other circuits. For example, in one embodiment, at least one direct media interface (DMI) 1116 interface and one or more PCIe ^TM interfaces 1114 are provided. The display engine and these interfaces are generally coupled to the memory via a PCIe ^TM bridge 1118. Further, one or more other interfaces may be provided for communication between other agents, such as additional processors or other circuits.

Referring now to FIG. 12 , a block diagram of a representative core is shown; specifically, multiple logic blocks of the back end of a core (such as core 1130 of FIG. 11 ) are shown. In general, the structure shown in FIG. 12 includes an out-of-order processor having a front end unit 1270 that is used to fetch incoming instructions, perform various processing (e.g., caching, decoding, branch prediction, etc.) and pass the instructions/operations together to an out-of-order (OOO) engine 1280. The OOO engine 1280 performs further processing on the decoded instructions.

Specifically, in the embodiment of FIG. 12 , the out-of-order engine 1280 includes an allocation unit 1282 for receiving decoded instructions from the front end unit 1270 and allocating the decoded instructions to appropriate resources such as registers. The decoded instructions may be in the form of one or more micro-instructions, i.e., microinstructions. Next, the instructions are provided to a reservation station 1284, which reserves resources and schedules resources for execution on one of a plurality of execution units 1286A-1286N. There may be various types of execution units, including, for example, an arithmetic logic unit (ALU), a load and store unit, a vector processing unit (VPU), a floating point execution unit, and the like. The results from these different execution units are provided to a record buffer (ROB) 1288, which records the out-of-order results and returns them to correct the program order.

Still referring to FIG. 12 , it is noted that the front end unit 1270 and the out-of-order engine 1280 are coupled to different levels of the memory hierarchy. Specifically, an instruction set cache 1272 is shown, which is in turn coupled to a mid-level cache 1276, which is in turn coupled to a last-level cache 1295. As an example, the unit 1290 is similar to the system agent 810 of FIG. 8 . As discussed above, the uncore 1290 communicates with the system memory 1299, which in the illustrated embodiment is implemented via ED RAM. It is also noted that the various execution units 1286 within the out-of-order engine 1280 communicate with the first-level cache 1274, which also communicates with the mid-level cache 1276. It is also noted that additional cores 1230N-2…1230N may be coupled to the LLC 1295. Although shown at this high level in the embodiment of FIG. 12 , it is also understood that various modifications and additional components may exist.

Turning to FIG. 13 , a block diagram of an exemplary computer system formed with a processor including an execution unit to execute instructions, wherein one or more of a plurality of interconnected ones implement one or more features according to an embodiment of the present invention. According to the present invention, such as in the embodiments described herein, system 1300 includes a component (such as processor 1302) to employ an execution unit, the execution unit including logic for executing an algorithm to process data. System 1300 represents a processing system based on a PENTIUMIII ^TM , PENTIUM 4 ^TM , Xeon ^TM , Itanium, XScale ^TM and/or StrongARM ^TM microprocessor, although other systems (including PCs with other microprocessors, engineer workstations, set-top boxes, etc.) may also be used. In one embodiment, sample system 1300 executes a version of the WINDOWS ^TM operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software and/or graphical user interfaces may also be used. Therefore, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), systems on chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can execute one or more instructions according to at least one embodiment.

In the illustrated embodiment, the processor 1302 includes one or more execution units 1308 to implement an algorithm for executing at least one instruction. An embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multi-processor system. System 1300 is an example of a "hub" system architecture. Computer system 1300 includes a processor 1302 to process data signals. As an illustrative example, processor 1302 includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements a combination of instruction sets, or any other processor device (such as, for example, a digital signal processor). Processor 1302 is coupled to a processor bus 1310, which transmits data signals between processor 1302 and other components in system 1300. The multiple elements of system 1300 (e.g., graphics accelerator 1312, memory controller hub 1316, memory 1320, I/O controller hub 1324, wireless transceiver 1326, flash BIOS 1328, network controller 1334, audio controller 1336, serial expansion port 1338, I/O controller 1340, etc.) perform their conventional functions that are well known to those skilled in the art.

In one embodiment, the processor 1302 includes a level 1 (L1) internal cache memory 1304. Depending on the architecture, the processor 1302 may have a single internal cache, or multiple levels of internal cache. Depending on the specific implementation and requirements, one embodiment includes a combination of both internal and external caches. The register file 1306 is used to store different types of data in various registers, including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

Also resident in the processor 1302 is an execution unit 1308, which includes logic for performing integer and floating point operations. In one embodiment, the processor 1302 includes a microcode (microcode) ROM for storing microcode, which, when executed, is used to execute the algorithm of a specific macroinstruction or handle complex situations. Here, the microcode may be updated to implement logic errors/fixes of the processor 1302. For one embodiment, the execution unit 1308 includes logic for handling a grouped instruction set 1309. By including the grouped instruction set 1309 in the instruction set of the general-purpose processor 1302, together with associated circuits for executing instructions, operations used by many multimedia applications can be performed using grouped data in the general-purpose processor 1302. Thus, by using the full width of the processor's data bus to perform operations on grouped data, many multimedia applications can be accelerated and executed more efficiently. This potentially eliminates the need to pass smaller data units across the processor's data bus to perform one or more operations, passing one data element at a time.

Alternative embodiments of execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1300 includes memory 1320. Memory 1320 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1320 stores instructions and/or data represented by data signals to be executed by processor 1302.

Note that any of the above features or aspects of the present invention may be used on one or more interconnects shown in FIG. 13. For example, an on-chip interconnect (ODI) (not shown) is used to couple internal units of the processor 1302, and the on-chip interconnect implements one or more aspects of the present invention described above. Alternatively, the present invention is associated with the following: a processor bus 1310 (e.g., other known high-performance computing interconnects), a high-bandwidth memory path 1318 to a memory 1320, a point-to-point link to a graphics accelerator 1312 (e.g., a Peripheral Component Interconnect Express (PCIe) compatible fabric), a controller hub interconnect 1322, an I/O or other interconnect (e.g., USB, PCI, PCIe) for coupling other components shown. Some examples of these components include an audio controller 1336, a firmware hub (Flash BIOS) 1328, a wireless transceiver 1326, a data memory 1324, a conventional I/O controller 1310 including a user input and keyboard interface 1342, a serial expansion port 1338 such as a Universal Serial Bus (USB), and a network controller 1334. Data storage device 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

Referring now to FIG. 14 , a block diagram of a second system 1400 is shown in accordance with an embodiment of the present invention. As shown in FIG. 14 , microprocessor 1400 is a point-to-point interconnect system and includes a first processor 1470 and a second processor 1480 coupled via a point-to-point interconnect 1450. Each of processors 1470 and 1480 may be a version of a processor. In an embodiment, 1452 and 1454 are part of a serial point-to-point coherent interconnect (such as a high performance architecture). As a result, the present invention may be implemented within a QPI architecture.

Although only two processors 1470, 1480 are shown, it should be understood that the scope of the present invention is not limited in this regard. In other embodiments, one or more additional processors may be present in a given processor.

The processors 1470 and 1480 are shown including integrated memory controller units 1472 and 1482, respectively. The processor 1470 also includes point-to-point (P-P) interfaces 1476 and 1478 as part of its bus controller unit; similarly, the second processor 1480 includes P-P interfaces 1486 and 1488. The processors 1470, 1480 can exchange information via the point-to-point (P-P) interface 1450 using interface circuits 1478, 1488. As shown in FIG. 14, the IMCs 1472 and 1482 couple the processors to respective memories, namely, memory 1432 and memory 1434, which can be portions of main memory locally attached to the respective processors.

Each of the processors 1470, 1480 exchanges information with the chipset 1490 via respective P-P interfaces 1452, 1454 using point-to-point interface circuits 1476, 1494, 1486, 1498. The chipset 1490 also exchanges information with the high-performance graphics circuit 1438 via interface circuit 1492 according to a high-performance graphics interconnect 1439.

A shared cache (not shown) may be included within either processor or external to both processors; still connected to the processors via the P-P interconnect so that when the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

Chipset 1490 may be coupled to first bus 1416 via interface 1496. In one embodiment, first bus 1416 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not limited in this regard.

As shown in Figure 14, various I/O devices 1414 are coupled to the first bus 1416, together with a bus bridge 1418 that couples the first bus 1416 to the second bus 1420. In one embodiment, the second bus 1420 includes a low pin count (LPC) bus. Various devices are coupled to the second bus 1420, including, for example, a keyboard and/or mouse 1422, a communication device 1427, and a storage unit 1428 such as a disk drive or other mass storage device, which, in one embodiment, typically includes instructions/codes and data 1430. Moreover, the audio I/O 1424 is coupled to the second bus 1420. It is noted that other architectures are also possible, wherein the components and interconnection architectures included can vary. For example, instead of the point-to-point architecture of Figure 14, the system can implement a multi-point bus or other such architectures.

Turning next to FIG. 15 , an embodiment of a system on chip (SOC) design according to the present invention is described. As a specific illustrative example, SOC 1500 is included in a user equipment (UE). In one embodiment, UE refers to any device to be used by an end user for transmission, such as a handheld phone, a smart phone, a tablet computer, an ultra-thin notebook computer, a notebook computer with a broadband adapter, or any other similar communication device. Typically, a UE is connected to a base station or node, which may correspond in nature to a mobile station (MS) in a GSM network.

Here, SOC 1500 includes two cores - 1506 and 1507. Similar to the above discussion, cores 1506 and 1507 may conform to an instruction set architecture, such as based on The processor of the architecture core ^TM , the processor of Advanced Micro Devices (AMD), the processor based on MIPS, the processor based on ARM, or its consumer and its licensee or adopter. The cores 1506 and 1507 are coupled to the cache control 1508, which is associated with the bus interface unit 1509 and the L2 cache 1511 for communicating with other parts of the system 1500. The interconnect 1510 includes an on-chip interconnect, such as IOSF, AMBA or other interconnects discussed above, which may implement one or more aspects described herein.

The interconnect 1510 provides a communication channel to other components, such as a subscriber identity module (SIM) 1530, an SDRAM controller 1540, a flash controller 1545, a peripheral control 1550, a GPU 1515, etc., wherein the subscriber identity module (SIM) 1530 is used to interface with a SIM card, a boot rom 1535 to retain the boot code executed by the cores 1506 and 1507 to initialize and boot the SOC 1500; the SDRAM controller 1540 is used to interface with an external memory (e.g., DRAM 1560); the flash controller 1545 is used to interface with a non-volatile memory (e.g., flash memory 1565); the peripheral control 1550 (e.g., a serial peripheral interface) is used to interface with peripheral devices, a video codec 1520 and a video interface 1525 to display and receive input (e.g., touch input); and the GPU 1515 is used to perform graphics-related calculations. Any of these interfaces can be combined with the various aspects of the invention described herein.

In addition, the system shows peripherals for communication, such as Bluetooth module 1570, 3G modem 1575, GPS 1585 and WiFi 1585. Note that as mentioned above, the UE includes a radio for communication. As a result, these peripheral communication modules are not all required. However, in the UE, some form of radio for external communication is included.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the present invention.

A design may go through various stages, from creation to simulation to manufacturing. Data representing a design may represent the design in many ways. First, as useful in simulation, hardware may be represented by a hardware description language or another functional description language. In addition, a circuit-level model with logic and/or transistor gates may be generated at certain stages of the design process. Moreover, many designs reach a data level representing the physical location of each device in the hardware model at a certain stage. In the case of using conventional semiconductor manufacturing technology, the data representing the hardware model may be data specifying the presence or absence of each feature on different mask layers of a mask used to produce an integrated circuit. In any representation of a design, the data may be stored in any form of machine-readable medium. A memory or a magnetic or optical storage such as a disk may be a machine-readable medium for storing information transmitted via light waves or electric waves, which are modulated or otherwise generated to transmit such information. When an electric carrier wave indicating or carrying a code or design is transmitted, a new copy is made in terms of duplication, buffering or retransmission of the electric signal. Thus, a communication provider or a network provider may store items embodying the technology of an embodiment of the present invention on a tangible machine-readable medium, such as information encoded as a carrier wave, at least temporarily.

As used herein, a module refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware (such as a microcontroller) associated with a non-transitory medium for storing code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware that is specifically configured to recognize and/or execute code to be retained on a non-transitory medium. Moreover, in another embodiment, the use of a module refers to a non-transitory medium including code that is specifically adapted to be executed by a microprocessor in order to perform a predetermined operation. In yet another embodiment, as can be inferred, the term module (in this example) refers to a combination of a microprocessor and a non-transitory medium. Typically, the boundaries of modules illustrated as separate typically vary and may overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic devices.

In one embodiment, the use of the phrase "configured to" refers to arranging, putting together, manufacturing, promising for sale, importing and/or designing a device, hardware, logic or element to perform a specified or determined task. In this example, if a device or its element is designed, coupled and/or interconnected to perform a specified task, the device or element is still "configured to" perform the specified task even if it is not in operation. As a purely illustrative example, a logic gate can provide 0 or 1 during operation. But a logic gate "configured to" provide an enable signal to a clock does not include every possible logic gate that may provide 1 or 0. Instead, a logic gate is a gate coupled in a manner that a 1 or 0 output is used to enable a clock during operation. Note again that the use of the term "configured to" does not require operation, but focuses on the latent state of the device, hardware and/or element, where in the latent state, the device, hardware and/or element is designed to perform a specific task when the device, hardware and/or element is operating.

Furthermore, in one embodiment, the use of the phrases "for", "can/with", and or "operable for" refers to a device, hardware, and/or element being designed in a manner that enables the device, hardware, and/or element to be used in a specified manner. Note that in one embodiment, the use of "for", "can", or "operable for" refers to a latent state of a device, hardware, and/or element, wherein the device, hardware, and/or element is not in operation, but is designed in a manner that enables the device to be used in a specified manner.

As used herein, a value includes any known representation of a number, state, logic state, or binary logic state. Typically, the use of logic levels, logic values, or logical values, also referred to as 1 and 0, simply represents a binary logic state. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage unit (such as a transistor or a flash memory cell) may be able to hold a single logic value or multiple logic values. However, other representations of values in a computer system have been used. For example, the decimal number 10 may also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, a value includes any representation of information that can be held in a computer system.

In addition, a state may be represented by a value or a portion of a value. As an example, a first value (such as a logical 1) may represent a default or initial state, while a second value (such as a logical 0) may represent a non-default state. In addition, in one embodiment, the terms reset and set refer to default and updated values or states, respectively. For example, a default value may include a high logic value, i.e., reset, and an updated value may include a low logic value, i.e., set. Note that any combination of values may be used to represent any number of states.

Embodiments of the methods, hardware, software, firmware or code presented above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible or computer-readable medium, which may be executed by a processing element. Non-transitory machine-accessible/readable media include any mechanism that provides (i.e., stores and/or transmits) information in a form that can be read by a machine (such as a computer or electronic system). For example, non-transitory machine-accessible media include random access memory (RAM) (such as static RAM (SRAM) or dynamic RAM (DRAM)); ROM; magnetic or optical storage media; flash memory devices; electronic storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from transient (propagating) signals, etc., which other storage devices are distinguished from non-transitory media that can receive information.

Instructions for programming logic to perform multiple embodiments of the present invention may be stored in a memory in the system, such as a DRAM, cache, flash memory, or other memory. Moreover, instructions may be distributed via a network or by other computer-readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to: a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM) random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, a flash memory, or a tangible, machine-readable memory for transmitting signals (e.g., carrier waves, infrared signals, digital signals, etc.) via electrical, optical, acoustic, or other forms. Thus, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

The following examples relate to embodiments according to the present specification. One or more embodiments provide apparatus, systems, machine-readable storage, machine-readable media, and methods to initialize a link, wherein the link is to include a plurality of lanes, a transmitter and a receiver are to be coupled to each lane of the plurality of lanes, reinitialization of the link is to include transmitting a predefined sequence on each lane, wherein reinitialization is provided without terminating the link.

In at least one example, a predefined sequence is to be sent from a transmitter to a receiver, and the receiver is to repeatedly send the predefined sequence to the transmitter.

In at least one example, the sequence includes an Electrical Idle Exit Ordered Set (EIEOS).

In at least one example, the sequence also includes multiple instances of a training sequence.

In at least one example, the EIEOS to be repeated is in a sequence according to a minimum frequency.

In at least one example, the sequence is repeated until the link is initialized.

One or more examples may also provide for verifying received instances of a predefined sequence to detect a proxy on a link.

In at least one example, the link comprises a differential serial data link.

In at least one example, the sequence is sent during a reset state to signal an exit from the reset state.

One or more embodiments may provide an apparatus, a system, a machine-readable memory, a machine-readable medium, and a method for transmitting a predefined sequence over multiple lanes of a differential serial data link to another entity connected to the data link, receiving an acknowledgement of the predefined sequence from the other entity, and implementing initialization of the data link using the predefined sequence.

In at least one embodiment, the flyer can be sent from the first device to the second device via a data link. The first and second devices may include microprocessors, graphics accelerators, and other devices.

The following examples pertain to embodiments in accordance with this specification. One or more embodiments may provide apparatus, systems, machine-readable storage, machine-readable media, and methods to detect a predefined sequence on each lane on a link comprising multiple lanes, and determine a state of another agent based on the detection of the predefined sequence.

One or more examples may also echo the predefined sequence to the other agent.

In at least one example, the sequence includes an EIEOS and the detection of the predefined sequence includes verification of the sequence.

In at least one example, verification of the sequence is based at least in part on identifying that the EIEOS is repeated according to a predefined frequency.

In at least one example, the sequence is repeated throughout a particular link initialization state.

In at least one example, the sequence indicates an initialization state.

In at least one example, the initialization state is included in a reinitialization of the link.

In at least one example, the sequence is detected during a reset state and indicates an exit from the reset state.

One or more embodiments may provide apparatus, systems, machine-readable storage, machine-readable media, and methods to monitor loops during link initialization and suspend link initialization in response to determining an unsuccessful loop during initialization.

One or more examples may also maintain a count of loops within the state machine during initialization.

In at least one example, a count is maintained at each agent communicating using the link.

In at least one example, the count is reset when the link is successfully initialized.

In at least one example, successful initialization of the link includes entering a link transmit state.

In at least one example, looping includes re-entering a reset state of the link training state machine.

In at least one example, initialization of the link is suspended in a reset state of the link training state machine.

In at least one example, the suspended initialization of the link is to be restarted in response to a command from the controller.

In at least one example, the link has a link width of 20 lanes.

One or more embodiments may provide an apparatus, a system, a machine-readable storage, a machine-readable medium, and a method to determine whether to perform one or more initialization tasks in conjunction with a specific initialization state; and based on determining whether to perform the initialization task, apply a short timer to transition from a specific state.

One or more examples may also apply a second short timer to transition from the second initialization state, the duration of the second short timer being different from the duration of the first short timer.

In at least one example, a short timer is applied based on a determination not to perform the initialization task.

In at least one example, a long timer for a particular initialization state is applied based on a determination to perform an initialization task.

In at least one example, the determination is based on an indication that a short timer is enabled.

In at least one example, the short timer is enabled by a software-based controller.

In at least one example, the short timer is enabled based on determining that configuration associated with the initialization task has completed.

In at least one example, the link comprises a differential serial data link.

One or more embodiments may provide an apparatus, system, machine-readable storage, machine-readable medium, and method to launch a flyer at a first speed in a first mode and launch a flyer at a second speed in a second mode, wherein a phase locked loop (PLL) speed is the same in the first mode and the second mode.

In at least one example, the first speed comprises an operating speed and the second speed comprises a slow speed.

In at least one example, the slow speed is to be emulated by the operating speed.

In at least one example, emulating the slow speed includes sending a series of bits at the operating speed to emulate bits in a slow mode.

In at least one example, the physical layer logic is further used to convert from the first speed to the second speed.

In at least one example, the transition is based on a request of at least one partially software-based controller.

One or more embodiments may provide apparatus, systems, machine-readable storage, machine-readable media, and methods to: determine an operating speed of a first device to be connected to a second device on a link; determine an operating speed of the second device; and determine a common slow speed to be applied by the first and second devices during transmission of data on the link.

In at least one example, the commonly used slow speed is determined during link initialization.

In at least one example, an operating speed of the first device is different than an operating speed of the second device, and initializing the link further includes determining a common operating speed.

In at least one example, the common operating speed is based on the slower of the operating speeds of the first and second devices.

In at least one example, determining the commonly used slow mode includes determining a first ratio of operating speeds to be applied to the first device to achieve the commonly used slow speed; and determining a second ratio of operating speeds to be applied to the second device to achieve the commonly used slow speed.

In at least one example, a commonly used slow speed is to be emulated by an operating speed.

In at least one example, emulating the slow speed includes sending a series of bits at the corresponding operating speed to emulate bits in a conventional slow mode.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the link comprising a first number of lanes, wherein the PHY comprises a synchronization (sync) counter, and wherein the PHY is used to transmit an electrical idle exit ordered set (EIEOS), the electrical idle exit ordered set (EIEOS) being aligned with the synchronization counter associated with the training sequence.

In at least one example, synchronization counter values from the synchronization counter are not swapped during each training sequence.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the link comprising a first number of lanes, wherein the PHY comprises a synchronization (sync) counter, and wherein the PHY is used to transmit an electrical idle exit ordered set (EIEOS), the electrical idle exit ordered set (EIEOS) being aligned with the synchronization counter associated with the training sequence.

In at least one example, synchronization counter values from the synchronization counter are not swapped during each training sequence.

In at least one example, the EIEOS alignment with the synchronization counter is to act as a proxy for exchanging the synchronization counter value from the synchronization counter during each training sequence.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the PHY being configured to include a software modifiable register and a PHY state machine, the software modifiable register including a control field, the PHY state machine being configured to transition between multiple states, wherein the PHY state machine is configured to maintain a transition between a first state and a second state based on a first value of the control field of the register.

In at least one example, the PHY state machine is to transition between the first state and the second state in response to software updating a control field of a register to a second value.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the PHY being configured to include a PHY state machine to transition between multiple states, wherein the PHY state machine is capable of transitioning from a first state to a second state based on a handshake event, and transitioning the PHY from a third state to a fourth state based on a master timer event.

In at least one example, the PHY state machine can transition the PHY from the fifth state to the sixth state based on a primary timer event in conjunction with a secondary timer event.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the link comprising a first number of lanes, wherein the PHY is used to transmit flyers at a first speed and to transmit flyers at a second speed, and wherein a phase-locked loop (PLL) speed is the same in a fast mode and a slow mode.

In at least one example, the first speed is a slow speed and the second speed is a fast speed.

In at least one example, the PHY for transmitting the flying chip at the slow speed includes: the PHY transmitting the bit of the flying chip at the fast speed multiple times in succession without changing the PLL speed to emulate the bit at the slow speed.

One or more examples may also provide a physical layer (PHY) configured to be coupled to a link, the link comprising a first number of lanes, wherein the PHY is used to transmit flying chips at a slow speed in a slow mode, and to transmit flying chips at a fast speed in a fast mode, the fast speed being greater than 2 times the slow speed, and wherein a phase-locked loop (PLL) speed is the same in the fast mode and the slow mode.

References throughout this specification to "one embodiment" or "an embodiment" refer to a particular feature, structure, or characteristic described in conjunction with an embodiment included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily all refer to the same embodiment. Moreover, particular features, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

In the above description, detailed description has been given with reference to specific exemplary embodiments. However, it is apparent that various modifications and variations may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and description are to be regarded as illustrative rather than restrictive. Moreover, the above use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as possibly the same embodiment.

Claims (20)

1. An apparatus for computing, comprising:

A processor, the processor comprising:

a physical layer circuit, the physical layer circuit to:

Transmitting a first training sequence in training of a physical layer of a link, wherein the first training sequence comprises a repetition sequence, the first training sequence comprises a specific pattern for mimicking a low speed clock, the first training sequence is for repeating a first frequency, and the first training sequence is defined to identify a first training task in the training, wherein,

The first training task comprises a device detection task;

a second training sequence is sent in the training of the physical layer of the link,

Wherein the second training sequence is different from the first training sequence, the second training sequence comprises a repeating sequence, the second training sequence comprises the particular pattern, the second training sequence repeats at a second frequency that is slower than the first frequency, and the second training sequence is defined to identify a second training task in the training, wherein,

The second training task includes determining a lane polarity on the link,

Wherein the particular pattern comprises hexadecimal values.

2. The apparatus of claim 1, wherein the physical layer circuitry is further to transmit a synchronization signal, wherein the link is to be initiated based at least in part on the synchronization signal.

3. The apparatus of claim 1, wherein the hexadecimal value comprises xFF00.

4. The apparatus of claim 1, wherein at least one of the first training sequence or the second training sequence is unscrambled.

5. The apparatus of claim 4, wherein both the first training sequence and the second training sequence are unscrambled.

6. The apparatus of claim 1, wherein a link layer circuit is to generate a flit and cause the flit to be transmitted on the link.

7. The apparatus of claim 6, wherein one or more of the flyers comprises a plurality of slots.

8. The apparatus of claim 1, wherein the layered protocol comprises a coherent interconnect protocol.

9. The apparatus of claim 1, wherein the link comprises at least 8 lanes, and the first training sequence and the second training sequence are transmitted on the at least 8 lanes.

10. The apparatus of claim 1, wherein the first training sequence and the second training sequence are transmitted in association with a reset of the link.

11. The apparatus of claim 1, further comprising:

a link layer circuit for implementing at least part of a link layer of the link; and

Protocol layer logic to implement at least part of a protocol layer of the link.

12. An apparatus for computing, comprising:

physical layer circuitry to implement at least part of a physical layer of a layered protocol;

A link layer circuit for implementing at least part of a link layer of the layered protocol;

Protocol layer circuitry for implementing at least part of a protocol layer of the layered protocol,

Wherein the physical layer circuit is configured to:

Receiving a first training sequence in training of a link, wherein the first training sequence comprises a repeating sequence, the first training sequence comprises a specific pattern for mimicking a low speed clock, the first training sequence is repeated at a first frequency, and the first training sequence is defined to identify a first training task in the training, wherein the first training task comprises a device detection task; and

Receiving a second training sequence in the training of the physical layer of the link, wherein the second training sequence is different from the first training sequence, the second training sequence comprises a repeating sequence, the second training sequence comprises the particular pattern, the second training sequence repeats at a second frequency that is slower than the first frequency, and the second training sequence is defined to identify a second training task in the training, wherein the second training task comprises determining a lane polarity on the link;

wherein the link layer circuitry is to generate and cause the flits to be transmitted over the link, an

Wherein the particular pattern comprises hexadecimal values.

13. The apparatus of claim 12, wherein the physical layer circuitry is further to transmit an instance of the first training sequence to another device, and the first training sequence is received from the other device in response to the transmission of the instance of the first training sequence.

14. The apparatus of claim 12, wherein the physical layer circuitry is further to transmit an instance of the second training sequence to another device, and the second training sequence is received from the other device in response to the transmission of the instance of the second training sequence.

15. The apparatus of claim 12, wherein the physical layer circuitry is further to receive a synchronization signal, wherein the link is to be initiated based at least in part on the synchronization signal.

16. The apparatus of claim 12, wherein the hexadecimal value comprises xFF00.

17. The apparatus of claim 12, wherein one or more of the first training sequence and the second training sequence are unscrambled.

18. The apparatus of claim 12, wherein the layered protocol comprises a coherent interconnect protocol.

19. A system for computing, comprising:

a host device, the host device comprising a processor;

an endpoint device coupled to the processor through an interconnect,

Wherein the host device includes:

A physical layer circuit for implementing at least part of a physical layer of a layered protocol, wherein the physical layer circuit is for;

Transmitting a first training sequence in training of a link for communication between the host device and the endpoint device over the interconnect, wherein the first training sequence comprises a repeating sequence including a particular pattern for mimicking a low speed clock, the first training sequence is repeated at a first frequency, and the first training sequence is defined to identify a first training task in the training, wherein,

The first training task comprises a device detection task;

Transmitting a second training sequence in the training of the link, wherein the second training sequence is different from the first training sequence, the second training sequence comprises a repeating sequence, the second training sequence comprises the particular pattern, the second training sequence repeats at a second frequency that is slower than the first frequency, and the second training sequence is defined to identify a second training task in the training, wherein the second training task comprises determining a lane polarity on the link,

Wherein the particular pattern comprises hexadecimal values.

20. A method for computing, comprising:

Transmitting a first training sequence in training of a link for communication over an interconnect between a host device and an endpoint device, wherein the first training sequence comprises a repeating sequence, the first training sequence comprises a particular pattern for mimicking a low speed clock, the first training sequence is repeated at a first frequency, and the first training sequence is defined to identify a first training task in the training, wherein the first training task comprises a device detection task;

Transmitting a second training sequence in the training of the link, wherein the second training sequence is different from the first training sequence, the second training sequence comprises a repeating sequence, the second training sequence comprises the particular pattern, the second training sequence repeats at a second frequency that is slower than the first frequency, and the second training sequence is defined to identify a second training task in the training, wherein the second training task comprises determining a lane polarity on the link; and

At least one synchronization pattern is sent in association with the initialization of the link,

Wherein the particular pattern comprises hexadecimal values.