CN111639038A - Memory control method and device of DMA controller, storage medium and equipment - Google Patents
Memory control method and device of DMA controller, storage medium and equipment Download PDFInfo
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- CN111639038A CN111639038A CN202010448196.6A CN202010448196A CN111639038A CN 111639038 A CN111639038 A CN 111639038A CN 202010448196 A CN202010448196 A CN 202010448196A CN 111639038 A CN111639038 A CN 111639038A
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention discloses a memory control method, a memory control device, a memory storage medium and memory equipment of a DMA (direct memory access) controller. The method comprises the following steps: obtaining a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller; when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list. By the technical scheme, the consistency of the cache data and the memory data can be effectively ensured, the conflict of the DMA memory and the address space of other memories is avoided, and the accuracy and the safety of data transmission through the DMA are effectively ensured.
Description
Technical Field
The present invention relates to the field of data processing, and in particular, to a method and an apparatus for controlling a memory of a DMA controller, a storage medium, and a device.
Background
DMA (Direct Memory Access) is an ideal way for high-speed data transmission, and DMA operation refers to directly transmitting data between peripheral equipment and a system Memory by using a DMA controller, which greatly saves the load of a Central Processing Unit (CPU), greatly improves the utilization rate of the CPU, and is widely applied to systems with large data transmission.
The DMA controller and the CPU are two parallel units. In the prior art, a CPU always accesses data in a memory through a data cache, and a DMA controller directly accesses the memory. If the data in the memory is updated by the DMA controller and the data in the data cache is not updated, the values of some addresses obtained by the CPU may not be the real values in the memory, which is likely to cause inconsistency between the cached data and the memory data and also likely to cause the address spaces of the DMA memory and the non-DMA memory to overlap, thereby causing an error in the DMA operation.
Disclosure of Invention
The invention provides a memory control method, a device, a storage medium and equipment of a DMA controller, which can effectively ensure the consistency of cache data and memory data, avoid the conflict of the address space of a DMA memory and other memories and effectively ensure the accuracy and the safety when data transmission is carried out through the DMA.
In a first aspect, an embodiment of the present invention provides a memory control method for a DMA controller, including:
obtaining a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller;
when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list.
In the above embodiment, when the DMA address space belongs to the kernel address space, converting the DMA address space into the user address space includes:
when the DMA address space belongs to a kernel address space, acquiring an address conversion rule between the kernel address space and a user address space;
and converting the DMA address space into a user address space according to the address conversion rule.
In the above embodiment, the address translation rule includes:
the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address;
converting the DMA address space to a user address space according to the address conversion rule, comprising:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
In the above embodiment, the obtaining the DMA address space applied by the central processing unit CPU for the DMA controller includes:
obtaining DMA memory configuration information;
and allocating a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
In the above embodiment, the DMA memory configuration information includes a memory block size and a memory block number.
In a second aspect, an embodiment of the present invention further provides a memory control device for a DMA controller, including:
a DMA address space obtaining module for obtaining the DMA address space applied by the CPU for the DMA controller;
the address space conversion module is used for converting the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
and the address space writing module is used for writing the converted DMA address space into a DMA linked list so as to enable the DMA controller to carry out data transmission according to the DMA linked list.
In the foregoing embodiment, the address space translation module includes:
an address translation rule obtaining unit, configured to obtain an address translation rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
and the address space conversion unit is used for converting the DMA address space into a user address space according to the address conversion rule.
In the above embodiment, the address translation rule includes:
the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address;
the address space conversion unit is configured to:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
In the foregoing embodiment, the DMA address space obtaining module is configured to:
obtaining DMA memory configuration information;
and allocating a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
In the above embodiment, the DMA memory configuration information includes a memory block size and a memory block number.
In a third aspect, an embodiment of the present invention further provides a computer storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the memory control method of the DMA controller provided in any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the memory control method of the DMA controller according to the embodiment of the present invention.
The invention provides a memory control scheme of a DMA controller, which comprises the following steps: obtaining a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller; when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, so that the conflict between the memory applied by the DMA controller and the address space of the memory applied by the CPU for other applications can be avoided, the DMA operation error is avoided, and the correctness and the safety of data transmission through the DMA are effectively ensured. Meanwhile, the user address space is a non-cache address space which is not mapped by the data cache, so that the CPU can directly access the data in the DMA memory without data cache, and the inconsistency of cache data and memory data is effectively avoided.
Drawings
Fig. 1 is a schematic flowchart of a memory control method of a DMA controller according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of data transmission between a CPU and an interactive chip based on a DMA controller according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating the spatial distribution of DMA addresses according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating another memory control method for a DMA controller according to an embodiment of the present invention;
fig. 5 is a block diagram of a memory control device of a DMA controller according to an embodiment of the present invention;
fig. 6 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Conventional DMA operations require a processor to support mapping to a Memory decode cache (also referred to as a TLB) of an MMU (Memory Management Unit). MMUs are typically hardware circuits within the CPU or may be separate integrated circuits, and their primary function is to translate virtual addresses to physical addresses, typically by means of segment and page mechanisms. The TLB, colloquially referred to as a fast table, is part of the MMU, which caches page table entries (virtual to physical address mappings) for recently used data. It appears to speed up data (memory) access and reduce repetitive page table lookups.
Illustratively, the TLB entry and exit entries for an R4000 family MIPS CPU are shown in the following table:
entry item
| VPN | PageMask | ASID | G |
Export item
Wherein, in the TLB entry, the VPN represents the upper order of the virtual address (i.e., the virtual page address); the PageMask is used for controlling how many bits of the virtual address are used for comparing with the VPN and how many bits are added into the physical address after passing; ASID is used for marking a decoding process of converting a virtual address into a physical address, and belongs to a certain specific process space; if the G bit is set to 1, the match of the ASID is turned off, which causes the decode entry to be used for all process spaces. In the exit entry of the TLB, a PFN (Physical Frame Number) and some useful flags C, D, V are output. Where PFN represents finding the physical address matching the VPN via the TLB, where typically the lower 12 bits are removed, i.e. 4K page alignment. The C bit is a cache control bit, and indicates that there is a cache when the C bit is set to 0, and indicates that there is no cache when the C bit is set to 1. The D bit is a write control bit, is set to be 1 and indicates that data is allowed to be written into a corresponding page, and is set to be 0 and indicates that "dirty" and data is not allowed to be written into the corresponding page; when the V position is set to 0, it indicates that the corresponding entry is not usable. Obviously, in the prior art, the C valid bit in the TLB table entry is controlled to implement the consistency between the cache data and the memory data when the CPU reads and writes data. When the C bit in the TLB table is designed with a bug, the cache data and the memory data are likely to be inconsistent.
Fig. 1 is a flowchart illustrating a method for controlling a memory of a DMA controller according to an embodiment of the present invention, where the method can be executed by a memory control device of the DMA controller, where the device can be implemented by software and/or hardware, and can be generally integrated in an electronic device. As shown in fig. 1, the method includes:
In the embodiment of the present invention, before data transmission is performed through DMA, a CPU needs to apply for a DMA linked list and a DMA data storage area corresponding to the DMA linked list for a DMA controller, where the DMA data storage area is also a DMA address space, and is used to store read-write operation data during data transmission through DMA. And acquiring a DMA address space applied by the CPU for the DMA controller.
In the embodiment of the invention, the program address space of the CPU can be divided into a plurality of address areas, and when one address space is in different address areas, different attributes exist. For example, the program address space of a 32-bit CPU may be divided into a plurality of address regions of Ku, K0, K1, and K2, where:
k1: the CPU does not access the address in the K1 through the cache, namely the CPU does not access the data in the K1 through the cache, but directly accesses the data in the K1 through a non-cache uncache mode. K1 is also the only address space that will work properly at system restart.
K2: this address space can only be used in kernel mode and is translated by the MMU and is not accessed until the MMU is configured.
In the embodiment of the present invention, the address region K2 may be used as a kernel address space, and the address region K1 may be used as a user address space, where the kernel address space is a cache address space mapped by a data cache, that is, an address space that the CPU needs to indirectly access through a cache, and it can be understood that the kernel address space needs to be indirectly accessed by the CPU through the cache, and the CPU cannot directly access the kernel address space. The user address space is a non-cache address space which is not mapped by the data cache, that is, the CPU does not need to directly access the address space through the cache.
For example, after obtaining a DMA address space that the CPU applies for the DMA controller, it is determined whether the DMA address space belongs to a kernel address space, and if so, the DMA address space is converted from the kernel address space to a user address space.
Optionally, when the DMA address space belongs to the kernel address space, converting the DMA address space into the user address space, including: when the DMA address space belongs to a kernel address space, acquiring an address conversion rule between the kernel address space and a user address space; and converting the DMA address space into a user address space according to the address conversion rule. Optionally, the address translation rule includes: the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address; converting the DMA address space to a user address space according to the address conversion rule, comprising: determining an address offset between a starting DMA address of a DMA address space and the starting kernel address; and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
Illustratively, a DMA address space (i.e., a DMA data storage area) applied by the CPU for the DMA controller through the malloc function is 0xC0504000-0xD0504000, where the DMA address space belongs to a kernel address space (i.e., a K2 address area), and the DMA address space is converted from the kernel address space to a user address space according to an address conversion rule between the kernel address space and the user address space. The address translation rule between the kernel address space and the user address space may include: the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address. Taking the kernel address space as the address area of K2 and the user address space as the address area of K1, that is, the kernel address space is 0xC 0000000-0 xfffffffff and the user address space is 0xA 0000000-0 xfffffffff, the highest bit C in the starting kernel address 0xC0000000 in the kernel address space is correspondingly converted with the highest bit a in the starting user address 0xA0000000 in the user address space, and the other bits remain unchanged, that is, the starting kernel address 0xC0000000 is converted into 0xA 0000000. After obtaining the DMA address space, determining the address offset between the initial DMA address and the initial kernel address of the DMA address space, and then converting the DMA address space into the user address space according to the address offset and the address conversion rule. For example, if the starting DMA address of the obtained DMA address space 0xC0504000-0xD0504000 is 0xC0504000 and the address offset between the starting DMA address and the kernel address space is 0000504000, the starting DMA address is converted into 0xA0504000 according to the address offset and the above address conversion rule, and similarly, the ending DMA address 0xD0504000 can be converted into 0xB0504000, that is, the DMA address space 0xC0504000-0xD0504000 is converted into 0xA0504000-0xB0504000, that is, the DMA address space is converted from the address space belonging to the kernel to the user address space.
And 103, writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
In the embodiment of the invention, the DMA linked list can be generated in advance by the CPU according to the information such as the external storage address, the data size and the like of the data needing to be transmitted. The DMA linked list may be a unidirectional structure or a circular structure, and the DMA linked list may include a data source address and a destination address. And writing the converted DMA address space into the DMA linked list so that the DMA controller performs data transmission according to the DMA linked list, namely, when the DMA controller performs data transmission, storing the data of read-write operation in the DMA address space stored in the DMA linked list, namely, the converted DMA address space. Because the converted DMA address space belongs to the user address space, namely the non-cache address space which is not mapped by the data cache, the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively ensuring the consistency of the cache data and the memory data, but also avoiding the conflict between the DMA memory and the address space of other memories, and effectively ensuring the accuracy and the safety when the data transmission is carried out by the DMA.
Illustratively, the DMA linked list further includes control words such as Valid, Start, End, etc., a length Len of read and write data, and a space address Addr of read and write operations. When Valid is set to 1, the DMA linked list is indicated to be Valid, and the DMA controller can determine whether to write data into the address space Addr or read data from the address space Addr according to the start flag bit by scanning the DMA linked list, where the length of the read-write data is controlled by Len. Start is used to indicate the Start of data frame transmission and End is used to indicate the End of data frame transmission, wherein if the Start flag bit is not set to 1, data transmission is not triggered. Len denotes the length of reading and writing data through the DMA linked list. Addr denotes the address of the DMA controller for direct read and write operations. In the embodiment of the invention, when the converted DMA address space is written into the DMA linked list, the converted DMA address space is written into the Addr in the DMA linked list.
Fig. 2 is a schematic structural diagram of data transmission between a CPU and an interactive chip based on a DMA controller according to an embodiment of the present invention. As shown in fig. 2, the CPU manages the switch chip through a PCIe (Peripheral Component interconnect express) interface, and the DMA controller is disposed on the switch chip in the figure, and the DMA controller is used to realize transmission of a large amount of data between the CPU and the switch chip. In the embodiment of the present invention, after writing the converted DMA address space into the DMA linked list, the DMA linked list is stored in the external Memory, where the external Memory may be a DDR (Double Data Rate, Double-Rate Synchronous Dynamic Random Access Memory) (as shown in fig. 2), and of course, the external Memory may also be an SDRAM (Synchronous Dynamic Random Access Memory). Optionally, the storage space of the external memory may be divided into two parts, one part stores the DMA linked list, and the other part stores the data to be transmitted to the DMA memory, and addresses of the two parts of the storage space may be preset. After the DMA controller obtains the bus control right from the CPU, the DMA linked list can be read through the bus, and the data stored in the external memory is transmitted to the DMA memory (namely the converted DMA address space) according to the DMA linked list. The bus may be a PCIE bus, and certainly may also be a PCI (Peripheral Component Interconnect) bus. Optionally, after the data transmission corresponding to the DMA linked list is completed, the DMA controller may release the bus control right to the CPU.
The memory control method of the DMA controller provided by the invention comprises the following steps: obtaining a DMA address space applied by a Central Processing Unit (CPU) for a DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and the user address space is a non-cache address space which is not mapped by the data cache, so that the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency of cache data and memory data, but also solving the technical problem that the DMA memory and the CPU conflict with the address space of the memory applied by other applications, and effectively ensuring the correctness and safety when the data is transmitted by the DMA.
In some embodiments, obtaining the DMA address space that the central processing unit CPU applies for the DMA controller comprises: obtaining DMA memory configuration information; and allocating a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information. The advantage of this arrangement is that the problem of a large amount of memory fragments caused by frequent operations when dynamically allocating DMA memory can be effectively avoided.
In the embodiment of the present invention, the application of the DMA address space and the application of the non-DMA address space are random, that is, the application of the DMA memory and the non-DMA memory is random, which is easy to cause the situation that the DMA memory and the non-DMA memory cross each other, and the situation that the CPU cross accesses the DMA memory and the non-DMA memory when the CPU reads data in the DMA memory is easy to occur. Particularly, when the non-cache address space is used as the DMA memory according to the technical solution provided by the embodiment of the present invention, if the CPU reads the non-DMA memory data through the cache, the data in the non-cache address space is easily damaged when the DMA memory and the non-DMA memory are crossed. And also memory fragmentation if DMA memory is dynamically allocated frequently. Therefore, when the CPU applies for the DMA address space for the DMA controller, the DMA memory configuration information is obtained, and the DMA address space matched with the DMA memory configuration information is allocated to the DMA controller at one time according to the DMA memory configuration information. The DMA memory configuration information includes the size of the memory block and the number of the memory blocks. It can be understood that the DMA controller is allocated with the DMA memory matched with the size and the number at a time according to the number of blocks and the block size in the DMA memory configuration information, wherein the DMA memory is a large continuous address space.
For example, fig. 3 is a schematic diagram of a DMA address space distribution according to an embodiment of the present invention. In fig. 3, the left diagram is a schematic diagram of memory distribution of a DMA memory and a non-DMA memory randomly applied, and the right diagram is a schematic diagram of memory distribution of a DMA memory collectively applied. As shown in fig. 3, the memory 2 and the memory 5 are DMA memories that need to perform DMA operations, the memory 1, the memory 4, and the memory 6 are normal memories, i.e., non-DMA memories, and the memory 3 is a memory fragment. Obviously, based on the technical scheme provided by the embodiment of the invention, the DMA memory can be intensively applied to a continuous address space at one time, so that the problem of a large amount of memory fragments caused by frequent operation when the DMA memory is dynamically allocated can be effectively avoided, and the condition that a CPU (central processing unit) has cross access to the DMA memory and a non-DMA memory can be greatly reduced.
Certainly, after the DMA address space matched with the DMA memory configuration information is allocated to the DMA controller at one time according to the DMA memory configuration information, it may be further determined whether the continuous DMA address space applied in the set belongs to the kernel address space, if so, the DMA address space may be converted into the user address space, that is, the DMA address space applied by the DMA controller is the continuous non-cache address space allocated in the set at one time. The method not only can effectively ensure the consistency of the cache data and the memory data, but also solves the technical problem that when the CPU reads the non-DMA memory data through the cache, and the DMA memory and the non-DMA memory are crossed, the data in the non-cache address space is easy to damage.
Fig. 4 is a flowchart illustrating another memory control method for a DMA controller according to an embodiment of the present invention, where as shown in fig. 4, the method includes the following steps:
The DMA memory configuration information includes the size of the memory block and the number of the memory blocks.
And step 402, distributing a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
Wherein the address translation rule comprises: and the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address.
The kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache.
And step 406, writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
The invention provides a memory control method of a DMA controller, which further judges whether the continuous DMA address space applied in a centralized way belongs to a kernel address space or not after the DMA address space matched with the DMA memory configuration information is allocated to the DMA controller in one time according to the DMA memory configuration information, if so, the DMA address space can be converted into a user address space, namely the DMA address space applied by the DMA controller is the continuous non-cache address space allocated in one time in a centralized way. The method not only can effectively ensure the consistency of the cache data and the memory data, solve the technical problem that the address space of the memory applied by the DMA memory and the CPU for other applications generates conflict, effectively ensure the correctness and the safety when data transmission is carried out through the DMA, but also solve the technical problem that the CPU reads the non-DMA memory data through the cache, and the data in the non-cache address space is easily damaged when the DMA memory and the non-DMA memory are crossed, and simultaneously effectively avoid the problem that a large amount of memory fragments are caused by frequent operation when the DMA memory is dynamically distributed.
Fig. 5 is a block diagram of a memory control device of a DMA controller according to an embodiment of the present invention, where the memory control device may be implemented by software and/or hardware, and is generally integrated in an electronic device, and may perform DMA memory control by executing a memory control method of the DMA controller. As shown in fig. 5, the apparatus includes:
a DMA address space obtaining module 501, configured to obtain a DMA address space that is applied by a central processing unit CPU for the DMA controller;
an address space conversion module 502, configured to convert the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
an address space writing module 503, configured to write the converted DMA address space into a DMA linked list, so that the DMA controller performs data transmission according to the DMA linked list.
The invention provides a memory control device of a DMA controller, which acquires a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller; when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and the user address space is a non-cache address space which is not mapped by the data cache, so that the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency of cache data and memory data, but also solving the technical problem that the DMA memory and the CPU conflict with the address space of the memory applied by other applications, and effectively ensuring the correctness and safety when data transmission is carried out by the DMA.
Optionally, the address space converting module includes:
an address translation rule obtaining unit, configured to obtain an address translation rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
and the address space conversion unit is used for converting the DMA address space into a user address space according to the address conversion rule.
Optionally, the address translation rule includes:
the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address;
the address space conversion unit is configured to:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
Optionally, the DMA address space obtaining module is configured to:
obtaining DMA memory configuration information;
and allocating a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
Optionally, the DMA memory configuration information includes a size of the memory block and a number of the memory blocks.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a memory control method for a DMA controller, the method including:
obtaining a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller;
when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list.
Storage medium-any of various types of memory devices or storage devices. The term "storage medium" is intended to include: mounting media such as CD-ROM, floppy disk, or tape devices; computer system memory or random access memory such as DRAM, DDRRAM, SRAM, EDORAM, Lanbas (Rambus) RAM, etc.; non-volatile memory such as flash memory, magnetic media (e.g., hard disk or optical storage); registers or other similar types of memory elements, etc. The storage medium may also include other types of memory or combinations thereof. In addition, the storage medium may be located in a first computer system in which the program is executed, or may be located in a different second computer system connected to the first computer system through a network (such as the internet). The second computer system may provide program instructions to the first computer for execution. The term "storage medium" may include two or more storage media that may reside in different locations, such as in different computer systems that are connected by a network. The storage medium may store program instructions (e.g., embodied as a computer program) that are executable by one or more processors.
Of course, the storage medium provided by the embodiment of the present invention includes computer-executable instructions, and the computer-executable instructions are not limited to the above-described memory control operation of the DMA controller, and may also perform related operations in the memory control method of the DMA controller provided by any embodiment of the present invention.
The embodiment of the invention provides electronic equipment, and a memory control device of a DMA controller provided by the embodiment of the invention can be integrated in the electronic equipment. Fig. 6 is a block diagram of an electronic device according to an embodiment of the present invention. The electronic device 600 may include: the memory 601, the processor 602 and the computer program stored on the memory 601 and executable by the processor, when the processor 602 executes the computer program, the memory control method of the DMA controller according to the embodiment of the present invention is implemented. The electronic equipment provided by the embodiment of the invention acquires a DMA address space applied by a Central Processing Unit (CPU) for a DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and the user address space is a non-cache address space which is not mapped by the data cache, so that the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency of cache data and memory data, but also solving the technical problem that the DMA memory and the CPU conflict with the address space of the memory applied by other applications, and effectively ensuring the correctness and safety when data transmission is carried out by the DMA.
The memory control device, the storage medium, and the apparatus of the DMA controller provided in the above embodiments may execute the memory control method of the DMA controller provided in any embodiment of the present invention, and have functional modules and advantageous effects corresponding to the execution of the method. For the technical details not described in detail in the above embodiments, reference may be made to the memory control method of the DMA controller provided in any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for controlling a memory of a Direct Memory Access (DMA) controller, comprising:
obtaining a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller;
when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
and writing the converted DMA address space into a DMA linked list so that the DMA controller carries out data transmission according to the DMA linked list.
2. The method of claim 1, wherein translating the DMA address space into a user address space when the DMA address space belongs to a kernel address space comprises:
when the DMA address space belongs to a kernel address space, acquiring an address conversion rule between the kernel address space and a user address space;
and converting the DMA address space into a user address space according to the address conversion rule.
3. The method of claim 2, wherein the address translation rules comprise:
the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address;
converting the DMA address space to a user address space according to the address conversion rule, comprising:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
4. The method of claim 1, wherein obtaining the DMA address space that the CPU applies for the DMA controller comprises:
obtaining DMA memory configuration information;
and allocating a DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
5. The method of claim 4, wherein the DMA memory configuration information comprises a memory block size and a memory block number.
6. A memory control device of a DMA controller, comprising:
a DMA address space obtaining module for obtaining the DMA address space applied by the CPU for the DMA controller;
the address space conversion module is used for converting the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by a data cache, and the user address space is a non-cache address space not mapped by the data cache;
and the address space writing module is used for writing the converted DMA address space into a DMA linked list so as to enable the DMA controller to carry out data transmission according to the DMA linked list.
7. The apparatus of claim 6, wherein the address space translation module comprises:
an address translation rule obtaining unit, configured to obtain an address translation rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
and the address space conversion unit is used for converting the DMA address space into a user address space according to the address conversion rule.
8. The apparatus of claim 7, wherein the address translation rule comprises:
the highest bit of the initial kernel address of the kernel address space is correspondingly converted with the highest bit of the initial user address of the user address space, and other bits of the initial kernel address are kept unchanged, wherein the other bits of the initial kernel address comprise address bits except the highest bit of the initial kernel address;
the address space conversion unit is configured to:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
9. A computer-readable storage medium on which a computer program is stored, the program, when being executed by a processor, implementing a memory control method of a DMA controller according to any one of claims 1 to 5.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the memory control method of the DMA controller according to any one of claims 1 to 5 when executing the computer program.
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