CN111628078A - Synaptic transistor based on two-dimensional and three-dimensional perovskite composite structure and preparation method thereof - Google Patents

Abstract

The invention discloses a synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure and a manufacturing method thereof, which mainly solves the problem of inaccurate simulated synaptic behavior of the existing two-terminal perovskite synaptic device, which is bottom-up , comprising a glass substrate (1), a transparent oxide gate electrode (2), a perovskite region (3), a source electrode (4), a drain electrode (5) and an encapsulation protection layer (6). The ion medium layer adopts a three-dimensional perovskite material, and the conductive channel layer adopts a two-dimensional perovskite material; the electric field formed by the ion migration in the three-dimensional perovskite material is used to modulate the carrier transport in the two-dimensional perovskite material The gate of the device simulates the presynaptic membrane as the input terminal; the source and drain of the device simulates the post-synaptic membrane to read the post-synaptic current. The regulation of current can improve the accuracy of synaptic behavior simulation by synaptic transistors, which can be used to simulate human synapses and build neural network systems.

Description

Synaptic transistor based on two-dimensional and three-dimensional perovskite composite structure and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, in particular to a synaptic transistor and a preparation method thereof, which can be used to simulate human synapses and construct a neural network system.

Background technique

Emerging technologies such as artificial intelligence, big data, and the Internet of Things based on data information are profoundly changing human life and leading human beings into the era of intelligent information. However, in the face of the ever-expanding data information, traditional computers have long been unable to meet the needs of flexible processing and storage of large amounts of information due to the physical separation of computing units and memory, that is, the von Neumann bottleneck. How to improve the efficiency of storage and computing has become a difficult problem that humans have to face. In contrast, the highly parallel nonlinear information processing capability of the human brain shows obvious advantages, and can efficiently complete learning, perception, recognition, A series of complex processes such as memory and thinking. The key to such a powerful ability of the human brain lies in its low-energy, high-speed and miniaturized neural network system composed of tens of billions of neurons and hundreds of trillions of synapses, and synapses are the "core" of information transmission in this system. device". Therefore, the development of artificial synaptic devices and the construction of neurological systems have become urgent needs and inevitable choices in the age of intelligent information. It is of great research interest to fully simulate the function of biological synapses with a single device, but traditional Si-based CMOS technology cannot accomplish this challenge. In recent years, the continuous emergence of many new materials, new devices and new mechanisms has brought new opportunities for the development of artificial synaptic devices.

Among many new materials, due to their unique material properties, including tunable bandgap, easy control of charge carriers, ultra-flexible and low-temperature synthesis process <150 °C, and fast ion migration, the material with both electronic and ionic conductivity Perovskite materials have become important potential materials for artificial synaptic devices. The two-terminal memristor is the mainstream of the reported perovskite synaptic devices, and the conductive filament theory is the main resistance-switching mechanism, which simulates synaptic plasticity and learning and memory processes. However, the disadvantage of this structure is that the conductive path is single, and the operation of signal transmission and regulation cannot be performed at the same time, so the artificial synapse at both ends cannot realize signal transmission and learning at the same time. In contrast, the three-terminal structure field effect transistor can control the conduction channel between the source and drain through the gate voltage, thereby accurately controlling the source-drain current. Therefore, the conductive channel and the gate can be regarded as signal transmission and adjustment modules, respectively. Therefore, by virtue of the natural advantages of the device mechanism, the field effect transistor-type three-terminal synapse device will be in the mainstream position over the two-terminal structure device.

However, the current research on three-terminal transistor-based synaptic devices based on halide perovskite is very lacking, and there is no relevant report on three-terminal perovskite synaptic transistors at home and abroad. The main problem with three-terminal perovskite synaptic transistors is that the ion migration behavior in halide perovskite materials limits the device performance. For typical 3D organic-inorganic perovskite polycrystalline films, the lateral and interfacial carrier transport in transistor devices is particularly susceptible to the ubiquitous defects in the crystal plane states and grains of polycrystalline films. For example, due to the ionic semiconductor properties of perovskite, when a gate voltage of a certain strength is applied to a synaptic transistor, an ion shielding effect will be formed at the interface between the perovskite material and the dielectric, making the gate voltage ineffective and ineffective. Regulates the transport of carriers in the channel. Therefore, it is difficult to obtain high-performance three-terminal synaptic transistors directly by using three-dimensional perovskite polycrystalline thin films as channel materials.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure and a preparation method thereof in view of the deficiencies in the prior art, so as to effectively regulate the transport of carriers in the channel and obtain high-performance three-dimensional terminal synapse transistor.

The technical idea of the present invention is: on the basis of retaining the three-dimensional perovskite material as the gate as the input terminal, the two-dimensional perovskite material is additionally used as the conductive channel layer, so as to realize the signal transmission and signal adjustment at the same time. , to avoid the regulation failure phenomenon caused by only using the traditional three-dimensional perovskite structure.

According to the above-mentioned thinking, the technical scheme of the present invention is realized as follows:

A synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure, comprising from bottom to top: a glass substrate, a transparent oxide gate electrode, a perovskite region, a source electrode, a drain electrode, and an encapsulation protective layer, characterized in that :

The perovskite zone is divided into an ion medium layer, an ion barrier layer and a conductive channel layer;

The ionic medium layer adopts three-dimensional perovskite material, which is used as the gate of the synaptic transistor to simulate the presynaptic membrane of biological nerves;

The ion blocking layer adopts oxide material to prevent ions in the ion medium layer from flowing into the conductive channel layer;

The conductive channel layer adopts a two-dimensional perovskite material for effectively realizing signal transfer.

Preferably, the glass substrate adopts conductive glass with a light transmittance greater than 80%, so that light can enter the device from one side of the substrate.

Preferably, the transparent oxide gate is made of FTO or ITO material.

Preferably, the three-dimensional perovskite material used in the ion medium layer is organic-inorganic hybrid perovskite CH ₃ NH ₃ PbI ₃ or pure inorganic perovskite CsPbBr ₃ with a thickness of 300-500 nm.

Preferably, the oxide material used for the ion blocking layer is Al ₂ O ₃ or MoO ₃ with a thickness of 10-20 nm.

Preferably, the two-dimensional perovskite material used in the conductive channel layer is (PEA) ₂ PbBr ₄ or (PEA) ₂ SnI ₄ with a thickness of 100-300 nm.

Preferably, both the source electrode and the drain electrode are Au with a thickness of 100-200 nm, and the distance between the source electrode and the drain electrode is 50-200 μm.

Preferably, the encapsulation protection layer adopts polymethyl methacrylate PMMA with a thickness of 150-300 nm.

According to the above ideas, the present invention provides a method for fabricating a synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure, which is characterized in that it includes the following:

For the glass substrate coated with transparent oxide, use acetone, ethanol, and deionized water for ultrasonic cleaning for 15-20min in sequence, and dry with nitrogen;

The surface of the cleaned conductive glass is treated with ultraviolet ozone for 20-25min;

The precursor solution of pure inorganic _{perovskite CsPbBr3} or the precursor solution of organic-inorganic hybrid _{perovskite CH3NH3PbI3} was spin-coated on the surface of the conductive glass after UV ozone treatment, and annealed to obtain a thickness of 300- 500nm crystalline CsPbBr ₃ or crystalline CH ₃ NH ₃ PbI ₃ thin film ionic dielectric layer;

Growth of Al ₂ O ₃ or MoO ₃ ion blocking layer with a thickness of 10-20nm on the CsPbBr ₃ or CH ₃ NH ₃ PbI ₃ thin film ion medium layer;

Two-dimensional (PEA) ₂ PbBr ₄ single crystal powder was first evaporated on the Al ₂ O ₃ or MoO ₃ ion barrier layer by thermal evaporation process, and then annealed and crystallized at 120°C for 20 min to prepare a thickness of 100 -300nm two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer;

Au metal source electrodes with a thickness of 100-200 nm are deposited on the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer by thermal evaporation process;

Au metal drain electrodes with a thickness of 100-200 nm are deposited on the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer by thermal evaporation process;

On the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer, the Au metal source electrode layer and the Au metal drain electrode layer, polymethyl methacrylate PMMA with a thickness of 150-300 nm was spin-coated to protect the device.

Compared with the prior art, the present invention has the following advantages:

First, because the present invention adopts a three-terminal synapse structure, the conductive channel between the source and the drain is regulated by the gate voltage, and the source-drain current is precisely controlled, so the conductive channel and the gate can be regarded as signal transmission and signal adjustment respectively. module, and realize signal transmission and adjustment at the same time.

Second, the present invention can realize the rapid migration of ions due to the use of perovskite with adjustable band gap, easy regulation of carriers, ultra-flexibility, and both electronic and ionic conductivity as the core material of the three-terminal synapse structure.

Third, because the present invention adopts the three-dimensional perovskite layer as the ion medium layer and the two-dimensional perovskite layer as the conductive channel layer respectively, it can retain the strong ion mobility of the three-dimensional perovskite layer and the lateral conductivity and the lateral conductivity of the two-dimensional perovskite layer. On the basis of stability, the ionic dielectric layer and the conductive channel layer are spatially separated to avoid the ion shielding effect.

Fourth, due to the use of this two-dimensional and three-dimensional perovskite composite structure, the present invention can simultaneously realize the two processes of carrier transport and gate control to simulate the behavior of biological nerve synapses, and obtain artificial synaptic transistors, which can be achieved by Different ways of voltage excitation, light excitation, and thermal excitation control the ion migration in the ionic medium, thereby regulating the source-drain current.

Description of drawings

Figure 1 is a structural diagram of an existing biological synapse;

2 is a schematic structural diagram of a synaptic transistor of the present invention;

FIG. 3 is a schematic flow chart of the present invention for fabricating a synaptic transistor.

Detailed ways

The embodiments of the present invention are further described below in conjunction with the accompanying drawings and implementation cases:

Referring to Figure 1, the biological synapse refers to the site where two neurons or between neurons and effector cells contact each other and transmit information, which is mainly composed of presynaptic membrane, synaptic cleft and synapse. Aftertouch composition. The principle of action of biological synapses is: impulses are transmitted to the presynaptic membrane, and the presynaptic membrane opens the ion channel, so that the contained transmitters combine with part of the presynaptic membrane and enter the synaptic cleft; The transmitter then binds to the receptor in the postsynaptic membrane to complete the transmission of information.

This example is based on the information transmission process of biological synapses, simulating the three-terminal structure of biological synapses, using synaptic devices with two-dimensional and three-dimensional perovskite composite structures, and realizing the process of information regulation and transmission at the same time. It uses a three-dimensional perovskite material as the gate of the synaptic transistor, which is used to simulate the presynaptic membrane of biological nerves, and plays the role of stimulating pulse input in the information transmission; the source and drain electrodes of the synaptic transistor serve as the post-synaptic membrane, It is used to read postsynaptic currents; the electric field formed by ion migration in 3D perovskite materials is used to modulate carrier transport in 2D perovskite materials to simulate the propagation of neurotransmitters.

2, the present example is based on a two-dimensional and three-dimensional perovskite composite structure of a synaptic transistor, including a glass substrate 1, a transparent oxide gate electrode 2, a perovskite region 3, a source electrode 4, a drain electrode 5, and a package protective layer 6. The perovskite region 3 is divided into an ion medium layer 31, an ion barrier layer 32 and a conductive channel layer 33;

The conductive glass 1 serves as the bottom layer of the synaptic transistor, on which is the transparent oxide gate electrode layer 2, on the transparent oxide gate electrode layer 2 is the perovskite region 3, and the perovskite region from bottom to top is the ion medium layer 31, The ion blocking layer 32 and the conductive channel layer 33, the upper ends of the conductive channel layer 33 are located near the boundary at the source metal electrode layer 4 and the drain metal electrode layer 5, and the encapsulation protection layer 6 is located on the conductive channel layer 33 and the source-drain metal electrode layer 5. above the electrode layer.

The glass substrate 1 adopts conductive glass with light transmittance greater than 80%, so that light can enter the device from the substrate side; the transparent oxide gate 2 adopts FTO or ITO material; the ion medium layer 31 adopts the three-dimensional perovskite material , which is an organic-inorganic hybrid perovskite CH ₃ NH ₃ PbI ₃ with a thickness of 300-500 nm or a pure inorganic perovskite CsPbBr ₃ ; the oxide material used for the ion blocking layer 32 is Al with a thickness of 10-20 nm ₂ O ₃ or MoO ₃ ; the two-dimensional perovskite material used for the conductive channel layer 33 is (PEA) ₂ PbBr ₄ with a thickness of 100-300 nm; both the source electrode 4 and the drain electrode 5 are made of a thickness of 100-200 nm of Au, and the distance between the source electrode 4 and the drain electrode 5 is 50-200 μm; the encapsulation protection layer 6 is made of polymethyl methacrylate PMMA with a thickness of 150-300 nm.

Referring to Figure 3, the present example fabricates a method for making synaptic transistors based on two-dimensional and three-dimensional perovskite composite structures, and the following four embodiments are given:

Example 1: Fabrication of pure inorganic three-dimensional perovskite synaptic transistors with FTO oxide gate electrode and Al ₂ O ₃ ion blocking layer.

Step 1: Process the conductive substrate.

As shown in Fig. 3a, the conductive substrate is composed of a substrate including a glass substrate and a FTO transparent oxide gate electrode. The conductive substrate is first ultrasonically cleaned with acetone, ethanol, and deionized water for 15 minutes, and then cleaned with acetone, ethanol, and deionized water. Blow dry with high-purity nitrogen; then, the surface of the cleaned conductive substrate is subjected to UV-ozone treatment for 20 minutes to obtain the gate electrode of the synaptic transistor.

Step 2: Growing the perovskite region.

2.1) As shown in Figure 3b, on the surface of the conductive substrate after UV ozone treatment, spin-coat the DMF solution of PbBr ₂ for 30 s at a concentration of 1 mol/L and a rotation speed of 2000 r/min, and carry out the process at a temperature of 90 °C for a long time. After thermal annealing for 1 h, a PbBr ₂ layer was obtained; then, a methanol solution of CsBr ₂ was spin-coated on the PbBr ₂ layer under the conditions of a concentration of 0.07 mol/L and a rotation speed of 2000 r/min for 30 s, and the temperature was 250 °C for 5 min. Thermal annealing, repeated 6 times, to obtain a three-dimensional CsPbBr ₃ ionic dielectric layer with a thickness of 300 nm;

2.2) As shown in Fig. 3c, the Al ₂ O ₃ ion barrier layer is grown on the ion dielectric layer by the atomic layer deposition process, that is, the Al ₂ with a thickness of 10 nm is grown under the conditions of a temperature of 300 °C and a cycle number of 250 O ₃ ion blocking layer;

2.3) As shown in Figure 3d, two-dimensional (PEA) ₂ PbBr ₄ single crystal powder was first evaporated on the ion barrier layer by thermal evaporation process, that is, under the conditions of evaporation temperature of 200 °C and evaporation rate of 0.05 nm/s Two-dimensional (PEA) ₂ PbBr ₄ was grown; then the two-dimensional (PEA) ₂ PbBr ₄ was annealed and crystallized at a temperature of 120 °C and a duration of 20 min to obtain a two-dimensional (PEA) ₂ PbBr ₄ conductive channel with a thickness of 100 nm Floor.

Step 3: Growing source and drain electrodes.

As shown in Figure 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation process, and under the condition of evaporation rate of 0.1 nm/s, source and drain metal electrodes with a thickness of 100 nm are grown to keep the The source-drain spacing is 100 μm.

Step 4: Synaptic Transistor Packaging.

As shown in Figure 3f, a chlorobenzene solution of PMMA was spin-coated on the conductive channel layer and the source-drain metal layer for 60 s at a concentration of 10 mg/mL and a rotation speed of 2000 r/min to generate a package protective layer with a thickness of 150 nm. Encapsulation protection. Completed the fabrication of synaptic transistors based on two-dimensional and three-dimensional perovskite composite structures.

Example 2: Fabrication of organic-inorganic hybrid three-dimensional perovskite synaptic transistor with ITO oxide gate electrode and MoO ₃ ion blocking layer.

Step 1: Treat the conductive substrate.

As shown in Fig. 3a, the conductive substrate is composed of a substrate including a glass substrate and an ITO transparent oxide gate electrode. The conductive substrate is first ultrasonically cleaned with acetone, ethanol, and deionized water for 15 minutes, and then cleaned with acetone, ethanol, and deionized water. Blow dry with high-purity nitrogen; then, the surface of the cleaned conductive substrate is subjected to UV-ozone treatment for 20 minutes to obtain the gate electrode of the synaptic transistor.

Step 2: Growing the perovskite region.

2a) As shown in Figure 3b, on the surface of the conductive substrate after UV ozone treatment, spin-coating a DMF solution of PbI ₂ for 45 s under the conditions of a concentration of 1.4 mol/L and a rotational speed of 3000 r/min to obtain a PbI ₂ layer; The isopropanol solution of CH ₃ NH ₃ I was spin-coated on the PbI ₂ layer at a concentration of 100 mg/mL and a rotation speed of 3000 r/min for 45 s, and then thermally annealed for 10 min under a nitrogen atmosphere at a temperature of 100 °C to obtain A three-dimensional CH ₃ NH ₃ PbI ₃ ion dielectric layer with a thickness of 400 nm;

2b) As shown in Fig. 3c, a MoO ₃ ion barrier layer was grown on the ion medium layer using a thermal evaporation process, and the MoO ₃ ions with a thickness of 15 nm were grown under the conditions of an evaporation temperature of 650 °C and an evaporation rate of 0.05 nm/s. barrier layer;

2c) As shown in Figure 3d, two-dimensional (PEA) ₂ PbBr ₄ single crystal powder was first evaporated on the ion barrier layer by thermal evaporation process, that is, under the conditions of evaporation temperature of 200 °C and evaporation rate of 0.05 nm/s Two-dimensional (PEA) ₂ PbBr ₄ was grown; then the two-dimensional (PEA) ₂ PbBr ₄ was annealed and crystallized at a temperature of 120 °C and a duration of 20 min to obtain a two-dimensional (PEA) ₂ PbBr ₄ conductive channel with a thickness of 200 nm Floor.

Step 3: Growing source and drain electrodes.

As shown in Figure 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation process, and under the condition of evaporation rate of 0.1 nm/s, source and drain metal electrodes with a thickness of 150 nm are grown to keep the The source-drain spacing is 100 μm.

Step 4: Packaging of synaptic transistors.

As shown in Figure 3f, a chlorobenzene solution of PMMA was spin-coated on the conductive channel layer and the source-drain metal layer at a concentration of 10 mg/mL and a rotation speed of 2000 r/min for 60 s to generate a package protective layer with a thickness of 200 nm. Package protection. Completed the fabrication of synaptic transistors based on two-dimensional and three-dimensional perovskite composite structures.

Example 3: Fabrication of organic-inorganic hybrid three-dimensional perovskite synaptic transistor with FTO oxide gate electrode and Al ₂ O ₃ ion blocking layer.

Step A: Treating the Conductive Substrate.

The specific implementation of this step is the same as that of step 1 in Embodiment 1.

Step B: Growing the perovskite region.

B1) As shown in Figure 3b, on the surface of the conductive substrate after UV ozone treatment, spin-coating a DMF solution of PbI ₂ for 45 s under the conditions of a concentration of 1.4 mol/L and a rotational speed of 3000 r/min to obtain a PbI ₂ layer; The isopropanol solution of CH ₃ NH ₃ I was spin-coated on the PbI ₂ layer at a concentration of 100 mg/mL and a rotation speed of 3000 r/min for 45 s, and then thermally annealed for 10 min under a nitrogen atmosphere at a temperature of 100 °C to obtain A three-dimensional CH ₃ NH ₃ PbI ₃ ion dielectric layer with a thickness of 500 nm;

B2) As shown in Figure 3c, an Al ₂ O ₃ ion barrier layer is grown on the ion dielectric layer by atomic layer deposition, that is, under the conditions of a temperature of 300 °C and a cycle number of 250, Al ₂ with a thickness of 20 nm is grown O ₃ ion blocking layer;

B3) As shown in Figure 3d, two-dimensional (PEA) ₂ PbBr ₄ single crystal powder was first evaporated on the ion barrier layer by thermal evaporation process, that is, under the conditions of evaporation temperature of 200 °C and evaporation rate of 0.05 nm/s Two-dimensional (PEA) ₂ PbBr ₄ was grown; then the two-dimensional (PEA) ₂ PbBr ₄ was annealed and crystallized at a temperature of 120 °C and a duration of 20 min to obtain a two-dimensional (PEA) ₂ PbBr ₄ conductive channel with a thickness of 300 nm Floor.

Step 3: Growing source and drain electrodes.

As shown in Figure 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation process, and under the condition of evaporation rate of 0.1 nm/s, source and drain metal electrodes with a thickness of 200 nm are grown, keeping the The source-drain spacing is 100 μm.

Step 4: Synaptic Transistor Packaging.

As shown in Figure 3f, a chlorobenzene solution of PMMA was spin-coated on the conductive channel layer and the source-drain metal layer at a concentration of 10 mg/mL and a rotational speed of 2000 r/min for 60 s to generate a package protective layer with a thickness of 300 nm. Package protection. Completed the fabrication of synaptic transistors based on two-dimensional and three-dimensional perovskite composite structures.

Example 4: Fabrication of pure inorganic three-dimensional perovskite synaptic transistors with ITO oxide gate electrodes and MoO ₃ ion blocking layers.

Step 1: Process the conductive substrate.

The specific implementation of this step is the same as that of step 1 in Embodiment 2

The second step: growing the perovskite region.

First, as shown in Fig. 3b, on the surface of the conductive substrate after UV ozone treatment, the DMF solution of PbBr ₂ was spin-coated at a concentration of 1 mol/L and a rotation speed of 2000 r/min for 30 s, and was carried out at a temperature of 90 °C for a long time. After thermal annealing for 1 h, a PbBr ₂ layer was obtained; then, a methanol solution of CsBr ₂ was spin-coated on the PbBr ₂ layer under the conditions of a concentration of 0.07 mol/L and a rotation speed of 2000 r/min for 30 s, and the temperature was 250 °C for 5 min. Thermal annealing, repeated 6 times, to obtain a three-dimensional CsPbBr ₃ ionic dielectric layer with a thickness of 450 nm;

Next, as shown in Figure 3c, a MoO ₃ ion barrier layer was grown on the ion medium layer by thermal evaporation process, and the MoO ₃ ions with a thickness of 15 nm were grown under the conditions of an evaporation temperature of 650 °C and an evaporation rate of 0.05 nm/s. barrier layer;

Then, as shown in Figure 3d, two-dimensional (PEA) ₂ PbBr ₄ single crystal powder was first evaporated on the ion barrier layer by thermal evaporation process, that is, under the conditions of evaporation temperature of 200 °C and evaporation rate of 0.05 nm/s Two-dimensional (PEA) ₂ PbBr ₄ was grown; then the two-dimensional (PEA) ₂ PbBr ₄ was annealed and crystallized at a temperature of 120 °C and a duration of 20 min to obtain a two-dimensional (PEA) ₂ PbBr ₄ conductive channel with a thickness of 150 nm Floor.

The third step: growing the source and drain electrodes.

As shown in Figure 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation process, and under the condition of evaporation rate of 0.1 nm/s, source and drain metal electrodes with a thickness of 180 nm are grown, keeping the The source-drain spacing is 100 μm.

Step 4: Synaptic Transistor Packaging.

As shown in Figure 3f, a chlorobenzene solution of PMMA was spin-coated on the conductive channel layer and the source-drain metal layer at a concentration of 10 mg/mL and a rotational speed of 2000 r/min for 60 s to generate a package protective layer with a thickness of 250 nm. Package protection. Completed the fabrication of synaptic transistors based on two-dimensional and three-dimensional perovskite composite structures.

The above descriptions are only four specific examples of the present invention. For those skilled in the art, after understanding the content and principles of the present invention, they can carry out the method according to the present invention without departing from the principles and scope of the present invention. Various corrections and changes in form and details, but these corrections and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims (12)

1. A synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure, comprising from bottom to top: a glass substrate (1), a transparent oxide gate electrode (2), a perovskite region (3), a source electrode (4), drain electrode (5), encapsulation protective layer (6), it is characterized in that: The perovskite region (3) is divided into an ion medium layer (31), an ion barrier layer (32) and a conductive channel layer (33); The ionic medium layer (31) adopts a three-dimensional perovskite material, which is used as the gate of the synaptic transistor to simulate the presynaptic membrane of biological nerves; The ion blocking layer (32) adopts oxide material to prevent ions in the ion medium layer (31) from flowing into the conductive channel layer (33); The conductive channel layer (33) adopts a two-dimensional perovskite material for effectively realizing signal transfer. 2. The transistor according to claim 1, characterized in that the glass substrate (1) is made of conductive glass with a light transmittance greater than 80%, so that light can enter the device from one side of the substrate. 3. The transistor according to claim 1, wherein the transparent oxide gate electrode (2) is made of FTO or ITO material. 4. The transistor according to claim 1, wherein: The three-dimensional perovskite material used in the ion medium layer (31) is organic-inorganic hybrid perovskite CH ₃ NH ₃ PbI ₃ or pure inorganic perovskite CsPbBr ₃ with a thickness of 300-500 nm. The oxide material used in the ion blocking layer (32) is Al ₂ O ₃ or MoO ₃ with a thickness of 10-20 nm; The two-dimensional perovskite material used in the conductive channel layer (33) is (PEA) ₂ PbBr ₄ with a thickness of 100-300 nm. 5. The transistor according to claim 1, wherein the source electrode (4) and the drain electrode (5) are Au with a thickness of 100-200 nm, and between the source electrode (4) and the drain electrode (5) The pitch is 50-200 μm. 6 . The transistor according to claim 1 , wherein the encapsulation protection layer ( 6 ) adopts polymethyl methacrylate (PMMA) with a thickness of 150-300 nm. 7 . 7. a method for making a synaptic transistor based on two-dimensional and three-dimensional perovskite composite structure, is characterized in that, comprises as follows: 1) For the glass substrate coated with transparent oxide, use acetone, ethanol, and deionized water to carry out ultrasonic cleaning for 15-20min in turn, and dry with nitrogen; 2) carrying out 20-25min ultraviolet ozone treatment on the cleaned conductive glass surface to form the gate electrode of the synaptic transistor; ₃ ) The precursor solution of pure inorganic _{perovskite CsPbBr3} or the precursor solution of organic-inorganic hybrid _perovskite CH3NH3PbI3 was spin-coated on the surface of the conductive glass after UV ozone treatment, and annealed to obtain a thickness of 300-500nm crystalline CsPbBr ₃ or crystalline CH ₃ NH ₃ PbI ₃ thin film ion medium layer; 4) A 10-20nm thick Al ₂ O ₃ or MoO ₃ ion blocking layer is grown on the CsPbBr ₃ or CH ₃ NH ₃ PbI ₃ thin film ion dielectric layer; 5) On the Al ₂ O ₃ or MoO ₃ ion barrier layer, firstly use the thermal evaporation process to evaporate two-dimensional (PEA) ₂ PbBr ₄ single crystal powder, and perform annealing and crystallization at 120 ° C for 20 min to prepare a thickness of is a two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer of 100-300 nm; 6) Au metal source electrode with a thickness of 100-200 nm is deposited on the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer using a thermal evaporation process: 7) Au metal drain electrodes with a thickness of 100-200 nm are deposited on the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer using a thermal evaporation process: 8) Spin coating polymethyl methacrylate PMMA with a thickness of 150-300 nm on the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer, Au metal source electrode layer and Au metal drain electrode layer to protect the device. 8. The method according to claim 7, wherein the 3) spin-coating the precursor solution of pure inorganic perovskite CsPbBr ₃ , and annealing, is achieved as follows: First, the DMF solution of PbBr ₂ was spin-coated on the surface of the FTO conductive glass after UV ozone treatment at a concentration of 1 mol/L, a rotational speed of 2000 r/min, and a time of 30 s, and then was thermally annealed at 90 °C for 1 h to obtain PbBr ₂ layers; Then, a methanol solution of CsBr ₂ was spin-coated on the PbBr ₂ layer under the conditions of a concentration of 0.07 mol/L, a rotational speed of 2000 r/min, and a time of 30 s, and thermal annealing was performed at 250 °C for 5 min, repeated 6 times, to obtain A three-dimensional CsPbBr ₃ ionic dielectric layer with a thickness of 300-500 nm. 9. The method according to claim 7, characterized in that in 3), spin-coating organic-inorganic hybrid perovskite CH ₃ NH ₃ PbI ₃ and annealing is performed as follows: In the first step, the DMF solution of PbI ₂ was spin-coated on the surface of the ITO conductive glass after UV ozone treatment with a concentration of 1.4 mol/L, a rotational speed of 3000 r/min, and a time of 45 s to obtain a PbI ₂ layer; In the second step, the isopropanol solution of CH ₃ NH ₃ I was spin-coated on the PbI ₂ layer at a concentration of 100 mg/mL, a rotation speed of 3000 r/min and a time of 45 s; A three-dimensional CH ₃ NH ₃ PbI ₃ ionic dielectric layer with a thickness of 300-500 nm was obtained. 10. The method according to claim 7, wherein the process conditions for growing the Al ₂ O ₃ or MoO ₃ ion barrier layer in the 4) are as follows: The growth of Al ₂ O ₃ is by the ozone method, the temperature is 300 ℃, and the number of cycles is 250; MoO3 was grown by thermal evaporation with a temperature _of 650 °C and an evaporation rate of 0.05 nm/s. 11. method according to claim 7 is characterized in that, the thermal evaporation technique adopted in described 5), 6), 7) is as follows respectively: The thermal evaporation process for growing the two-dimensional (PEA) ₂ PbBr ₄ conductive channel layer in 5) is as follows: the evaporation temperature is 200° C. and the evaporation rate is 0.05 nm/s; The thermal evaporation process for growing the source electrode of the Au material in 6) is as follows: the evaporation rate is 0.1 nm/s; The thermal evaporation process for growing the drain electrode of the Au material in 7) is as follows: the evaporation rate is 0.1 nm/s. 12. method according to claim 7, is characterized in that, described 8) the technological condition of spin coating encapsulation protective layer is: polymethyl methacrylate PMMA concentration is 10mg/mL, rotating speed is 2000r/min, time for 60s.

Images