CN111600598A - Sync counter - Google Patents

Abstract

The invention provides a synchronous counter. The synchronous counter includes: a logic circuit, at least two number selection circuits, and at least two D flip-flops, wherein the at least two number selection circuits are in one-to-one correspondence with the at least two D flip-flops; the logic circuit The signal input terminal of the logic circuit is connected to the output terminal of each D flip-flop, the first signal output terminal of the logic circuit is connected to the first input terminal of each digital selection circuit, and the second signal output terminal of the logic circuit is connected to each digital selection circuit. The address selection input terminal of the digital selection circuit is connected to each other; for the corresponding digital selection circuit and D flip-flop, the output terminal of the digital selection circuit is connected to the signal input terminal of the D flip-flop; the second input terminal of each digital selection circuit is used to receive the synchronous counter The preset level signal of each D flip-flop is the input end of the synchronous counter, and the second signal output end of the logic circuit is the output end of the synchronous counter. The supply voltage of the synchronous counter provided by the present invention is lower.

Description

Sync counter

technical field

The invention belongs to the technical field of circuit design, and more particularly, relates to a synchronous counter.

Background technique

The counter circuit is one of the basic circuits of integrated circuit design. According to the different clock pulse input methods, it can be divided into synchronous counter and asynchronous counter. The circuit designed by the synchronous counter has good stability. At present, many integrated circuits are designed using the synchronous counter circuit.

However, with the popularization and application of integrated circuits, higher requirements are also placed on the performance of synchronous counters in integrated circuits. Therefore, how to provide synchronous counters with higher performance has become an urgent problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a synchronous counter with a lower power supply voltage.

In order to achieve the above object, the technical solution adopted in the present invention is to provide a synchronous counter, comprising:

a logic circuit, at least two digital selection circuits, and at least two D flip-flops, the at least two digital selection circuits are in one-to-one correspondence with the at least two D flip-flops;

The signal input terminal of the logic circuit is connected to the output terminal of each D flip-flop, the first signal output terminal of the logic circuit is connected to the first input terminal of each digital selection circuit, and the second signal output terminal of the logic circuit is connected to the first input terminal of each digital selection circuit. The output terminal is connected with the address selection input terminal of each digital selection circuit;

For the corresponding digital selection circuit and D flip-flop, the output end of the digital selection circuit is connected with the signal input end of the D flip-flop;

The second input terminal of each digital selection circuit is used to receive the preset level signal of the synchronous counter, the clock input terminal of each D flip-flop is the input terminal of the synchronous counter, and the second signal output terminal of the logic circuit is the synchronous counter input terminal. output of the counter.

Optionally, each digital selection circuit includes a first bias resistor, a second bias resistor, a third bias resistor, a first digital selection transistor, a second digital selection transistor, a third digital selection transistor, and a fourth digital selection transistor. a transistor, a fifth digital selection transistor, a sixth digital selection transistor, and a seventh digital selection transistor;

The first end of the first bias resistor and the first end of the second bias resistor are connected to a power supply voltage;

The second end of the first bias resistor is connected to the collector of the first digital selection transistor and the collector of the fourth digital selection transistor, and the second end of the second bias resistor is connected to the first digital selection transistor. The collector of the second digital selection transistor and the collector of the third digital selection transistor are connected;

The emitter of the first digital selection transistor is connected to the emitter of the second digital selection transistor and the collector of the fifth digital selection transistor, and the emitter of the third digital selection transistor is connected to the fourth digital selection transistor. The emitter of the selection transistor and the collector of the sixth digital selection transistor are connected;

The emitter of the fifth digital selection transistor is connected to the emitter of the sixth digital selection transistor and the collector of the seventh digital selection transistor;

The base of the seventh digital selection transistor is connected to the DC bias voltage, the emitter of the seventh digital selection transistor is connected to the first end of the third bias resistor, and the second end of the third bias resistor is connected. terminal grounding;

The base of the first digital selection transistor is the second input end of the digital selection circuit, which is used to receive the preset level signal of the synchronous counter, and the base of the second digital selection transistor is used to receive the first level signal; Wherein, the first level signal is the inverted signal of the preset level signal of the synchronization counter;

The base of the third digital selection transistor is the first input end of the digital selection circuit for receiving the first control signal of the logic circuit, and the base of the fourth digital selection transistor is used for receiving the second level signal; wherein , the second level signal is the inverted signal of the first control signal of the logic circuit;

The base of the fifth digital selection transistor is the address selection input end of the digital selection circuit, which is used to receive the second control signal of the logic circuit, and the base of the sixth digital selection transistor is used to receive the third level signal; wherein , the third level signal is the inverted signal of the second control signal of the logic circuit;

The collector of the second digital selection transistor is the output end of the digital selection circuit.

Optionally, the first digital selection transistor, the second digital selection transistor, the third digital selection transistor, the fourth digital selection transistor, the fifth digital selection transistor, the sixth digital selection transistor and the seventh digital selection transistor are bipolar. type transistor.

Optionally, the D flip-flop includes a first latch and a second latch, and the first latch and the second latch have the same circuit structure and their ports correspond to each other;

The first bias terminal of the first latch and the first bias terminal of the second latch are connected to the power supply voltage in common, and the second bias terminal of the first latch and the second latch The second bias terminal of the latch is commonly connected to the DC bias voltage;

The first input terminal of the first latch is the signal input terminal of the D flip-flop, which is used to receive the input signal of the digital selection circuit, and the second input terminal of the first latch is used to receive the digital selection circuit. The inverted signal of the input signal of the circuit;

The second output end of the second latch is the output end of the D flip-flop, which is used to output the state signal to the logic circuit, and the first output end of the second latch is used to output the inverse of the state signal. phase signal;

The third input terminal of the first latch is the clock input terminal of the D flip-flop for receiving the clock signal, and the fourth input terminal of the first latch is used for receiving the inverted signal of the clock signal ;

The first output terminal of the first latch is connected to the second input terminal of the second latch, and the second output terminal of the first latch is connected to the first output terminal of the second latch. The input terminal is connected, the third input terminal of the first latch is connected to the fourth input terminal of the second latch, and the fourth input terminal of the first latch is connected to the second latch connected to the third input of the device.

Optionally, the first latch includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth a transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

The first end of the first resistor, the first end of the second resistor, the collector of the eighth transistor, and the collector of the ninth transistor are commonly connected to the power supply voltage;

The second end of the first resistor is connected to the collector of the first transistor, the collector of the third transistor, the base of the fourth transistor, and the base of the ninth transistor, and the second end of the second resistor is connected to the first transistor. The collector of the second transistor, the base of the third transistor, the collector of the fourth transistor, and the base of the eighth transistor are connected;

The base of the first transistor is the first input end of the first latch, and the base of the second transistor is the second input end of the first latch;

The emitter of the first transistor is connected to the emitter of the second transistor and the collector of the fifth transistor, and the emitter of the third transistor is connected to the emitter of the fourth transistor and the sixth transistor. collector connection;

The base of the fifth transistor is the third input end of the first latch, and the base of the sixth transistor is the fourth input end of the first latch;

The emitter of the fifth transistor is connected to the emitter of the sixth transistor and the collector of the seventh transistor;

The base of the seventh transistor, the base of the tenth transistor, and the base of the eleventh transistor are connected to the DC bias voltage in common;

The emitter of the seventh transistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; the emitter of the eighth transistor is the first output end of the first latch, the eighth The emitter of the transistor is connected to the collector of the tenth transistor, the emitter of the tenth transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the emitter of the ninth transistor is the first The second output end of the latch, the emitter of the ninth transistor is connected to the collector of the eleventh transistor, the emitter of the eleventh transistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected terminal to ground.

Optionally, the second latch includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. transistors, sixteenth transistors, seventeenth transistors, eighteenth transistors, nineteenth transistors, twentieth transistors, twenty-first transistors, and twenty-second transistors;

The first end of the sixth resistor, the first end of the seventh resistor, the collector of the nineteenth transistor, and the collector of the twentieth transistor are commonly connected to the power supply voltage;

The second end of the sixth resistor is connected to the collector of the twelfth transistor, the collector of the fourteenth transistor, the base of the fifteenth transistor, and the base of the twentieth transistor. The two terminals are connected to the collector of the thirteenth transistor, the base of the fourteenth transistor, the collector of the fifteenth transistor, and the base of the nineteenth transistor;

The base of the twelfth transistor is the first input end of the second latch, and the base of the thirteenth transistor is the second input end of the second latch;

The emitter of the twelfth transistor is connected to the emitter of the thirteenth transistor and the collector of the sixteenth transistor, and the emitter of the fourteenth transistor is connected to the emitter of the fifteenth transistor and the collector of the sixteenth transistor. the collector connection of the seventeenth transistor;

The base of the sixteenth transistor is the third input end of the second latch, and the base of the seventeenth transistor is the fourth input end of the second latch;

The emitter of the sixteenth transistor is connected to the emitter of the seventeenth transistor and the collector of the eighteenth transistor;

The base of the eighteenth transistor, the base of the twenty-first transistor, and the base of the twenty-second transistor are connected to the DC bias voltage in common;

The emitter of the eighteenth transistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is grounded; the emitter of the nineteenth transistor is the first output end of the second latch, and the The emitter of the nineteenth transistor is connected to the collector of the twenty-first transistor, the emitter of the twenty-first transistor is connected to the first end of the ninth resistor, and the second end of the ninth resistor is grounded; The emitter of the twentieth transistor is the second output terminal of the second latch, the emitter of the twentieth transistor is connected to the collector of the twenty-second transistor, and the emitter of the twenty-second transistor is connected to the connection of the tenth resistor. The first end is connected, and the second end of the tenth resistor is grounded.

Optionally, the transistors in the D flip-flops are bipolar transistors.

The beneficial effects of the synchronous counter provided by the present invention are as follows: the present invention realizes the setting and counting functions through the D flip-flop and the number selection circuit, effectively reduces the number of circuit stages of the transistors in the D flip-flop, and reduces the power supply voltage of the D flip-flop, This in turn reduces the supply voltage of the synchronous counter.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the present invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a schematic structural diagram of a synchronization counter provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a digital selection circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a D flip-flop provided by an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Please refer to FIG. 1 , which is a schematic structural diagram of a synchronous counter provided by an embodiment of the present invention (taking five digital selection circuits and five D flip-flops as an example). The synchronization counter includes:

The logic circuit 10 , at least two digital selection circuits 20 , at least two D flip-flops 30 , and the at least two digital selection circuits 20 are in one-to-one correspondence with the at least two D flip-flops 30 .

The signal input terminal of the logic circuit 10 is connected to the output terminal of each D flip-flop 30, the first signal output terminal of the logic circuit 10 is connected to the first input terminal of each digital selection circuit 20, and the second signal output terminal of the logic circuit 10 is output The terminal is connected to the address selection input terminal of each digital selection circuit 20 .

For the digital selection circuit 20 and the D flip-flop 30 corresponding to each other, the output terminal of the digital selection circuit 20 is connected to the signal input terminal of the D flip-flop 30 .

The second input terminal of each digital selection circuit 20 is used to receive the preset level signal of the synchronous counter, the clock input terminal of each D flip-flop 30 is the input terminal of the synchronous counter, and the second signal output terminal of the logic circuit 10 is Synchronous counter output.

In this embodiment, the function of setting and subtracting is realized by the combination of the number selection circuit 20 and the D flip-flop 30, which effectively reduces the circuit stages of the transistors in the D flip-flop 30 and reduces the power supply voltage of the D flip-flop 30. This in turn reduces the supply voltage of the synchronous counter.

In this embodiment, the output terminal of the D flip-flop 30 is the Q terminal of the D flip-flop 30 , and the port connecting the Q terminal of the D flip-flop 30 with the logic circuit 10 is the signal input terminal of the logic circuit 10 . The first input terminal of the digital selection circuit 20 is the B terminal of the digital selection circuit 20 , and the port connecting the B terminal of the digital selection circuit 20 to the logic circuit 10 is the first signal output terminal of the logic circuit 10 . The address selection input terminal of the digital selection circuit 20 is the S terminal of the digital selection circuit 20, and the port where the S terminal of the digital selection circuit 20 is connected to the logic circuit 10 is the second signal output terminal of the logic circuit 10. The S terminal receives the data from the second signal output terminal of the logic circuit 10, and is used to determine that the synchronous counter implements the setting or counting function.

In this embodiment, the output terminal of the digital selection circuit 20 is the F terminal of the digital selection circuit 20, and the signal input terminal of the D flip-flop 30 is the D terminal of the D flip-flop.

In this embodiment, the second input terminal of each digital selection circuit 20 is used to receive the preset level signal of the synchronous counter, and the preset level signal is the initial data of the synchronous counter, which is used to determine the score of the synchronous counter. frequency ratio.

In this embodiment, the clock input terminal of the D flip-flop 30 is the CLK terminal of the D flip-flop 30, and the clock input terminal of the D flip-flop 30 is also the input terminal of the synchronous counter for receiving the external input signal f _IN . The second signal output terminal of the logic circuit 10 is the output terminal of the synchronous counter for outputting the level signal f _OUT .

In this embodiment, the logic circuit 10 is configured to determine the next state Q _n ^* of the D flip-flop 30 according to the current state Q _n of the D flip-flop 30 . In this embodiment, the function of the logic circuit 10 is described in detail by taking a 5-bit synchronous counter as an example:

First, the frequency division ratio is 2 to 32 through the five-bit synchronous counter. The state table of the five-bit synchronous counter is shown in Table 1. In Table 1, Q _n (n=0...4) is the output data of the D flip-flop.

Table 1 Status table of five-bit synchronous counter

In Table 1, Q ₀ to Q ₄ represent the output data of 5 D flip-flops in the counter, with a total of 32 states. Counting down from 11111 to 00000, the output of the synchronous counter is high level only when it is 00000, and the rest state is low level, realizing frequency division by 32. According to Table 1, it can be determined that the characteristic equation of the synchronous counter is: Q ₀ ^* =Q ₀ ^′ . Q ₁ ^* =Q ₀ ⊙Q ₁ . Q ₂ ^* =(Q ₀ +Q ₁ )⊙Q ₂ . Q ₃ ^* =(Q ₀ +Q ₁ +Q ₂ )⊙Q ₃ . Q ₄ ^* =(Q ₀ +Q ₁ +Q ₂ +Q ₃ )⊙Q ₄ . Wherein Qn _{* is} the next state of ^Qn , ⊙ is expressed as the same or, the function of the logic circuit 10 _is to convert the current state Qn of the D flip-flop to the next state Q of the D flip-flop according to the characteristic equation of the synchronous counter _n ^* .

In this embodiment, for the digital selection circuit 20, when the input of the S terminal is high, F outputs the data of the A port, and when it is low, F outputs the data of the B port.

Optionally, please refer to FIG. 1 to FIG. 2 , as a specific implementation of the synchronous counter provided by the embodiment of the present invention, each number selection circuit 20 includes a first bias resistor R ₂₁ and a second bias resistor R ₂₂ , the third bias resistor R ₂₃ , the first number selection transistor T ₂₁ , the second number selection transistor T ₂₂ , the third number selection transistor T ₂₃ , the fourth number selection transistor T ₂₄ , the fifth number selection transistor T ₂₅ , the Six digital selection transistors T ₂₆ and seventh digital selection transistor T ₂₇ .

The first terminal of the first bias resistor R ₂₁ and the first terminal of the second bias resistor R ₂₂ are connected to the power supply voltage VCC.

The second end of the first bias resistor _R21 is connected to the collector of the first digital selection transistor _T21 and the collector of the fourth digital selection transistor T24, and the second end of the second bias resistor _R22 is connected to the second digital selection transistor _T24 . The collector of the selection transistor _T22 and the collector of the third digital selection transistor _T23 are connected.

The emitter of the first digital selection transistor _T21 is connected to the emitter of the second digital selection transistor _T22 and the collector of the fifth digital selection transistor _T25 , and the emitter of the third digital selection transistor _T23 is connected to the fourth digital selection transistor. The emitter of _T24 and the collector of the sixth digital selection transistor _T26 are connected.

The emitter of the fifth digital selection transistor _T25 is connected to the emitter of the sixth digital selection transistor T26 and the collector of the _seventh digital selection transistor T27.

The base of the _seventh digital selection transistor T27 is connected to the DC bias voltage VB, the emitter of the _seventh digital selection transistor T27 is connected to the first end of the third bias resistor R23, and the third bias resistor _R23 is connected to the first end of the third bias resistor _R23 . Both ends are grounded.

信号)。其中，第一电平信号为同步计数器的预设电平信号的反相信号，第一电平信号可通过对预设电平信号进行反相处理得到。The base of the first digital selection transistor T ₂₁ is the second input terminal of the digital selection circuit (A terminal, the port receiving signal can be recorded as the A signal), which is used to receive the preset level signal of the synchronous counter. The second digital selection transistor T The base of ₂₂ is used to receive the first level signal (the port received signal can be recorded as

Signal). Wherein, the first level signal is an inversion signal of the preset level signal of the synchronization counter, and the first level signal can be obtained by inverting the preset level signal.

信号)。其中，第二电平信号为逻辑电路的第一控制信号的反相信号，第二电平信号可通过对第一控制信号进行反相处理得到。The base of the third digital selection transistor _T23 is the first input terminal (B terminal, the port receiving signal can be recorded as the B signal) of the digital selection circuit for receiving the first control signal of the logic circuit, and the fourth digital selection transistor _T24 The base is used to receive the second level signal (the port received signal can be recorded as

Signal). Wherein, the second level signal is an inverted signal of the first control signal of the logic circuit, and the second level signal can be obtained by inverting the first control signal.

信号)。其中，第三电平信号为逻辑电路的第二控制信号的反相信号，第三电平信号可通过对第二控制信号进行反相处理得到。The base of the fifth digital selection transistor _T25 is the address selection input end of the digital selection circuit (S terminal, the port receiving signal can be denoted as S signal), which is used to receive the second control signal of the logic circuit, and the sixth digital selection transistor _T26 The base is used to receive the third level signal (the port received signal can be recorded as

Signal). The third level signal is an inverted signal of the second control signal of the logic circuit, and the third level signal can be obtained by performing inversion processing on the second control signal.

The collector of the second digital selection transistor _T22 is the output terminal of the digital selection circuit (F terminal, the port receiving signal can be recorded as the F signal).

信号。Among them, the collector of the first digital selection transistor _T21 can output the inverted signal of the output signal of the digital selection circuit, and the port receiving signal can be recorded as

Signal.

Optionally, as a specific implementation of the synchronous counter provided in the embodiment of the present invention, the first number selection transistor, the second number selection transistor, the third number selection transistor, the fourth number selection transistor, the fifth number selection transistor, The sixth digital selection transistor and the seventh digital selection transistor are bipolar transistors.

In this embodiment, the bipolar transistor has the advantages of low flicker noise and high cut-off frequency, so the synchronous counter constructed based on the bipolar transistor has low phase noise and high operating frequency.

Optionally, please refer to FIG. 1 to FIG. 3 , as a specific implementation of the synchronous counter provided in the embodiment of the present invention, the D flip-flop includes a first latch 31 and a second latch 32 , and the first latch The circuit structure of the latch 31 and the second latch 32 are the same and the ports correspond to each other.

The first bias terminal of the first latch 31 and the first bias terminal of the second latch 32 are connected to the power supply voltage VCC in common, and the second bias terminal of the first latch 31 and the second latch 32 The second bias terminal of , is connected to the DC bias voltage VB in common.

信号)，其中，数选电路的输入信号的反相信号可通过对数选电路的输入信号进行反相处理得到。The first input terminal of the first latch 31 is the signal input terminal of the D flip-flop (the D terminal, the port receiving signal can be recorded as the D signal), which is used to receive the input signal of the digital selection circuit. The second input terminal is used to receive the inverted signal of the input signal of the digital selection circuit (the received signal of the port can be recorded as

signal), wherein the inverted signal of the input signal of the digital selection circuit can be obtained by inverting the input signal of the digital selection circuit.

信号)。The second output terminal of the second latch 32 is the output terminal of the D flip-flop (Q terminal, the port receiving signal can be recorded as the Q signal), which is used to output the status signal to the logic circuit. The first output terminal of the second latch 32 The output terminal is used to output the inverted signal of the status signal (the port received signal can be recorded as

Signal).

信号)。The third input terminal of the first latch 31 is the clock input terminal of the D flip-flop (the CLK terminal, the port receiving signal can be recorded as the CLK signal), which is used to receive the clock signal, and the fourth input terminal of the first latch 31 The inverted signal used to receive the clock signal (the port received signal can be recorded as

Signal).

The first output terminal of the first latch 31 is connected to the second input terminal of the second latch 32, the second output terminal of the first latch 31 is connected to the first input terminal of the second latch 32, The third input terminal of the first latch 31 is connected to the fourth input terminal of the second latch 32 , and the fourth input terminal of the first latch 31 is connected to the third input terminal of the second latch 32 .

In this embodiment, the first bias terminal, the second bias terminal, the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the first output terminal, the The second output terminal corresponds to the first terminal of the first resistor R1, the collector of the seventh transistor T7, the collector of the first transistor T1, the collector of the second transistor T2, the collector of the fifth transistor T5, The collector of the sixth transistor T6, the emitter of the eighth transistor T8, and the emitter of the ninth transistor T9.

In this embodiment, the first bias terminal, the second bias terminal, the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the first output terminal, the The second output terminal corresponds to the first terminal of the sixth resistor R6, the collector of the eighteenth transistor T18, the collector of the twelfth transistor T12, the collector of the thirteenth transistor T13, and the sixteenth transistor T16 in FIG. 3, respectively. , the collector of the seventeenth transistor T17, the emitter of the nineteenth transistor T19, and the emitter of the twentieth transistor T20.

Optionally, please refer to FIG. 1 to FIG. 3. As a specific implementation of the synchronous counter provided in the embodiment of the present invention, the first latch 31 includes a first resistor R1, a second resistor R2, a third resistor R3, The fourth resistor R4, the fifth resistor R5, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, The ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11.

The first end of the first resistor R1, the first end of the second resistor R2, the collector of the eighth transistor T8, and the collector of the ninth transistor T9 are commonly connected to the power supply voltage VCC. That is, the first end of the first resistor R1, the first end of the second resistor R2, the collector of the eighth transistor T8, and the collector of the ninth transistor T9 can all be used as the first bias end of the first latch 31 .

The second end of the first resistor R1 is connected to the collector of the first transistor T1, the collector of the third transistor T3, the base of the fourth transistor T4, and the base of the ninth transistor T9, and the second end of the second resistor R2 It is connected to the collector of the second transistor T2, the base of the third transistor T3, the collector of the fourth transistor T4, and the base of the eighth transistor T8.

信号)。The base of the first transistor T1 is the first input terminal (D terminal, the port receiving signal can be denoted as D signal) of the first latch, and the base of the second transistor T2 is the second input terminal (port terminal) of the first latch. The received signal can be recorded as

Signal).

The emitter of the first transistor T1 is connected to the emitter of the second transistor T2 and the collector of the fifth transistor T5, the emitter of the third transistor T3 is connected to the emitter of the fourth transistor T4 and the collector of the sixth transistor T6.

信号)。The base of the fifth transistor T5 is the third input terminal (the CLK terminal, the port receiving signal can be recorded as the CLK signal) of the first latch, and the base of the sixth transistor T6 is the fourth input terminal (the port) of the first latch. The received signal can be recorded as

Signal).

The emitter of the fifth transistor T5 is connected to the emitter of the sixth transistor T6 and the collector of the seventh transistor T7.

The base of the seventh transistor T7, the base of the tenth transistor T10, and the base of the eleventh transistor T11 are connected to the DC bias voltage in common. That is, the base of the seventh transistor T7 , the base of the tenth transistor T10 , and the base of the eleventh transistor T11 can all be used as the second bias terminal of the first latch 31 .

The emitter of the seventh transistor T7 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded. The emitter of the eighth transistor T8 is the first output terminal of the first latch, the emitter of the eighth transistor T8 is connected to the collector of the tenth transistor T10, and the emitter of the tenth transistor T10 is connected to the first output of the fourth resistor R4. terminal is connected, and the second terminal of the fourth resistor R4 is grounded. The emitter of the ninth transistor T9 is the second output terminal of the first latch, the emitter of the ninth transistor T9 is connected to the collector of the eleventh transistor T11, and the emitter of the eleventh transistor T11 is connected to the collector of the fifth resistor R5. The first end is connected, and the second end of the fifth resistor R5 is grounded.

Optionally, please refer to FIG. 1 to FIG. 3, as a specific implementation of the synchronous counter provided by the embodiment of the present invention, the second latch 32 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, The ninth resistor R9, the tenth resistor R10, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22.

The first end of the sixth resistor R6, the first end of the seventh resistor R7, the collector of the nineteenth transistor T19, and the collector of the twentieth transistor T20 are commonly connected to the power supply voltage. That is, the first end of the sixth resistor R6, the first end of the seventh resistor R7, the collector of the nineteenth transistor T19, and the collector of the twentieth transistor T20 can all be used as the first bias of the second latch 32. set end.

The second end of the sixth resistor R6 is connected to the collector of the twelfth transistor T12, the collector of the fourteenth transistor T14, the base of the fifteenth transistor T15, and the base of the twentieth transistor T20, and the seventh resistor R7 The second terminal of the transistor T13 is connected to the collector of the thirteenth transistor T13, the base of the fourteenth transistor T14, the collector of the fifteenth transistor T15, and the base of the nineteenth transistor T19.

The base of the twelfth transistor T12 is the first input terminal of the second latch, and the base of the thirteenth transistor T13 is the second input terminal of the second latch.

The emitter of the twelfth transistor T12 is connected to the emitter of the thirteenth transistor T13 and the collector of the sixteenth transistor T16, and the emitter of the fourteenth transistor T14 is connected to the emitter of the fifteenth transistor T15 and the seventeenth transistor Collector connection of T17.

信号)，第十七晶体管T17的基极为第二锁存器的第四输入端(端口接收信号可记为CLK信号)。The base of the sixteenth transistor T16 is the third input terminal of the second latch (the port receiving signal can be recorded as

signal), the base of the seventeenth transistor T17 is the fourth input terminal of the second latch (the port receiving signal can be recorded as the CLK signal).

The emitter of the sixteenth transistor T16 is connected to the emitter of the seventeenth transistor T17 and the collector of the eighteenth transistor T18.

The base of the eighteenth transistor T18, the base of the twenty-first transistor T21, and the base of the twenty-second transistor T22 are connected to the DC bias voltage in common. That is, the base of the eighteenth transistor T18 , the base of the twenty-first transistor T21 , and the base of the twenty-second transistor T22 can all be used as the second bias terminal of the second latch 32 .

信号)，第十九晶体管T19的发射极与第二十一晶体管T21的集电极连接，第二十一晶体管T21的发射极与第九电阻R9的第一端连接，第九电阻R9的第二端接地。第二十晶体管T20的发射极为第二锁存器的第二输出端(也即Q端，端口输出信号可记为Q信号)，第二十晶体管T20的发射极与第二十二晶体管T22的集电极连接，第二十二晶体管T22的发射极与第十电阻R10的第一端连接，第十电阻R10的第二端接地。The emitter of the eighteenth transistor T18 is connected to the first end of the eighth resistor R8, and the second end of the eighth resistor R8 is grounded. The emitter of the nineteenth transistor T19 is the first output terminal of the second latch (the port output signal can be recorded as

signal), the emitter of the nineteenth transistor T19 is connected to the collector of the twenty-first transistor T21, the emitter of the twenty-first transistor T21 is connected to the first end of the ninth resistor R9, and the second end of the ninth resistor R9 terminal to ground. The emitter of the twentieth transistor T20 is the second output terminal of the second latch (ie, the Q terminal, the port output signal can be recorded as the Q signal), and the emitter of the twentieth transistor T20 is the same as the second output terminal of the twenty-second transistor T22. The collector is connected, the emitter of the twenty-second transistor T22 is connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is grounded.

Optionally, as a specific implementation manner of the synchronous counter provided by the embodiment of the present invention, the transistor in the D flip-flop is a bipolar transistor.

In this embodiment, the bipolar transistor has the advantages of low flicker noise and high cut-off frequency, so the synchronous counter constructed based on the bipolar transistor has low phase noise and high operating frequency.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or modifications within the technical scope disclosed by the present invention. Replacement, these modifications or replacements should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (7)

1. a synchronous counter, is characterized in that, comprises: a logic circuit, at least two digital selection circuits, and at least two D flip-flops, the at least two digital selection circuits are in one-to-one correspondence with the at least two D flip-flops; The signal input terminal of the logic circuit is connected to the output terminal of each D flip-flop, the first signal output terminal of the logic circuit is connected to the first input terminal of each digital selection circuit, and the second signal output terminal of the logic circuit is connected to the first input terminal of each digital selection circuit. The output terminal is connected with the address selection input terminal of each digital selection circuit; For the corresponding digital selection circuit and D flip-flop, the output end of the digital selection circuit is connected with the signal input end of the D flip-flop; The second input terminal of each digital selection circuit is used to receive the preset level signal of the synchronous counter, the clock input terminal of each D flip-flop is the input terminal of the synchronous counter, and the second signal output terminal of the logic circuit is the synchronous counter input terminal. output of the counter. 2. The synchronous counter of claim 1, wherein each digital selection circuit comprises a first bias resistor, a second bias resistor, a third bias resistor, a first digital selection transistor, and a second digital selection transistor. a transistor, a third digital selection transistor, a fourth digital selection transistor, a fifth digital selection transistor, a sixth digital selection transistor, and a seventh digital selection transistor; The first end of the first bias resistor and the first end of the second bias resistor are connected to a power supply voltage; The second end of the first bias resistor is connected to the collector of the first digital selection transistor and the collector of the fourth digital selection transistor, and the second end of the second bias resistor is connected to the first digital selection transistor. The collectors of the two digital selection transistors and the collectors of the third transistors are connected; The emitter of the first digital selection transistor is connected to the emitter of the second digital selection transistor and the collector of the fifth digital selection transistor, and the emitter of the third digital selection transistor is connected to the fourth digital selection transistor. The emitter of the selection transistor and the collector of the sixth digital selection transistor are connected; The emitter of the fifth digital selection transistor is connected to the emitter of the sixth digital selection transistor and the collector of the seventh digital selection transistor; The base of the seventh digital selection transistor is connected to the DC bias voltage, the emitter of the seventh digital selection transistor is connected to the first end of the third bias resistor, and the second end of the third bias resistor is connected. terminal grounding; The base of the first digital selection transistor is the second input end of the digital selection circuit, which is used to receive the preset level signal of the synchronous counter, and the base of the second digital selection transistor is used to receive the first level signal; Wherein, the first level signal is the inverted signal of the preset level signal of the synchronization counter; The base of the third digital selection transistor is the first input end of the digital selection circuit for receiving the first control signal of the logic circuit, and the base of the fourth digital selection transistor is used for receiving the second level signal; wherein , the second level signal is the inverted signal of the first control signal of the logic circuit; The base of the fifth digital selection transistor is the address selection input end of the digital selection circuit, which is used to receive the second control signal of the logic circuit, and the base of the sixth digital selection transistor is used to receive the third level signal; wherein , the third level signal is the inverted signal of the second control signal of the logic circuit; The collector of the second digital selection transistor is the output end of the digital selection circuit. 3. The synchronous counter of claim 2, wherein the first number selection transistor, the second number selection transistor, the third number selection transistor, the fourth number selection transistor, the fifth number selection transistor, the sixth number selection transistor The digital selection transistor and the seventh digital selection transistor are bipolar transistors. 4. The synchronous counter of claim 1, wherein the D flip-flop comprises a first latch and a second latch, the first latch and the second latch circuit The structure is the same and the ports correspond to each other; The first bias terminal of the first latch and the first bias terminal of the second latch are connected to the power supply voltage in common, and the second bias terminal of the first latch and the second latch The second bias terminal of the latch is commonly connected to the DC bias voltage; The first input terminal of the first latch is the signal input terminal of the D flip-flop, which is used to receive the input signal of the digital selection circuit, and the second input terminal of the first latch is used to receive the digital selection circuit. The inverted signal of the input signal of the circuit; The second output end of the second latch is the output end of the D flip-flop, which is used to output the state signal to the logic circuit, and the first output end of the second latch is used to output the inverse of the state signal. phase signal; The third input terminal of the first latch is the clock input terminal of the D flip-flop for receiving the clock signal, and the fourth input terminal of the first latch is used for receiving the inverted signal of the clock signal ; The first output terminal of the first latch is connected to the second input terminal of the second latch, and the second output terminal of the first latch is connected to the first output terminal of the second latch. The input terminal is connected, the third input terminal of the first latch is connected to the fourth input terminal of the second latch, and the fourth input terminal of the first latch is connected to the second latch connected to the third input of the device. 5. The synchronous counter of claim 4, wherein the first latch comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second resistor a transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The first end of the first resistor, the first end of the second resistor, the collector of the eighth transistor, and the collector of the ninth transistor are commonly connected to the power supply voltage; The second end of the first resistor is connected to the collector of the first transistor, the collector of the third transistor, the base of the fourth transistor, and the base of the ninth transistor, and the second end of the second resistor is connected to the first transistor. The collector of the second transistor, the base of the third transistor, the collector of the fourth transistor, and the base of the eighth transistor are connected; The base of the first transistor is the first input end of the first latch, and the base of the second transistor is the second input end of the first latch; The emitter of the first transistor is connected to the emitter of the second transistor and the collector of the fifth transistor, and the emitter of the third transistor is connected to the emitter of the fourth transistor and the sixth transistor. collector connection; The base of the fifth transistor is the third input end of the first latch, and the base of the sixth transistor is the fourth input end of the first latch; The emitter of the fifth transistor is connected to the emitter of the sixth transistor and the collector of the seventh transistor; The base of the seventh transistor, the base of the tenth transistor, and the base of the eleventh transistor are connected to the DC bias voltage in common; The emitter of the seventh transistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; the emitter of the eighth transistor is the first output end of the first latch, the eighth The emitter of the transistor is connected to the collector of the tenth transistor, the emitter of the tenth transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the emitter of the ninth transistor is the first The second output end of the latch, the emitter of the ninth transistor is connected to the collector of the eleventh transistor, the emitter of the eleventh transistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected terminal to ground. 6. The synchronous counter of claim 4, wherein the second latch comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a twelfth transistor, a Thirteen transistors, fourteenth transistors, fifteenth transistors, sixteenth transistors, seventeenth transistors, eighteenth transistors, nineteenth transistors, twentieth transistors, twenty-first transistors, and twenty-second transistors ; The first end of the sixth resistor, the first end of the seventh resistor, the collector of the nineteenth transistor, and the collector of the twentieth transistor are commonly connected to the power supply voltage; The second end of the sixth resistor is connected to the collector of the twelfth transistor, the collector of the fourteenth transistor, the base of the fifteenth transistor, and the base of the twentieth transistor. The two terminals are connected to the collector of the thirteenth transistor, the base of the fourteenth transistor, the collector of the fifteenth transistor, and the base of the nineteenth transistor; The base of the twelfth transistor is the first input end of the second latch, and the base of the thirteenth transistor is the second input end of the second latch; The emitter of the twelfth transistor is connected to the emitter of the thirteenth transistor and the collector of the sixteenth transistor, and the emitter of the fourteenth transistor is connected to the emitter of the fifteenth transistor and the collector of the sixteenth transistor. the collector connection of the seventeenth transistor; The base of the sixteenth transistor is the third input end of the second latch, and the base of the seventeenth transistor is the fourth input end of the second latch; The emitter of the sixteenth transistor is connected to the emitter of the seventeenth transistor and the collector of the eighteenth transistor; The base of the eighteenth transistor, the base of the twenty-first transistor, and the base of the twenty-second transistor are connected to the DC bias voltage in common; The emitter of the eighteenth transistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is grounded; the emitter of the nineteenth transistor is the first output end of the second latch, the The emitter of the nineteenth transistor is connected to the collector of the twenty-first transistor, the emitter of the twenty-first transistor is connected to the first end of the ninth resistor, and the second end of the ninth resistor is grounded; The emitter of the twentieth transistor is the second output terminal of the second latch, the emitter of the twentieth transistor is connected to the collector of the twenty-second transistor, and the emitter of the twenty-second transistor is connected to the connection of the tenth resistor. The first end is connected, and the second end of the tenth resistor is grounded. 7 . The synchronous counter according to claim 5 , wherein the transistors in the D flip-flops are bipolar transistors. 8 .

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