CN111563058A - A device for switching PCIE Gen4 in a server - Google Patents

Abstract

The invention discloses a device for switching PCIE Gen4 in a server, which comprises a mainboard, a PCIE adapter plate and an IO plate, wherein a CPU arranged on the mainboard is connected with a mainboard connector arranged on the mainboard through a PCIE Gen4 bus, the mainboard connector is connected with the PCIE adapter plate, the PCIE adapter plate is connected with the IO plate, and the mainboard connector is connected with PCIE Gen4 equipment arranged in a PCIE Gen4 slot of the IO plate through the PCIE adapter plate. Through setting up the mainboard connector on the mainboard, through connecting the PCIE keysets, be connected PCIE keysets and IO board again, realize that CPU on the mainboard is connected with the PCIE Gen4 equipment in the PCIE Gen4 groove of IO board, when the server supports PCIE Gen4 equipment, saved high-speed backplate design, change high-speed cable interconnection design into and improved system heat-sinking capability, easy maintainability ability, high-speed signal link loss has been reduced, the operational reliability of server has been improved.

Description

A device for switching PCIE Gen4 in a server

technical field

The invention relates to the technical field of PCIE switching in a server, and more particularly, to a device for switching PCIE Gen4 in a server.

Background technique

The IO interface performance of the server is one of the important performance indicators of the server, and the PCIE interface is the most important IO interface of the server. With the continuous upgrading of technology, the PCIE interface standard has been upgraded from the initial 1.0 to 2.0, and then to 3.0.

Currently, server products supporting the PCIE 4.0 interface already exist in the market. The updated interface standard means higher transmission bandwidth and speed, which puts forward higher requirements for server hardware design. Among the existing server technologies, products supporting the PCIE 3.0 interface are very common, with a bit rate of 8 Gbps. With the gradual emergence of PCIE 4.0 interface with a bit rate of 16Gbps in server technology, server system design faces more challenges, such as chip drive capability, PCB board loss, connector loss, cable loss, etc. more severe. Therefore, the link conditions in the existing system design can no longer meet the link loss requirements of the PCIE 4.0 interface.

In the more common PCIE transfer method in the prior art, as shown in FIG. 1 , the PCIE Gen3 signal of the CPU4 is first connected from the motherboard 1 to the high-speed backplane 3 through the high-speed backplane connector, and then from the high-speed backplane 3 connector. The high-speed backplane 3 is connected to the IO board 2, and the IO board 2 is connected to the PCIE device through the PCIE slot 5. This design is generally used for servers larger than 2U, such as 3U, 4U, 6U, etc., and has better expansion capabilities of PCIE devices, such as multiple network devices, storage devices, and so on. Therefore, it is necessary to support larger system power consumption and better high-speed interconnection capability.

But this design often faces two risks:

First, the design of the vertical high-speed backplane is relatively windproof, and its heat dissipation capacity is limited when the system power consumption is large;

Second, second, the PCIE signal needs to pass through the main board, high-speed backplane, IO board and other multi-level PCB boards, resulting in a large signal loss, and it is difficult to support a higher signal rate.

SUMMARY OF THE INVENTION

The invention provides a device for transferring PCIE Gen4 in the server, which improves the ventilation efficiency in the chassis to improve the heat dissipation capacity, reduces the loss of the PCIE Gen4 signal link, and can realize the upgrade rate of the PCIE equipment in the server from PCIE Gen3 to PCIE Gen4.

In order to solve the above-mentioned technical problems, the present invention provides a device for switching PCIE Gen4 in a server, including a main board, a PCIE adapter board and an IO board. The CPU arranged on the main board and the main board connector arranged on the main board pass through. PCIEGen4 bus connection, the motherboard connector is connected with the PCIE adapter board, the PCIE adapter board is connected with the IO board, and the motherboard connector is connected to the IO board through the PCIE adapter board PCIE Gen4 slot for PCIE Gen4 device connection.

Wherein, the mainboard connector is connected with the PCIE adapter board so that the mainboard connector is connected with the adapter board connector arranged on the PCIE adapter board, and the adapter board connector is connected with the adapter board connector arranged on the PCIE adapter board. The adapter card of the PCIE adapter board is connected, or the motherboard connector is connected with the adapter card arranged on the PCIE adapter board.

Wherein, the motherboard connector and the adapter board connector are Slimline connectors or Examax connectors.

Wherein, the motherboard connector and the adapter board connector of the PCIE adapter board are connected through a Slimline cable or the motherboard connector and the adapter card of the PCIE adapter board are connected through a Slimline to Examax cable .

Wherein, the number of the CPUs arranged on the motherboard is at least two.

Wherein, the surfaces of the IO board and the PCIE adapter board are on the same plane, and are on a different plane from the surface of the motherboard.

Wherein, the PCIE adapter board is connected with the IO board through a backplane connector.

Wherein, a plurality of the motherboard connectors are connected with a plurality of adapter board connectors arranged on the PCIE adapter board in a one-to-one correspondence, or a plurality of the motherboard connectors are connected with the adapter board connectors arranged on the PCIE adapter board. The cards are connected one by one.

The device for transferring PCIE Gen4 in the server can realize the PCIE Gen4 slot between the CPU on the motherboard and the IO board by arranging the mainboard connector on the mainboard, connecting the PCIE adapter board, and then connecting the PCIE adapter board with the IO board. When the server supports PCIE Gen4 devices, the high-speed backplane design is omitted, and the high-speed cable interconnection design improves the system’s heat dissipation capability and easy maintenance, reduces the loss of high-speed signal links, and improves the server’s performance. Operational reliability.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

1 is a schematic diagram of a PCIE switching structure in a server of the prior art;

2 is a schematic structural diagram of an embodiment of an apparatus for switching PCIE Gen4 in a server provided by the present application;

FIG. 3 is a schematic structural diagram of another embodiment of an apparatus for switching PCIE Gen4 in a server provided by the present application.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in Figures 1-3, Figure 1 is a schematic structural diagram of a PCIE switch in a server in the prior art; Figure 2 is a schematic structural diagram of an embodiment of a device for switching PCIE Gen4 in a server provided by the present application; The application provides a schematic structural diagram of another embodiment of an apparatus for switching PCIE Gen4 in a server.

In a specific embodiment, the present invention provides a device for switching PCIE Gen4 in a server, which includes a main board 10, a PCIE switching board 20 and an IO board 30. The CPU 11 arranged on the main board 10 and the CPU 11 arranged on the The motherboard connector 12 of the motherboard 10 is connected through the PCIE Gen4 bus, the motherboard connector 12 is connected with the PCIE adapter board 20, the PCIE adapter board 20 is connected with the IO board 30, and the motherboard connector 12 It is connected to the PCIE Gen4 device disposed in the PCIE Gen4 slot 31 of the IO board 30 through the PCIE adapter board 20 .

By arranging the motherboard connector 12 on the motherboard 10, by connecting the PCIE adapter board 20, and then connecting the PCIE adapter board 20 with the IO board 30, the CPU11 on the motherboard 10 and the PCIE Gen4 slot 31 of the IO board 30 are realized PCIE Gen4 Device connection, while the server supports PCIE Gen4 devices, the high-speed backplane design is omitted, and the high-speed cable interconnection design is used to improve the system's heat dissipation capability and easy maintenance, reduce the loss of high-speed signal links, and improve the reliability of server operation. sex.

The device for switching PCIE Gen4 in the server of the present invention does not limit the connection method between the motherboard connector 12 and the PCIE switching board 20 , which may be a direct connection or an indirect connection. That is, the connection between the motherboard connector 12 and the PCIE adapter board 20 may be the connection between the motherboard connector 12 and the adapter board connector 21 provided on the PCIE adapter board 20, and the adapter board connector 21 is connected with the adapter card arranged on the PCIE adapter board 20, and is indirectly connected through the adapter board connector 21; or the motherboard connector 12 is connected with the adapter card arranged on the PCIE adapter board 20 , for direct connection.

The indirect connection method is adopted, and the connection required equipment is relatively simple. The present invention does not limit the type and quantity of the corresponding connectors. The main board connector 12 and the adapter board connector 21 are Slimline connectors or Examax connectors, or other type of connector.

Correspondingly, the present invention does not limit the cables used in the connection process. The motherboard connector 12 is connected with the adapter board connector 21 of the PCIE adapter board 20 through the Slimline cable 13 or the motherboard connector. 12 is connected to the riser card of the PCIE riser board 20 through a cable 14 from Slimline to Examax.

In the present invention, the number of CPUs 11 on the motherboard 10 is not limited, and it may be one or multiple. Generally, in order to improve the operating efficiency of the server, multiple CPUs 11 are used. Therefore, the proposal is arranged on the CPU 11 of the motherboard 10 The number is at least two.

In the present invention, because the cable is used to connect the PCIE adapter board 20 and the main board 10, instead of using the backplane connector in the prior art to connect the IO board 30, the main board 10 and the high-speed backplane at the same time, the backplane connector is not used. The hard connection method adopts the soft connection method of cable, so that it can not be in the same plane with the motherboard 10 and will not affect the heat dissipation of the motherboard 10. Moreover, the cable connection method is adopted, and cables of different lengths can be used according to needs. , to achieve the purpose of being far away from the main board 10, and can further reduce mutual interference, so that the staff can arrange the equipment at will. The specific setting position is not limited. Therefore, in one embodiment, the surfaces of the IO board 30 and the PCIE adapter board 20 are in the same plane, and are in a different plane from the surface of the main board 10 . It should be pointed out that the surfaces of the IO board 30 and the main board 10 are in a different plane. , it can be in a parallel plane, that is, at different heights. If the distance is relatively far, it can also be in the same plane without affecting the heat dissipation, but generally try to avoid this situation and reduce the design difficulty.

The present invention does not limit the connection mode of the PCIE adapter board 20 and the IO board 30, and the connection mode in the prior art may be adopted, or a new connection mode may be adopted. In one embodiment, the PCIE adapter board 20 is connected to the IO board 30 through a backplane connector.

In the present invention, the connection links between the multiple CPUs 11 and the PCIE Gen4 devices can be the same or different. For example, the connection link of one CPU11 is a direct connection, and the other is an indirect connection. However, in order to simplify the process and reduce the difficulty of the process, Generally, multiple links adopt the same structure, for example, a plurality of the motherboard connectors 12 are connected to a plurality of adapter board connectors 21 provided on the PCIE adapter board 20 in a one-to-one correspondence, or a plurality of the motherboard connectors are connected The adapter 12 is connected to the adapter cards disposed on the PCIE adapter board 20 in a one-to-one correspondence.

In one embodiment, the PCIE Gen4 signal of the CPU 11 on the motherboard 10 is connected to the PCIE adapter board 20 through the Slimline cable 13 that can support 16G rate, and the PCIE Gen4 signal on the PCIE adapter board 20 is connected through the in-line backplane The connector is connected to the PCIE Gen4 slot 31 on the IO board 30. The main board 10 is on one level, the IO board 30 and the PCIE adapter board 20 are on another level, but their interconnection does not need to pass through a vertical high-speed backplane, thereby ensuring the expandable space of the server system and avoiding the high-speed backplane. Bad influence on system heat dissipation, on the other hand, the link loss of high-speed cables such as slimline is lower than that of PCB high-speed backplane, so the link loss when using PCIE Gen4 signal is lower than that when using PCIE Gen4 in the prior art Therefore, the server can support PCIE Gen4 devices, and the cable-based high-speed interconnection design has the advantages of lower design cost, easy maintenance, and flexible installation compared with the high-speed backplane interconnection design.

On the basis of the above embodiment, in another embodiment, the PCIE signal sent by the CPU 11 on the main board 10 is directly connected to the Examax connector terminal of the IO board 30 through a customized Slimline to Examax cable, that is, using direct connection. One end of the Slimline-to-Examax cable 14 is installed on the slimline connector of the motherboard 10, and the other end is fixed on the PCIE adapter board 20, but there is no actual PCIE Gen4 signal routing on the PCIE adapter board 20, only for the purpose of The structure is fixed, so that the IO board 30 can be inserted and pulled out of the whole module to the PCIE adapter card. Therefore, in this design, the IO board 30 still guarantees its hot-plug capability, and will not lose the hot-plug characteristic due to interconnection with the cable, and will not increase the difficulty of hot-plug design. At the same time, since the PCB traces of the PCIE signal on the PCIE adapter board 20 are reduced, the link loss of the PCIE Gen4 signal can be further reduced. In this embodiment, the link loss of the PCIE Gen4 signal is further optimized, and the cable is more customized, and the server design can be arbitrarily selected according to the actual link length. For PCIE Gen4 high-speed signal routing requirements, the direct connection structure can also be used in combination with the direct connection and indirect connection solutions in the actual design.

To sum up, the device for switching PCIE Gen4 in the server provided by the embodiment of the present invention is realized by arranging the motherboard connector on the motherboard, connecting the PCIE switching board, and then connecting the PCIE switching board with the IO board. The CPU on the motherboard is connected to the PCIE Gen4 device in the PCIE Gen4 slot of the IO board. While the server supports the PCIE Gen4 device, the high-speed backplane design is omitted, and the high-speed cable interconnection design is used to improve the system heat dissipation capacity and easy maintenance. The loss of high-speed signal links is reduced, and the operational reliability of the server is improved.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. The device for switching PCIE Gen4 in the server is characterized by comprising a mainboard, a PCIE adapter board and an IO board, wherein the CPU and the mainboard connector of the mainboard are connected through a PCIE Gen4 bus, the mainboard connector is connected with the PCIE adapter board, the PCIE adapter board is connected with the IO board, and the mainboard connector is connected with PCIE Gen4 equipment in a PCIE Gen4 groove of the IO board through the PCIE adapter board.

2. The apparatus of claim 1, wherein the board connector is connected to the PCIE interposer such that the board connector is connected to an interposer connector disposed on the PCIE interposer, the interposer connector is connected to an interposer disposed on the PCIE interposer, or the board connector is connected to an interposer disposed on the PCIE interposer.

3. The apparatus of claim 2, wherein the motherboard connector, the patch panel connector is a slim line connector or an Examax connector.

4. The apparatus of claim 3, wherein the motherboard connector is connected to a patch panel connector of the PCIE patch panel via a Slimline cable or the motherboard connector is connected to a patch card of the PCIE patch panel via a Slimline to Examax cable.

5. The apparatus for switching PCIE Gen4 in a server of claim 4, wherein the number of the CPUs provided on the motherboard is at least two.

6. The apparatus of claim 5, wherein surfaces of the IO board and the PCIE interposer are in a same plane and are in a different plane than a surface of the motherboard.

7. The apparatus of claim 6, wherein the PCIE Gen4 switch board and the IO board are connected by a backplane connector.

8. The apparatus of claim 7, wherein a plurality of the motherboard connectors are connected to a plurality of the interposer connectors disposed on the PCIE interposer in a one-to-one correspondence, or a plurality of the motherboard connectors are connected to the interposer connectors disposed on the PCIE interposer in a one-to-one correspondence.

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