CN111565255A - Communication device and modem - Google Patents
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Abstract
一种通信装置及调制解调器,所述通信装置包括:处理器件;第一存储模块,分别与所述处理器件以及所述调制解调器耦接;所述处理器件与所述调制解调器共享所述第一存储模块;第二存储模块,与所述调制解调器耦接;所述第二存储模块为所述调制解调器专属存储模块;调制解调器,包括存储控制模块;所述存储控制模块,适于在接收到数据处理请求时,根据所述数据处理请求对应的地址,确定访问第一存储模块还是访问第二存储模块。上述方案,能够在降低通信装置成本的同时,提高调制解调器的实时性。
A communication device and a modem, the communication device comprising: a processing device; a first storage module, respectively coupled to the processing device and the modem; the processing device and the modem share the first storage module; a second storage module, coupled to the modem; the second storage module is a dedicated storage module for the modem; the modem includes a storage control module; the storage control module is adapted to, when a data processing request is received, according to The address corresponding to the data processing request determines whether to access the first storage module or the second storage module. The above solution can improve the real-time performance of the modem while reducing the cost of the communication device.
Description
技术领域technical field
本发明涉及通信技术领域,尤其涉及一种通信装置及调制解调器。The present invention relates to the field of communication technologies, and in particular, to a communication device and a modem.
背景技术Background technique
现有的调制解调器对双倍速率同步动态随机存储器(Double Data RateSynchronous Dynamic Random Access Memory,简称DDR SDRAM,可简称DDR)的访问是不可或缺的。调制解调器中的MCU和各个硬件(Hardware,简称HW)加速器都需要DDR承担大数据量缓存。Access to Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM for short, DDR for short) is indispensable for existing modems. The MCU in the modem and each hardware (Hardware, HW for short) accelerator all require DDR to undertake a large amount of data cache.
已有技术方案中,有的方案为调制解调器配置专用DDR,这虽然能够满足调制解调器的数据缓存需求,但实现成本高昂。有的方案为调制解调器配置共享DDR,以在降低产品成本的同时满足数据缓存需求。但是,外部存储器访问通常伴随访问延迟过大的问题,无法应用在一些对实时性要求较高的应用场景。Among the existing technical solutions, some solutions configure a dedicated DDR for the modem. Although this can meet the data buffering requirements of the modem, the implementation cost is high. Some solutions configure shared DDR for modems to meet data buffering requirements while reducing product costs. However, external memory access is usually accompanied by the problem of excessive access delay, which cannot be used in some application scenarios that require high real-time performance.
发明内容SUMMARY OF THE INVENTION
本发明实施例解决的技术问题是无法实现通信装置的成本与调制解调器实时性的折中。The technical problem solved by the embodiments of the present invention is that a compromise between the cost of the communication device and the real-time performance of the modem cannot be achieved.
为解决上述技术问题,本发明实施例提供一种通信装置,包括:处理器件;第一存储模块,分别与所述处理器件以及所述调制解调器耦接;所述处理器件与所述调制解调器共享所述第一存储模块;第二存储模块,与所述调制解调器耦接;所述第二存储模块为所述调制解调器专属存储模块;调制解调器,包括存储控制模块;所述存储控制模块,适于在接收到数据处理请求时,根据所述数据处理请求对应的地址,确定访问第一存储模块还是访问第二存储模块。To solve the above technical problem, an embodiment of the present invention provides a communication device, including: a processing device; a first storage module, respectively coupled to the processing device and the modem; the processing device and the modem share the a first storage module; a second storage module, coupled to the modem; the second storage module is a dedicated storage module for the modem; the modem includes a storage control module; the storage control module is adapted to receive data When processing the request, it is determined whether to access the first storage module or the second storage module according to the address corresponding to the data processing request.
可选的,所述调制解调器还包括:缓存模块,用于缓存所述存储控制模块访问过的历史数据;所述存储控制模块,还适于在接收到所述数据处理请求时,先读取所述缓存模块,如果命中就返回读取结果;如果未命中就根据所述数据处理请求对应的地址确定对应的存储模块。Optionally, the modem further includes: a cache module, configured to cache the historical data accessed by the storage control module; the storage control module is further adapted to read the data processing request first when receiving the data processing request. If the cache module is hit, the read result will be returned; if it is not hit, the corresponding storage module will be determined according to the address corresponding to the data processing request.
可选的,所述缓存模块缓存的是所述存储控制模块历史上高频访问的数据。Optionally, the cache module caches data that is frequently accessed in the history of the storage control module.
可选的,所述调制解调器包括接口单元,所述接口单元用于与所述处理器件基于串行总线进行通信。Optionally, the modem includes an interface unit, and the interface unit is configured to communicate with the processing device based on a serial bus.
可选的,所述第一存储模块的存储容量大于所述第二存储模块的存储容量。Optionally, the storage capacity of the first storage module is greater than the storage capacity of the second storage module.
可选的,所述处理器件为应用处理器。Optionally, the processing device is an application processor.
为解决上述技术问题,本发明实施例还提供了一种调制解调器,包括:存储控制模块,适于在接收到数据处理请求时,根据所述数据处理请求对应的地址,确定对应的存储模块,所述存储模块包括第一存储模块与第二存储模块,所述第一存储模块与外部处理器件以及所述调制解调器均耦接,所述第二存储模块与所述调制解调器耦接;所述外部处理器件与所述调制解调器共享所述第一存储模块;所述第二存储模块为所述调制解调器专属存储模块。In order to solve the above technical problem, an embodiment of the present invention also provides a modem, including: a storage control module, which is adapted to, when receiving a data processing request, determine a corresponding storage module according to an address corresponding to the data processing request, so that the The storage module includes a first storage module and a second storage module, the first storage module is coupled with an external processing device and the modem, the second storage module is coupled with the modem; the external processing device The first storage module is shared with the modem; the second storage module is a dedicated storage module for the modem.
可选的,所述调制解调器还包括:缓存模块,用于缓存所述存储控制模块访问过的历史数据;所述存储控制模块,还适于在接收到所述数据处理请求时,先读取所述缓存模块,如果命中就返回读取结果;如果未命中就根据所述数据处理请求对应的地址确定对应的存储模块。Optionally, the modem further includes: a cache module, configured to cache the historical data accessed by the storage control module; the storage control module is further adapted to read the data processing request first when receiving the data processing request. If the cache module is hit, the read result will be returned; if it is not hit, the corresponding storage module will be determined according to the address corresponding to the data processing request.
可选的,所述缓存模块缓存的是所述存储控制器历史上高频访问的数据。Optionally, the cache module caches data that is frequently accessed in the history of the storage controller.
可选的,所述调制解调器包括:接口单元;用于与所述外部处理器件基于串行总线进行通信。Optionally, the modem includes: an interface unit; used to communicate with the external processing device based on a serial bus.
可选的,所述第一存储模块的存储容量大于所述第二存储模块的存储容量。Optionally, the storage capacity of the first storage module is greater than the storage capacity of the second storage module.
与现有技术相比,本发明实施例的技术方案具有以下有益效果:Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:
调制解调器与处理器件共享第一存储模块,专用第二存储模块。第二存储模块中存储对实时性要求较高的数据,第一存储模块中存储对实时性要求较低的数据。调制解调器与处理器件共享的第一存储模块,可以减少第二存储模块的存储容量以降低调制解调器的成本,进而降低通信装置的成本;为调制解调器设置第二存储模块,能够提高调制解调器的实时性。The modem shares the first storage module with the processing device and dedicates the second storage module. The second storage module stores data with higher real-time requirements, and the first storage module stores data with lower real-time requirements. The first storage module shared by the modem and the processing device can reduce the storage capacity of the second storage module to reduce the cost of the modem, thereby reducing the cost of the communication device; setting the second storage module for the modem can improve the real-time performance of the modem.
进一步,调制解调器在接收到数据处理请求后,先读取缓存模块,若命中则直接返回读取结果,由于从缓存模块中读取数据的速度更快,因此能够更进一步地提高解调器的实时性。Further, after the modem receives the data processing request, it first reads the cache module, and if it hits, it directly returns the read result. Since the speed of reading data from the cache module is faster, it can further improve the real-time performance of the demodulator. sex.
附图说明Description of drawings
图1是本发明实施例中的一种通信装置的结构示意图;FIG. 1 is a schematic structural diagram of a communication device in an embodiment of the present invention;
图2是本发明实施例中的一种调制解调器的结构示意图。FIG. 2 is a schematic structural diagram of a modem in an embodiment of the present invention.
具体实施方式Detailed ways
如上所述,已有技术方案中,有的方案为调制解调器配置专用DDR,这虽然能够满足调制解调器的数据缓存需求,但实现成本高昂。有的方案为调制解调器配置共享DDR,以在降低产品成本的同时满足数据缓存需求。但是,外部存储器访问通常伴随访问延迟过大的问题,无法应用在一些对实时性要求较高的应用场景。As mentioned above, among the existing technical solutions, some solutions configure a dedicated DDR for the modem, although this can meet the data buffering requirements of the modem, but the implementation cost is high. Some solutions configure shared DDR for modems to meet data buffering requirements while reducing product costs. However, external memory access is usually accompanied by the problem of excessive access delay, which cannot be used in some application scenarios that require high real-time performance.
在本发明实施例中,调制解调器与处理器件共享的第一存储模块,可以减少第二存储模块的存储容量以降低调制解调器的成本;为调制解调器设置第二存储模块,能够提高调制解调器的实时性。In the embodiment of the present invention, the first storage module shared by the modem and the processing device can reduce the storage capacity of the second storage module to reduce the cost of the modem; setting the second storage module for the modem can improve the real-time performance of the modem.
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
参照图1,给出了本发明实施例中的一种通信装置。在本发明实施例中,通信装置可以包括处理器件11、第一存储模块12、第二存储模块13以及调制解调器14。Referring to FIG. 1, a communication apparatus in an embodiment of the present invention is shown. In this embodiment of the present invention, the communication apparatus may include a processing device 11 , a
在具体实施中,处理器件11可以为应用处理器(Application Processor,AP),也可以为其他独立于调制解调器14且能够实现数据处理能够的电子元件。In a specific implementation, the processing device 11 may be an application processor (Application Processor, AP), or may be other electronic components independent of the
在具体实施中,第一存储模块12可以分别于调制解调器14以及处理器件11耦接。第一存储模块12中可以存储处理器件11工作时所需的数据以及调制解调器14工作时所需的数据,也即处理器件11与调制解调器14可以共享第一存储模块12。在通信装置工作时,处理器件11与调制解调器14均可以对第一存储模块12进行数据读取、写入、擦除等操作。In a specific implementation, the
在具体实施中,可以预先将第一存储模块12划分为至少两个存储区域,其中一个存储区域可以用于存储处理器件11工作时所需的数据,另一个存储区域可以用于存储调制解调器14工作时所需的数据。在将第一存储模块12划分为至少两个存储区域时,可以采用地址区间划分的方式来实现,且不同的存储区域对应的地址空间不存在交集。In a specific implementation, the
例如,第一存储模块12被划分为区域A、区域B以及区域C,区域A的地址区间、区域B的地址区间以及区域C的地址区间相互独立且不存在交集。For example, the
换而言之,在本发明实施例中,可以将第一存储模块12划分为多个独立的存储区域,以避免不同的处理器件11之间、处理器件11与调制解调器14之间的数据相互交叉。In other words, in this embodiment of the present invention, the
可以理解的是,第一存储模块12的某一个或多个区域也可以被不同处理器件11共享,或者被处理器件11与调制解调器14共享。It can be understood that, one or more areas of the
在具体实施中,第二存储模块13可以仅与调制解调器14耦接。在本发明实施例中,第二存储模块13可以为调制解调器14的专属存储模块,其中所存储的数据为调制解调器14工作过程中所需用到的数据。In a specific implementation, the
参照图2,给出了本发明实施例中的一种调制解调器14的结构示意图。Referring to FIG. 2, a schematic structural diagram of a
在具体实施中,结合图1及图2,调制解调器14可以包括存储控制模块141,存储控制模块141可以与第二存储模块13耦接。当接收到数据处理请求时,存储控制模块141可以根据数据处理请求对应的地址,确定是访问第一存储模块12还是访问第二存储模块13。In a specific implementation, with reference to FIG. 1 and FIG. 2 , the
在实际应用中可知,调制解调器14、处理器件11等均属于物理层,应用层可以视作物理层的上层。当上层需要进行数据处理操作时,会生成数据处理请求并下发至物理层,由物理层执行相应的数据处理操作并将得到的处理结果反馈至上层。上层下发的数据处理请求通常可以包括数据处理对应的类型以及地址。例如,数据处理请求为读取数据A,对应的地址为数据A存储的地址。In practical application, it can be known that the
调制解调器14的存储控制模块141在接收到数据处理请求之后,可以从中获取数据处理请求对应的地址,进而确定该地址对应的地址空间处于第一存储模块12还是第二存储模块13。若该地址对应的地址空间处于第一存储模块12,则存储控制模块141访问第一存储模块12;若该地址对应的地址空间处于第二存储模块13,则存储控制模块141访问第二存储模块13。After receiving the data processing request, the
在具体实施中,由于处理器件11以及调制解调器14共享第一存储模块12,因此可以设置较大容量的第一存储模块12。而第二存储模块13为调制解调器14专属存储模块,因此可以设置较小容量的第二存储模块13。在本发明实施例中,可以设置第一存储模块12的存储容量大于第二存储模块13的存储容量。In a specific implementation, since the processing device 11 and the
例如,可以设置第一存储模块12的存储容量为512M,设置第二存储模块13的存储容量为128M。For example, the storage capacity of the
在具体实施中,存储控制模块141可以通过数据总线(BUS)与第一存储模块12进行通信,以根据数据处理请求对第一存储模块12进行相应的操作。In a specific implementation, the
在实际应用中,存在一些对实时性要求较高的应用场景,例如语音通话场景。在本发明实施例中,可以将执行实时性要求较高的应用场景的数据存储至第二存储模块13,将执行实时性要求较低的应用场景的数据存储至第一存储模块12。In practical applications, there are some application scenarios that require high real-time performance, such as voice call scenarios. In this embodiment of the present invention, data for executing application scenarios with higher real-time requirements may be stored in the
在具体实施中,第一存储模块12可以为处理器件11所对应的存储模块。通常情况下,第一存储模块12的存储容量较大,且第一存储模块12可以存在一定的未被处理器件11所使用的存储空间。因此,在本发明实施例中,可以将上述第一存储模块12中未被使用的存储空间充分利用,将其用于存储调制解调器14对应的对实时性要求较低的数据。In a specific implementation, the
由此可见,调制解调器与处理器件共享第一存储模块,可以减少第二存储模块的存储容量,故而能够降低调制解调器的成本。为调制解调器设置专属的第二存储模块,第二存储模块存储对实时性要求较高的数据,可以提高调制解调器的实时性。It can be seen that the modem and the processing device share the first storage module, which can reduce the storage capacity of the second storage module, thereby reducing the cost of the modem. A dedicated second storage module is provided for the modem, and the second storage module stores data requiring higher real-time performance, which can improve the real-time performance of the modem.
在具体实施中,调制解调器14中还可以设置有缓存模块143,缓存模块143可以与存储控制模块141耦接,适于缓存存储控制模块141最近访问的历史数据。缓存模块143可以为一级cache、二级cache等。In a specific implementation, the
存储控制模块141在接收到数据处理请求时,可以先读取缓存模块143。若能够从缓存模块143中命中,则直接返回读取结果;若未能够从缓存模块143中命中,则存储控制模块141根据数据处理请求对应的地址确定对应的存储模块。When the
由于缓存模块143中存储有存储控制模块141访问过的历史数据,因此,若历史数据中存在当前数据处理请求对应的数据,则可以直接从缓存模块143中读取该数据并返回。由于无需从存储模块中查找数据,因此,从缓存模块143中读取数据的速度要快于从存储模块读取数据的速度。Since the
在实际应用中,为节省成本,缓存模块143的存储容量通常较小,因此其中能够存储的数据也较为有限。因此,缓存模块143缓存的历史数据可以是存储控制模块141历史上访问频率最高的数据。In practical applications, in order to save costs, the storage capacity of the
缓存模块143缓存的数据也可以进行更新,当其中存储的数据达到缓存模块143的上限时,可以从中删除一些数据,并添加新的数据。The data cached by the
在具体实施中,调制解调器14还可以包括接口单元144,调制解调器14可以通过接口单元144与处理器件11基于串行总线进行通信。在本发明实施例中,调制解调器14可以通过高速串行计算机扩展总线标准(Peripheral Component Interconnect Express,简称PCI Express,亦即PCIE)与处理器件11进行通信。In a specific implementation, the
在具体实施中,调制解调器14还可以包括功能模块142,功能模块142可以为调制解调器14的微处理器(Micro Controller Unit,MCU),也可以为调制解调器14的硬件加速器等。In a specific implementation, the
在本发明实施例中,第一存储模块12可以为DDR,第二存储模块13也可以为DDR。In this embodiment of the present invention, the
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1308744A (en) * | 1998-07-03 | 2001-08-15 | 艾利森电话股份有限公司 | Caching server network |
| CN1592894A (en) * | 2002-06-27 | 2005-03-09 | 纳佐米通讯公司 | Application processors and memory architecture for wireless applications |
| CN1619524A (en) * | 2003-09-20 | 2005-05-25 | 三星电子株式会社 | Communication device and method having a shared local memory |
| CN1619523A (en) * | 2003-09-20 | 2005-05-25 | 三星电子株式会社 | Communication device and method having a common platform |
| US20090210691A1 (en) * | 2006-10-26 | 2009-08-20 | Jeon-Taek Im | Memory System and Memory Management Method Including the Same |
| US20100153618A1 (en) * | 2008-12-15 | 2010-06-17 | Nvidia Corporation | Shared memory access techniques |
| CN101894082A (en) * | 2010-07-21 | 2010-11-24 | 中兴通讯股份有限公司 | A memory device and smart phone system |
| CN102646073A (en) * | 2012-04-28 | 2012-08-22 | 华为技术有限公司 | Data processing method and device |
| US20130179527A1 (en) * | 2012-01-11 | 2013-07-11 | Renesas Mobile Corporation | Application Engine Module, Modem Module, Wireless Device and Method |
| CN104424145A (en) * | 2013-08-30 | 2015-03-18 | 联想(北京)有限公司 | Electronic device and data transmission method |
| US20170185545A1 (en) * | 2013-01-24 | 2017-06-29 | Qualcomm Innovation Center, Inc. | Hardware accelerated communications over a chip-to-chip interface |
| CN106990910A (en) * | 2015-11-23 | 2017-07-28 | 三星电子株式会社 | Operation method of storage device and storage device |
| CN110275841A (en) * | 2019-06-20 | 2019-09-24 | 上海燧原智能科技有限公司 | Access request processing method, device, computer equipment and storage medium |
-
2020
- 2020-04-27 CN CN202010344625.5A patent/CN111565255B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1308744A (en) * | 1998-07-03 | 2001-08-15 | 艾利森电话股份有限公司 | Caching server network |
| CN1592894A (en) * | 2002-06-27 | 2005-03-09 | 纳佐米通讯公司 | Application processors and memory architecture for wireless applications |
| CN1619524A (en) * | 2003-09-20 | 2005-05-25 | 三星电子株式会社 | Communication device and method having a shared local memory |
| CN1619523A (en) * | 2003-09-20 | 2005-05-25 | 三星电子株式会社 | Communication device and method having a common platform |
| US20090210691A1 (en) * | 2006-10-26 | 2009-08-20 | Jeon-Taek Im | Memory System and Memory Management Method Including the Same |
| US20100153618A1 (en) * | 2008-12-15 | 2010-06-17 | Nvidia Corporation | Shared memory access techniques |
| CN101894082A (en) * | 2010-07-21 | 2010-11-24 | 中兴通讯股份有限公司 | A memory device and smart phone system |
| US20130179527A1 (en) * | 2012-01-11 | 2013-07-11 | Renesas Mobile Corporation | Application Engine Module, Modem Module, Wireless Device and Method |
| CN102646073A (en) * | 2012-04-28 | 2012-08-22 | 华为技术有限公司 | Data processing method and device |
| US20170185545A1 (en) * | 2013-01-24 | 2017-06-29 | Qualcomm Innovation Center, Inc. | Hardware accelerated communications over a chip-to-chip interface |
| CN104424145A (en) * | 2013-08-30 | 2015-03-18 | 联想(北京)有限公司 | Electronic device and data transmission method |
| CN106990910A (en) * | 2015-11-23 | 2017-07-28 | 三星电子株式会社 | Operation method of storage device and storage device |
| CN110275841A (en) * | 2019-06-20 | 2019-09-24 | 上海燧原智能科技有限公司 | Access request processing method, device, computer equipment and storage medium |
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