CN111564175B - Impedance configuration method of memory interface and computer readable storage medium - Google Patents

Abstract

The present invention provides an impedance configuration method for a memory interface, which is executed by a processing unit and includes: setting a first resistance value of an in-chip termination resistor associated with a first receiver as a first default resistance value; setting a first resistance value associated with a second The second resistance value of the drive variable resistor of the transmitter is set to a second default resistance value; the test is performed for a plurality of test combinations, wherein each combination includes a third resistance value associated with the drive variable resistor of the first transmitter and a fourth resistance value of the on-chip termination resistor associated with the second receiver; and storing the test results of each test combination to a specific location in the SRAM, so that the calibration host can obtain each test result from the SRAM The test results of each test combination, and the impedance setting of the memory interface is determined according to the test results.

Description

Impedance configuration method of memory interface and computer-readable storage medium

technical field

The present invention relates to a communication interface, in particular to an impedance configuration method of a memory interface and a computer-readable storage medium.

Background technique

After the speed of the Dynamic Random Access Memory (DRAM) bus reaches a high transfer rate, such as 500Mb/s or higher, system-level signaling problems may occur, for example, from connected peer devices (such as controllers, DRAM modules, etc.) pin lines produce reflections. The above-mentioned signal transmission problem can be solved by adjusting the driver (Driver) and the on-die termination resistor (On-Die Termination ODT). Therefore, the present invention provides a configuration method of a memory interface and a computer-readable storage medium, which are used for calibrating a driver in a memory interface and an in-chip termination resistor.

SUMMARY OF THE INVENTION

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

The present invention provides an impedance configuration method for a memory interface. The method is executed by a processing unit and includes: setting a first resistance value of an on-chip termination resistor associated with a first receiver as a first default resistance value; The second resistance value of the drive variable resistor of the second transmitter is set to a second default resistance value; the tests are performed for a plurality of test combinations, wherein each combination includes a third value associated with the drive variable resistor of the first transmitter a resistance value and a fourth resistance value associated with the on-chip termination resistor of the second receiver; and storing the test results of each test combination to a specific location in the SRAM so that the calibration host can access the memory from the SRAM Obtain the test results of each test combination, and determine the impedance setting of the memory interface according to the test results. The processing unit is coupled to a memory interface, the SRAM and a calibration interface, the memory interface is coupled to a memory device and includes the first transmitter and the first receiver, and the memory device includes the second transmitter and the second receiver.

The present invention also provides a computer-readable storage medium of an impedance configuration of a memory interface for storing a computer program executable by a processing unit, and the computer program when executed by the processing unit implements the method described above.

One of the advantages of the above embodiments is that the calibration host can determine the impedance setting of the memory interface based on the test results of each test combination provided to the calibration host.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application.

FIG. 1 is a schematic diagram of a calibration system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a calibration system according to an embodiment of the present invention.

3 is a graphical user interface for impedance configuration of a memory interface in accordance with an embodiment of the present invention.

4 is a flowchart of a training method for a transmitter and a receiver in a memory interface according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of an initial data table for writing training of DDR4 DRAM according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of an initial data table for read training of DDR4 DRAM according to an embodiment of the present invention.

7 is a flowchart of a method for writing and reading training according to an embodiment of the present invention.

FIG. 8 shows example results of write training for DDR4 DRAM in accordance with an embodiment of the present invention. FIG. 9 is a flowchart of a method for writing training according to an embodiment of the present invention.

【List of reference numerals】

130 substrates

110 Calibrate the main unit

115 processing unit

150 Controllers

170 Memory devices

190 monitors

210 processing unit

230 static random access memory

250 Calibration Interface

270 memory interface

271 Physical layer

273 ODT gear register

275 Drive gear register

277 MAC layer

290 Direct Memory Access Controller

300 Graphical User Interface for Memory Calibration

310 Display box

330 Select button

335 Selection menu

350 Test Progress Box

370 start button

390 Test Information Box

S410～S470 Method steps

S711～S790 method steps

800 Box defining a functioning resistance setting

800a Associated Intermediate Resistance

S910～S970 method steps

Detailed ways

The embodiments of the present invention will be described below with reference to the related drawings. In the figures, the same reference numbers refer to the same or similar components or method flows.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, job processes, components and/or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the present invention is used to modify the components in the claims, and is not used to indicate that there is a priority order, a precedence relationship, or a component precedence Another component, or the chronological order in which method steps are executed, is only used to distinguish components with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present. Other words used to describe the relationship between components can also be read in a similar fashion, such as "between" versus "directly interposed," or "adjacent" versus "directly adjoining," and the like.

Referring to FIG. 1 , the controller 150 and the memory device 170 may be mounted on the substrate 130 , and the controller 150 may be coupled or connected to the memory device 170 through the substrate 130 . The memory device 370 may be a dynamic random access memory (Dynamic Random Access Memory DRAM, etc.). The calibration host 110 is coupled to the controller 150 for issuing commands to request the controller 150 to execute the impedance test method, and then reads the test results from the controller 150 and displays the test results on the display 190 so that the engineer can determine the control according to the test results The impedance configuration (Configurations) in the interface of the device 150 and the memory device 170 . Alternatively, in other embodiments, the calibration host 110 may execute an application program for interpreting the test results and automatically determine impedance settings in the interfaces of the controller 150 and the memory device 170 according to an algorithm. Next, the calibration host 110 may issue a command and the determined impedance setting, requesting the controller 150 to execute the impedance setting method of the memory interface. When the processing unit 210 in the controller 150 loads and executes the relevant firmware or software program code of the impedance setting method of the memory interface, the determined impedance setting is written into the non-volatile storage in the controller 150 and the memory device 170 space, as the factory default value.

Referring to FIG. 2, the controller 150 includes a processing unit 210, which may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other computing capable processors) ), and provides the functions described later when executing software and/or firmware instructions of the Mass Production Integrated System Program MPISP (Mass Production Integrated System Program MPISP). The controller 150 may include a calibration interface 250, such as an I2C interface, for the calibration host 110 to send commands to the processing unit 210 through the calibration interface 250 to start and execute the impedance test and setting method of the memory interface. After the calibration is completed, the calibration host 110 can request the direct memory access controller (Direct Memory Access DMA Controller) to read the test results from the default part of the static random access memory (Static Random Access Memory SRAM) 230 through the calibration interface 250 . MPISP can be stored in a Read Only Memory ROM (not shown in FIG. 2 ) in the controller 150 when it leaves the factory, or be transmitted to the controller 150 by the test host 110 through the calibration interface 250 or other interfaces before starting the calibration .

In some embodiments, the controller 170 may also be referred to as an Application-Specific Integrated Circuit ASIC-side, and the memory device 170 may be a DRAM, referred to as a DRAM side, for buffering the execution of software and firmware The data required in the process of the instruction, such as variables, data tables, etc., as well as various user data. The memory interface 270 can communicate with the DRAM using a Double Data Rate DDR communication protocol, for example, the third generation double data rate (DDR3), the low power DDR3 (Low Power LPDDR3), the fourth generation double data rate (DDR3) rate (DDR4) or other interface. The input and output signals between the memory interface 270 and the DRAM may include reset, CK, CK_N, CKE, ODT, CS_N, ACT_N, BG, BA, A, DM, DQS, DQS_N, DQ_lower, DQ_upper, and the like.

The memory interface 470 may include a physical layer (Physical Layer PHY) 471 having circuitry connected to the memory device 370 . The DDR communication protocol and associated physical layer 471 may provide the ability to communicate for transmitting commands, addresses, and data, etc. to and receiving data, addresses, and information, etc. from memory device 370 . The physical layer 471 includes a transmitter (Transmitter) and a receiver (Receiver) for transmitting signals to the receiver of the memory device 370 and receiving signals from the transmitter of the memory device 370, respectively. The output end of the transmitter (also referred to as a driver) can be connected to a variable resistance (Variable Resistance, which can be referred to as a driving variable resistance), so that the processing unit 210 can change the driving-stage register (Driving-stage Register) 275 by changing The setting can adjust the resistance of the driving variable resistor, and then change the driving strength of the output. On the other hand, the input end of the receiver can be connected to a variable resistor (which can be called an ODT variable resistor), so that the processing unit 210 can change the on-die termination resistance stage register (On-DieTermination ODT-stage Register) 275 to adjust the impedance of the ODT variable resistor (Impedance).

The drive gear register 275 can store a 4-bit value, as shown in Table 1:

Table 1

value (decimal) Z target (ohms) 0 480 1 240 2 160 3 120 4 96 5 80 6 68.6 7 60 8 53.3 9 48 10 43.6 11 40 12 36.9 13 34.3 14 32 15 30

For example, when the value stored in the driving gear register 275 is set to 0, the resistance value of the driving variable resistor is adjusted to 480ohm. When the value stored in the drive gear register 275 is set to 1, the resistance value of the drive variable resistor is adjusted to 240ohm. The rest of the settings can be deduced by analogy to the resistance value change of the driving variable resistor, and will not be repeated for brevity.

The ODT gear register 273 can store 4-bit values, as shown in Table 2:

Table 2

For example, when the value stored in the ODT gear register 273 is set to 2, the resistance value of the driving variable resistor is adjusted to 120ohm. The rest of the settings can be deduced by analogy to the resistance value change of the ODT variable resistor, and will not be repeated for brevity.

Conversely, the memory device 170 may also include similar variable resistor settings for changing the output drive strength and ODT impedance. The processing unit 210 may instruct the MAC layer 277 to send a command to the memory device 170 through the physical layer 271 for changing the output driving strength of the transmitter and the ODT resistance value of the receiver in the memory device 170 .

When the memory interface 470 communicates with the memory device 170 using the DDR3 communication protocol, the processing unit 210 may instruct the MAC layer 277 to send an I/O Configuration Command and setting values to the memory device 170 through the physical layer 271 . The memory interface 470 can instruct the memory device 170 to adjust the resistance of the driving variable resistor to a specific level through the A5 and A1 signals, as shown in Table 3:

table 3

A5 A1 Output driver resistance 0 0 RZQ/6 0 1 RZQ/7 1 0 Reserved 1 1 Reserved

Those skilled in the art understand that RZQ is 240ohm. For example, when the A5 and A1 signals are both 0, the memory device 170 adjusts the resistance of the driving variable resistor to 40ohm (ie, RZQ/6). When the A5 and A1 signals are 1 and 0 respectively (preserving the set value), the memory device 170 may not change the resistance value of the driving variable resistor. Changes in the resistance values of the driving variable resistors in the memory device 170 for the remaining settings can be deduced in the same way, and are not repeated for brevity. In addition, the memory interface 470 can instruct the memory device 170 to adjust the resistance value of the ODT variable resistor therein to a specific level through the A9, A6 and A2 signals, as shown in Table 4:

Table 4

A9 A6 A2 Rtt_Nom 0 0 0 Disable 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6 1 0 0 RZQ/12 1 0 1 RZQ/8 1 1 0 reserve 1 1 1 reserve

For example, when the A9, A6 and A2 signals are all 0, the memory device 170 may not enable ODT. When the A9, A6, and A2 signals are 0, 0, and 1, respectively, the memory device 170 can adjust the resistance of the ODT variable resistor to 60ohm (ie, RZQ/4). When the A9, A6 and A2 signals are respectively 1, 1 and 0 (preserving the set value), the memory device 170 may not change the resistance value of the driving variable resistor. Changes to the resistance value of the ODT variable resistor in the memory device 170 for the remaining settings can be deduced by analogy, and are not repeated for brevity.

When the memory interface 470 communicates with the memory device 170 using the DDR4 communication protocol, the processing unit 210 may instruct the MAC layer 277 to send the I/O configuration commands and setting values to the memory device 170 through the physical layer 271 . The memory interface 470 can instruct the memory device 170 to adjust the resistance of the driving variable resistor to a specific level through the A5 and A1 signals, as shown in Table 5:

table 5

The details of the resistance value change of the driving variable resistor described in Table 5 can be referred to the description of Table 3, and are not repeated for brevity. In addition, the memory interface 470 can instruct the memory device 170 to adjust the resistance value of the ODT variable resistor therein to a specific level through the A9, A6 and A2 signals, as shown in Table 6:

Table 6

A9 A6 A2 ODT resistance 0 0 0 Disable 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6 1 0 0 RZQ/1 1 0 1 RZQ/5 1 1 0 RZQ/3 1 1 1 RZQ/7

The details of the resistance value change of the ODT variable resistor described in Table 6 can be referred to the description of Table 4, and are not repeated for brevity.

When the memory interface 470 communicates with the memory device 170 using the LPDDR3 communication protocol, the processing unit 210 may instruct the MAC layer 277 to send a ModeRegister Write Command and a setting value to the memory device 170 through the physical layer 271 . The memory interface 470 may instruct the memory device 170 to perform an I/O Configuration by writing "03H" to MA[7:0] in the mode register, and writing a specific value to OP<3 in the mode register: 0> Instruct the memory device 170 to adjust the resistance of the drive variable resistor therein to a specific level, as shown in Table 7:

Table 7

For example, when "0010" (the default value) is written to Op<3:0> in the mode register, the memory device 170 adjusts the resistance value of the driving variable resistor to 34.3ohm (ie, RZQ/6). When "1001" is written to Op<3:0> in the mode register, the memory device 170 adjusts the pull-down resistance of the drive variable resistor to 34.3ohm, and the pull-up resistance Adjust it to 40ohm, and adjust the terminal resistance to 240ohm. When Op<3:0> in the mode register is written with "0000" (set value reserved) or other values not listed in Table 7, the memory device 170 may not change the resistance value of the driving variable resistor. Changes in the resistance values of the driving variable resistors in the memory device 170 for the rest of the settings can be deduced by analogy, and are not repeated for brevity.

Additionally, the memory interface 470 may instruct the memory device 170 to perform ODT control by writing "0BH" to MA[7:0] in the mode register, and instruct the memory device to perform ODT control by writing a specific value to OP<1:0> in the mode register 170 adjusts the resistance of the ODT variable resistor to a specific level, as shown in Table 8:

Table 8

Op<1:0> ODT resistance 00 Disable (default) 01 reserve 10 RZQ/2 11 RZQ/1

For example, when Op<1:0> in the mode register is written with "00" (the default value), the memory device 170 may not enable ODT. When Op<1:0> in the mode register is written with "01" (preserving the set value), the memory device 170 may not change the resistance value of the ODT variable resistor. When "10" is written to Op<1:0> in the mode register, the memory device 170 adjusts the resistance value of the ODT variable resistor to 120ohm (ie, RZQ/2). Changes to the resistance value of the ODT variable resistor in the memory device 170 for the remaining settings can be deduced by analogy, and are not repeated for brevity.

The processing unit 115 in the calibration host 110 can execute a calibration tool, and the calibration tool can provide a human-machine interface to facilitate the engineer to configure the impedance of the memory interface. The display 190 displays a memory calibration graphical user interface (hereinafter referred to as calibration GUI) 300 as shown in FIG. 3 . Calibration GUI 300 may provide selection buttons 330 . When the user clicks on the selection button 330, the processing unit 115 may execute a click event handler (On_click() Event Handler) of the selection button 330 for displaying the selection menu 335 on the display 190, including a plurality of items, each item associated with An MPISP stored in the read-only memory of the controller 150, such as a DRAM MPISP. Display box 310 may display the MPISP as determined by the user by operating selection menu 335 . Calibration GUI 300 may additionally provide a start button 370. When the user clicks the start button 370 , the processing unit 115 of the calibration host 110 can execute the click event handler of the start button 330 to instruct the processing unit 210 of the controller 150 to load and execute the MPISP determined by the user through the calibration interface 250 . The calibration host 110 can continuously obtain the test results of the transceivers in the memory interface 270 and the memory device 170 through the calibration interface 250 and the direct memory access controller 290 , and can update the content of the test progress block 350 and the calibration information block 390 accordingly.

When the processing unit 210 loads and executes the designated MPISP, the processing flow shown in FIG. 4 may be implemented. After initializing the memory device 170, the processing unit 210 can execute the instruction of the function vInitDramZQRemapIdx() to initialize the data table for storing the test results. (step S410). Next, the processing unit 210 executes the instruction of the function vScanDramWindow(WrTraining) to execute the memory write training (Write-Training) (step S430), and executes the instruction of the function vScanDramWindow(RdTraining) to execute the memory read training (Read-Training) (step S450). It should be noted that although the program code of a single function is used with different input parameters "WrTraining" and "RdTraining" to implement memory writing and reading training, those skilled in the art can also write and read the memory. Read training is implemented in a different function. In other embodiments, the processing unit 210 may perform memory read training first, followed by memory write training. In other embodiments, the processing unit 210 may not perform memory reading training, but directly set the impedance in the ODT of the receiver of the controller 150 and the driving variable resistor of the transmitter of the memory device 170 for memory reading is the default value (eg mid-range). Finally, the test result is provided to the static random access memory (Static Random Access Memory SRAM) 230 (step S470).

In step S410, the processing unit 210 may initialize different data tables for writing and reading training respectively, so as to record subsequent test results. Take DRAM as an example: the training data table contains two axes: one axis is related to the signal strength of the ODT on the DRAM side, arranged from weak to strong or from strong to weak; the other axis is related to the driving signal strength of the ASIC side, from weak to weak. Arranged from strong to weak. Reading the training data table contains two axes: one axis is related to the drive signal strength at the DRAM side, arranged from weak to strong or from strong to weak; the other axis is related to the signal strength of the ODT at the ASIC side, from weak to strong or from strong to strong Weak permutation. The purpose of writing training is to optimize the resistance matching between the ASIC-side driving variable resistor and the DRAM-side ODT, while the purpose of reading training is to optimize the resistance matching between the DRAM-side driving variable resistor and the ASIC-side ODT. Such re-mapping (Remapping) can help engineers or application programs to interpret the algorithm and find the appropriate resistance gear more efficiently. The initialized data table may be stored in the SRAM 230 .

Take DDR4DRAM as an example: refer to Figure 5. In order to facilitate the interpretation of engineers or applications, the size (Size) of the training data table is 16x16 bytes, and each byte records when the drive variable resistance at the ASIC side is set to the first resistance. The test result when the ODT of the DRAM terminal is set to the second resistance value. The storage cells (Cells) of the data table can be conceptually divided into groups of 16 bytes. For example, when the drive variable resistor at the ASIC side is set to a specific resistance value (such as 480ohm), change the ODT resistance value of the DRAM side from high to low (such as never enable the ODT to set the ODT resistance to RZQ/7). Test Results. Alternatively, when the ODT resistance value of the DRAM side is set to a specific resistance value (RZQ/1), the test result of changing the resistance value of the driving variable resistor at the ASIC side (eg, from 480ohm to 30ohm) is changed from high to low. Since the ODT gear of DDR4DRAM is only 8 gears, the value of the memory cells from 0h to 7h of each specific resistance value (that is, each row) of the drive variable resistor associated with the ASIC side is initially "0x00". The values of the memory cells from 8h to Fh are initially "0x05" (which can be called ignore values) to tell the engineer or application that the test result can be ignored.

Take DDR4DRAM as an example: refer to Figure 6, in order to facilitate the interpretation of engineers or applications, the capacity of reading the training data table is 16x16 bytes, and each byte records when the driving variable resistance of the DRAM end is set to the first resistance value and the ASIC The test result when the ODT of the terminal is set to the second resistance value. The storage cells of the data table can be conceptually divided into groups of 16 bytes. For example, when the drive variable resistor at the DRAM side is set to a specific resistance value (eg RZQ/5), the test result of changing the ODT resistance value at the ASIC side (eg, from 120ohm to 40ohm) is changed from high to low. Or, when the ODT resistance value of the ASIC side is set to a specific resistance value (120ohm), the test result of changing the resistance value of the driving variable resistor of the DRAM side (eg from RZQ/5 to RZQ/7) from high to low. Since DDR4DRAM has only 2 files for the drive position, the memory cells from 0h to 1h associated with each specific resistance value (that is, each row) of the ASIC-side ODT are initially "0x00", while 2h to The values of the memory cells of Fh are all initially "0x05". Those skilled in the art can change the ignored value to any value between "0x05" and "0xFF", and the present invention is not limited thereby.

In some embodiments, for the details of writing training described in step S430, reference may be made to the method flowchart shown in FIG. 9 . The method is implemented by the processing unit 210 when the program code of the software or firmware module is loaded and executed. The resistance value of the drive variable resistor of the transmitter at the terminal is set to the default resistance value (step S930 ), and tests are performed for a plurality of different test combinations according to the scanning sequence, wherein each test combination includes a drive variable associated with the transmitter of the ASIC terminal. The resistance value of the variable resistor and the resistance value of the ODT associated with the receiver at the device end (step S950 ); and storing the test results of each test combination to a specific location in the SRAM 230 , so that the calibration host 110 can access the SRAM 230 through the calibration interface 250 Obtain the test result of each test combination (step S970). Details of scan sequence, test combinations, test procedures and test results can be found in the following paragraphs.

In other embodiments, for details of the training described in steps S430 and S450, reference may be made to the method flowchart shown in FIG. 7 . Whether it is memory writing or reading training, the whole process will repeatedly execute a cycle (steps S711 to S790 ) until all the relevant resistance gears of the ASIC and device ends have been tested (that is, scanned) (step S790 ) "Yes" in the path). The execution details of write training and read training are described below:

When it is determined to be writing training (the "Yes" path in step S711 ), the processing unit 210 may determine the resistance values of the ODT on the ASIC side and the driving variable resistor on the device side as default resistance values, and determine the ODT and the device side according to the scanning sequence. The resistance level of the drive variable resistor at the ASIC end (step S713 ). Taking DDR4DRAM as an example, the default resistance value of the ODT resistance on the ASIC side can be 60ohms in Table 2, and the default resistance value of the drive variable resistor on the device side can be RZQ/5 in Table 5. Regarding the scanning sequence, for example, referring to FIG. 5 , the processing unit 210 can first fix the resistance of the ODT on the device side to a specific gear, and then sequentially change the resistance of the driving variable resistor on the ASIC side from 480ohm to 30ohm. After all the resistance values of the drive variable resistors at the ASIC end have been tested, fix the ODT resistance value at the device end to the next gear and continue the test. Next, the memory device is initialized (step S730). Taking DDR4 DRAM as an example, in step S730, the processing unit 410 can change the value of the ODT gear register 273 to the default resistance value determined in step S713, and change the drive gear register 275 to the gear determined according to the scanning sequence in step S713. In addition, the processing unit 410 can instruct the MAC layer 277 to send an I/O configuration command and a setting value to the memory device 170 through the physical layer 271, so as to set the resistance value of the driving variable resistor of the memory device 170 as the default determined in step S713 resistance value, and the ODT resistance value of the memory device 170 is set to the gear level determined according to the scanning sequence in step S713. The storage space of the memory device 170 includes a small test part. In step S730 , the memory device 170 can perform test-write-then-read in the test part, which is also called device-side self-training. The memory device 170 can send the information of whether the device-side self-training has passed to the processing unit 210 through the memory interface 270 . When the device-side self-training fails (the path of "No" in step S751), the processing unit 210 may store "0x01" in the corresponding memory cell written in the training data table as the test result (step S773).

In order to improve the reliability of the test, when the device-side self-training is passed (the path of "Yes" in step S751 ), the processing unit 210 may further perform a random read/write test (step S753 ). In the random read/write test, the processing unit 210 may instruct the MAC layer 277 to write 8MB random data pattern data to the memory device 170, and then instruct the MAC layer 277 to read back data from the memory device 170, and check the read data. Whether the returned data is consistent with the previously written data. The processing unit 210 stores the test results in the corresponding storage cells written in the training data table according to the execution of the random read/write test (step S773). In detail, when a read timeout (Read Timeout) occurs, the processing unit 210 may store "0x02" to a corresponding storage cell in the writing training data table. When the read back data is inconsistent with the previously written data, the processing unit 210 may store "0x03" to the corresponding memory cell in the written training data table. When a Write Timeout occurs, the processing unit 210 may store "0x04" to the corresponding storage cell in the write training data table. When the read-back data is consistent with the previously written data, the processing unit 210 may store "0x00" to the corresponding memory cell in the written training data table, or in other embodiments, may not store any data in the written training data table , because the corresponding cell is already initialized to "0x00".

When it is determined to be read training (the "No" path in step S711 ), the processing unit 210 can determine the resistance value of the drive variable resistor on the ASIC side and the resistance value of the ODT on the device side as default resistance values, and determine the drive variable resistor on the device side according to the scanning sequence. The resistance level of the varistor and the ODT of the ASIC terminal (step S715 ). Taking DDR4DRAM as an example, the default resistance value of the drive variable resistor on the ASIC side can be 60ohms in Table 1, and the default resistance value of the ODT resistance on the device side can be RZQ/4 in Table 6. Regarding the scanning sequence, for example, referring to FIG. 6 , the processing unit 210 can first fix the resistance value of the drive variable resistor at the device end to a specific gear, and then sequentially change the ODT resistance value at the ASIC end from 120ohm to 40ohm. After all ODT resistance values at the ASIC end have been tested, the resistance value of the drive variable resistor at the device end is fixed at the next gear and the test continues. Next, the memory device is initialized (step S730). For details of the execution of step S730, reference may be made to the descriptions in the above paragraphs, which are not repeated for brevity. When the device-side self-training is passed (the "Yes" path in step S751 ), the processing unit 210 may further perform a random read/write test (step S753 ). For details of the execution of step S753, reference may be made to the descriptions in the above paragraphs, which are not repeated for brevity. Next, the processing unit 210 stores the test results in the corresponding storage cells in the read training data table according to the execution of the random read/write test (step S775 ). In detail, when a read timeout occurs, the processing unit 210 may store "0x02" to a corresponding memory cell in the read training data table. When the read back data is inconsistent with the previously written data, the processing unit 210 may store "0x03" to the corresponding memory cell in the read training data table. When a write timeout occurs, the processing unit 210 may store "0x04" to a corresponding memory cell in the read training data table. When the read-back data is consistent with the previously written data, the processing unit 210 may store "0x00" into the corresponding memory cell in the read training data table, or in other embodiments, may not store any data in the read training data table , because the corresponding cell is already initialized to "0x00".

It will be appreciated here that the more types of errors recorded in the memory cells may facilitate an engineer or a program application executed by the processing unit 115 to diagnose impedance matching problems arising from a particular setup.

In step S470, the processing unit 115 of the calibration host 110 can drive the direct memory access controller 290 through the calibration interface 250 to read the content of a specific part in the SRAM 230 as a basis for configuring the transceiver of the memory interface. The read content can be displayed on the display 190 for reference by engineers when configuring. Referring to the example results shown in FIG. 8 , when the engineer or the processing unit 115 executes the application program, it can be found that when the resistance value of the driving variable resistor at the ASIC side is between 60ohm and 36.9ohm and the resistance value of the ODT at the device side is between RZQ/ Between 1 and RZQ/5 (as shown in the dashed box 800), the memory interface 270 can operate normally. When the engineer or the processing unit 115 executes the application program, the intermediate value 800a in the normal part 800 can be written to the drive variable resistor and the ODT resistance gear of the ASIC side and the drive variable resistor and ODT resistance gear of the device side. into the non-volatile storage space in the controller 150 as a factory setting.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as an operating system of a computer, a driver program of specific hardware in the computer, or a software program. Furthermore, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the method of the embodiment of the present invention into a calculator program, which will not be described again for the sake of brevity. The calculator program implemented by the method according to the embodiment of the present invention can be stored in a suitable computer-readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, or can be stored in appropriate vehicle) to access the web server.

Although the components described above are included in FIG. 2 , it is not excluded that more other additional components can be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of FIGS. 4 , 7 and 9 are executed in the specified order, those skilled in the art can modify the steps between these steps on the premise of achieving the same effect without violating the spirit of the invention. order, therefore, the present invention is not limited to use only the above-mentioned order. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims (14)

1. An impedance configuration method for a memory interface, implemented by a processing unit when loading and executing program codes of a software or firmware module, wherein the processing unit is coupled to a memory interface, a static random access memory and a calibration interface, and the memory interface is coupled to A memory device is connected and includes a first transmitter and a first receiver, the memory device includes a second transmitter and a second receiver, wherein the method includes: For the first training procedure, the first resistance value of the on-chip termination resistor associated with the first receiver for the second transmission from the memory device is set as a first default resistance value receiver to receive the signal; for the first training procedure, setting the second resistance value of the drive variable resistor associated with the second transmitter to a second default resistance value; In the first training procedure, tests are performed for a plurality of first test combinations, wherein each of the first test combinations includes a third resistance value and a fourth resistance value, and the third resistance value is associated with the first transmission The drive variable resistance of the controller, and the fourth resistance value is associated with the on-chip termination resistance of the second receiver, wherein the first transmitter in the memory interface of the controller is used to send a signal to the memory device in the memory device. the second receiver; and storing the test results of each of the first test combinations in a specific location of the SRAM, so that the calibration host can obtain the test results of each of the first test combinations from the SRAM through the calibration interface, Wherein the first training program includes multiple cycles, each of the cycles corresponding to one of the multiple first test combinations, including the following steps: changing the driving variable resistance of the first transmitter according to the corresponding third resistance value; changing the on-chip termination resistance of the second receiver according to the corresponding fourth resistance value; and The test is performed under the condition that the on-chip termination resistance of the first receiver is fixed to the first default resistance value, and the driving variable resistance of the second transmitter is fixed to the second default resistance value. 2. The impedance configuration method of the memory interface according to claim 1, characterized in that, comprising: receiving commands and impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host based on the test results of the first test combination; and The impedance setting is written into the non-volatile storage space of the controller and the memory device as a factory default value, wherein the controller includes the processing unit. 3 . The impedance configuration method of a memory interface according to claim 1 , wherein the test result of the first test combination is stored in a data table, and the data table includes a first axis and a second axis. 4 . axis, the first axis is related to the signal strength of the on-chip termination resistance of the memory device, arranged from weak to strong or from strong to weak, the second axis is related to the drive signal strength of the memory interface, from weak to strong Or in order from strong to weak. 4 . The impedance configuration method of the memory interface as claimed in claim 3 , wherein the data table includes a plurality of bytes, and each byte records when the drive variable resistance of the memory interface is set to the fifth resistance. 5 . The test result when the on-chip termination resistance of the memory device is set to the sixth resistance value. 5 . The impedance configuration method of a memory interface as claimed in claim 4 , wherein when the byte is the first value, it means that the memory device fails to pass the test read and write in the test part of the storage space. 6 . 6. The impedance configuration method of a memory interface as claimed in claim 4, wherein when the byte is the second value, it means that a read timeout occurs when the processing unit instructs the memory interface to perform a random read/write test; when When the byte is the third value, it means that a write timeout occurs when the processing unit instructs the memory interface to perform random read and write tests; and when the byte is the fourth value, it means that the processing unit instructs the memory interface to perform random read and write tests. The data read back during the test is inconsistent with what was previously written. 7. The impedance configuration method of a memory interface according to claim 1, characterized in that, comprising: For a second training procedure, set the fifth resistance value of the on-chip termination resistor associated with the second receiver to a third default resistance value, wherein the second receiver is used to retrieve data from the first in the memory interface The transmitter receives the signal; For the second training procedure, setting the sixth resistance value of the driving variable resistor associated with the first transmitter to a fourth default resistance value; In the second training procedure, tests are performed for a plurality of second test combinations, wherein each of the second test combinations includes a seventh resistance value and an eighth resistance value, and the seventh resistance value is associated with the second transmission The drive variable resistor of the controller, and the eighth resistance value is associated with the on-chip termination resistor of the first receiver, wherein the second transmitter is used to send a signal to the first receiver in the memory interface of the controller. a receiver; and Store the test results of each of the second test combinations in a specific location of the SRAM, so that the calibration host can obtain the test results of each of the second test combinations from the SRAM through the calibration interface . 8. The impedance configuration method of the memory interface according to claim 7, characterized in that, comprising: receiving commands and impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host based on the test results of the first test set and the second test set; and The impedance setting is written into the non-volatile storage space of the controller and the memory device as a factory default value, wherein the controller includes the processing unit. 9. An impedance-configured computer-readable storage medium of a memory interface for storing a computer program executable by a processing unit, wherein the processing unit is coupled to a memory interface, a static random access memory, and a calibration interface, the memory interface A memory device is coupled and includes a first transmitter and a first receiver, the memory device includes a second transmitter and a second receiver, and characterized in that, when the computer program is executed by the processing unit, the following steps are implemented: For the first training procedure, the first resistance value of the on-chip termination resistor associated with the first receiver for the second transmission from the memory device is set as a first default resistance value receiver to receive the signal; for the first training procedure, setting the second resistance value of the drive variable resistor associated with the second transmitter to a second default resistance value; In the first training procedure, tests are performed for a plurality of first test combinations, wherein each of the first test combinations includes a third resistance value and a fourth resistance value, and the third resistance value is associated with the first transmission The drive variable resistance of the controller, and the fourth resistance value is associated with the on-chip termination resistance of the second receiver, wherein the first transmitter in the memory interface of the controller is used to send a signal to the memory device in the memory device. the second receiver; and storing the test results of each of the first test combinations in a specific location of the SRAM, so that the calibration host can obtain the test results of each of the first test combinations from the SRAM through the calibration interface, Wherein the first training program includes multiple cycles, each of the cycles corresponding to one of the multiple first test combinations, including the following steps: changing the driving variable resistance of the first transmitter according to the corresponding third resistance value; changing the on-chip termination resistance of the second receiver according to the corresponding fourth resistance value; and The test is performed under the condition that the on-chip termination resistance of the first receiver is fixed to the first default resistance value, and the driving variable resistance of the second transmitter is fixed to the second default resistance value. 10. The impedance-configured computer-readable storage medium of claim 9, wherein when the computer program is executed by the processing unit, the following steps are implemented: receiving commands and impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host based on the test results of the first test combination; and The impedance setting is written into the non-volatile storage space of the controller and the memory device as a factory default value, wherein the controller includes the processing unit. 11. The computer-readable storage medium of the impedance configuration of the memory interface according to any one of claims 9 or 10, wherein the test result of the first test combination is stored in a data table, and the data table contains The first axis and the second axis, the first axis is related to the signal strength of the on-chip termination resistance of the memory device, arranged from weak to strong or from strong to weak, the second axis is related to the drive signal of the memory interface Intensity, arranged from weak to strong or from strong to weak. 12. The impedance-configured computer-readable storage medium of claim 11, wherein the data table contains a plurality of bytes, each of the bytes recording when the drive of the memory interface is variable The test result when the resistance is set to the fifth resistance value and the on-chip termination resistance of the memory device is set to the sixth resistance value. 13 . The computer-readable storage medium with impedance configuration of the memory interface as claimed in claim 12 , wherein when the byte is the first value, it represents that the memory device performs trial reading and writing in the test part of the storage space. 14 . Fail. 14. The computer-readable storage medium with impedance configuration of the memory interface of claim 12, wherein when the byte is the second value, it occurs when the processing unit instructs the memory interface to perform a random read/write test read timeout; when the byte is the third value, it means that the processing unit instructs the memory interface to perform a random read and write test when a write timeout occurs; and when the byte is the fourth value, it means that the processing unit instructs the When the memory interface performs random read and write tests, the data read back is inconsistent with the previously written data.

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