CN111552205A - Manage PWM trip signals from multiple sources - Google Patents

Abstract

Embodiments of the present application relate to managing pulse width modulated trip signals from multiple sources. An integrated communication subsystem (ICSS) (200) includes a pulse width modulator (244) that drives a power stage, such as a motor. The pulse width modulator (244) is configured to shut down the power stage when the pulse width modulator (244) receives a trip signal from a logic circuit (421) of the ICSS (200). The logic circuit (421) can be easily reprogrammed to send a trip signal only when a specific error condition is detected. In addition, the ICSS (200) contains one or more filters that adjust the sensitivity of the logic circuit (421) to error signals, thereby enabling the ICSS (200) to distinguish between true errors requiring shutdown and negligible transient fluctuations during operation of the ICSS (200).

Description

Manage PWM trip signals from multiple sources

Cross-references to related applications

This application claims priority to US Provisional Application No. 62/677,878, filed May 30, 2018, and US Provisional Application No. 62/786,477, filed December 30, 2018, which Both cases are fully incorporated herein by reference.

technical field

The present invention generally relates to industrial communicators that may be formed as part of an integrated circuit such as a digital signal processor (DSP), a system on a chip (SoC) or an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) system (ICSS). More particularly, the present invention relates to systems and methods for managing pulse width modulated trip signals from multiple sources in an industrial control subsystem.

Background technique

Industrial motor control applications such as robotics, servo drives, and computer numerical controls require the ability to shut down powered devices when faulty conditions occur that can cause damage to motors, machines, and/or people.

SUMMARY OF THE INVENTION

At least one example of the invention includes a control system comprising: a power stage; a pulse width modulator coupled to the power stage, the pulse width modulator configured to receive a trip on the pulse width modulator a processor coupled to the pulse width modulator; a logic circuit coupled to the pulse width modulator and the processor, the logic circuit comprising: a first interface that including a plurality of inputs, wherein the plurality of inputs include: a first input configured to receive a first trip event indication signal originating at the pulse width modulator; a second input configurable to receive a source From a second trip event indication signal at an electronic device releasably coupled to the second input at a connection port; and a third input configured to receive a third input from the processor a trip event indication signal; and a second interface comprising: a first selection input configured to receive the first selection; and a second selection input configured to receive the second selection, wherein the logic circuit is configured to The trip signal is sent to the pulse width modulator when the logic circuit receives at least one of the three trip event indication signals.

At least one other example of the invention includes a logic circuit coupled to a pulse width modulator, the logic circuit configured to receive a plurality of inputs, the plurality of inputs including: a first input corresponding to a a first signal at the pulse width modulator; a second input corresponding to a second signal originating at the electronic device; and a third input corresponding to a third signal originating at one or more processors signal; wherein the logic circuit is configured to controllably select which of the plurality of inputs to output to a pulse width modulator as a trip signal to cause the pulse width modulator to turn off by the pulse width modulator drive power stage.

At least one additional example of the present invention is a method for managing a trip signal for a pulse width modulator, the method comprising: driving a power stage using the pulse width modulator; receiving a first input at a logic circuit, the the first input corresponds to a first trip event indication signal originating at the pulse width modulator; a second input is received at the logic circuit, the second input corresponding to a first trip event indication originating at the electronic device two trip event indication signals, the electronic device being releasably coupled to the logic circuit at a port; receiving a third input, the third input corresponding to a third trip event indication signal from the processor; by the logic The circuit selects which input to output to the pulse width modulator as a trip signal to cause the pulse width modulator to turn off a power stage driven by the pulse width modulator, wherein selecting includes selecting from the first input, the selecting from a plurality of inputs of the second input and the third input; and outputting the selected input from the logic circuit.

Description of drawings

To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

1 is a block diagram of a system with an architecture according to an example of the present invention;

Figure 2A illustrates a first communication and control portion of a system such as the system illustrated in Figure 1, according to an example of the present invention;

2B illustrates shared component portions of a system such as the system illustrated in FIG. 1, according to an example of the present invention;

Figure 2C illustrates a second communication and control portion of a system such as the system illustrated in Figure 1, according to an example of the present invention;

3 illustrates aspects of pulse width generation according to an example of the present disclosure;

4A illustrates the logical configuration of a pulse width modulation monitor and controller according to an example of this disclosure;

4B illustrates a trip signal logic unit interacting with the logic configuration illustrated in FIG. 4A, according to an example of the present invention;

5 illustrates aspects of a system such as the system illustrated in FIGS. 1 and 2A-2C, according to an example of the present disclosure;

6 is a state diagram showing the relationship of possible states of one or more components of a system, such as the system illustrated in FIGS. 1 and 2A-2C, according to an example of this disclosure; and

7 is a block diagram of a state machine 700 according to an example of the present invention.

Detailed ways

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the examples disclosed herein. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the disclosed examples.

When introducing elements of various examples of this disclosure, the articles "a, an" and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that additional elements may be present in addition to the listed elements. The examples discussed below are intended to be illustrative in nature and should not be construed to mean that the examples described herein must be preferred in nature.

The examples described in this disclosure are neither mutually exclusive nor mutually exhaustive. References to "one instance" or "an instance" should not be read as excluding the existence of additional instances that also incorporate the recited features.

As used herein, the term "media" refers to one or more non-transitory physical media that together store the content described as being stored thereon. The term "media" does not include signals, electrical or otherwise. Examples may include non-volatile secondary storage, read only memory (ROM), and/or random access memory (RAM).

As used herein, the terms "application" and "function" refer to one or more computing modules, programs, processes, workloads, threads, and/or a set of computing instructions executed by a computing system. Example implementations of applications and functions include software modules, software objects, software instances, and/or other types of executable code.

One or more embodiments of the invention are implemented on a 'system on a chip' (SoC). In at least one example, an SoC includes multiple hardware components. In at least one example, an SoC includes a microcontroller, a microprocessor, a digital signal processor (DSP) core, and/or a multiprocessor SoC with more than one processor core. In at least one example, the SoC includes a memory block that includes a selection of ROM, RAM, electrically erasable programmable read-only memory, and flash memory. In at least one example, the SoC includes a timing source including an oscillator and a phase locked loop. In at least one example, the SoC includes peripheral devices including a counter-timer, a real-time timer, and a power-on reset generator. In at least one example, the SoC includes an analog interface including an analog-to-digital converter and a digital-to-analog converter. In at least one example, the SoC includes a voltage regulator and power management circuitry.

In at least one example, an SoC includes both the hardware described above and software and/or firmware that controls a microcontroller, microprocessor or DSP core, peripherals, and interfaces.

Within the present invention, pulse width modulation refers to the process of modifying the width of the pulses in a pulse train in proportion to a small control signal; the larger the control voltage, the wider the resulting pulse becomes. By using a sine wave of the desired frequency as the control voltage for a pulse width modulation control circuit (also referred to as a 'pulse width modulator'), it is possible to generate a high power waveform with an average voltage suitable for driving alternating current (AC) The motor changes in a sine wave manner. AC motors are used in many industrial applications such as robotics, servo drives and computer numerical controls. Pulse width modulation is a way of describing a digital (binary/discrete) signal formed by a modulation technique that involves encoding a message into a pulsed signal.

In an example of the present invention, pulse width modulation is used to control the amount of power supplied to an electrical device including an inertial load such as a motor. The average value of the voltage (and current) fed to the load is controlled by rapidly turning on and off the switch between the power supply and the load. The longer the switch is on, the higher the total power supplied to the load will be compared to the period in which the switch is off. In an example of the present invention, the pulse width modulation switching frequency is much higher than the switching frequency that will affect the load (device that uses power). Make the resulting waveform as sensed by the load (eg, motor) as smooth as possible. Therefore, jitter is minimized.

Sometimes (eg, when an error condition exists) it is necessary to have a pulse width modulator (PWM) rapidly shut down one or more motors under the control of the PWM. Examples of the present invention relate to apparatus and methods for rapidly shutting down PWM-controlled devices while minimizing the potential for harm to people, motors, and machines due to the shutdown.

Within this disclosure, the term 'event indication signal' refers to a signal (eg, within a device or network) that indicates that a pulse width modulator (PWM) may be required to rapidly shut down one or more motors (eg, in a power stage cutoff) . In an example of the present invention, the one or more event indication signals (EIS) may come from various sources. One or more examples of this disclosure relate to systems and methods for managing EIS from such sources. At least one embodiment of the present invention pertains to a method of reducing unnecessary EIS generation by such sources.

EIS can be caused by operational errors in devices, circuits, components, and the like. EIS may also correspond to instantaneous fluctuations. Momentary fluctuations include signals caused by minor operational errors that do not actually necessitate a power stage shutdown. Transient fluctuations include transient signal errors that can be caused by non-error events such as electromagnetic interference caused by environmental factors. Momentary fluctuations correspond to 'false positive' detections of false events. At least one example of the present invention is a method of mitigating the effects of transient fluctuations. In one or more examples, if the filter determines that the EIS is not due to transient fluctuations, the filter will transmit a trip event indication signal (TEIS); in an ideal situation, all false positive EISs are filtered out and all positive (true positive) EIS is communicated to a trip signal transmitter (eg, logic circuit 421 shown in Figure 4B). It is worth noting that the EIS can have varying lengths, and in general, the longer the EIS lasts, the more likely it is that the EIS is indicative of a fault and not just transient fluctuations.

At least one example of the present invention is a method of combining multiple TEISs into a single TEIS.

Examples of the present invention include diagnostics for identifying the source of EIS, determining with greater accuracy when the event that produced a given EIS occurred (to within plus or minus three nanoseconds), and storing this source and timing information for consideration mechanism and method. Unlike conventional solutions, the mechanisms and methods provide the ability to read back EIS source information and timing information for multiple events. The ability to respond to an error immediately is a corollary of the accuracy of the error timing determination. For example, in an implementation of the present technology, a field effect transformer (FET) based power stage must be turned off within the wrong 1 microsecond to avoid damage to the FET based power stage. In some embodiments, damage prevention requires shutting down the FET-based power stage before no more than 500 nanoseconds of the error condition has elapsed. For error conditions to be handled quickly, the error conditions must be communicated quickly to the shutdown mechanism; the delay from detecting the error signal to tripping the PWM should be minimized.

Depending on the operating environment of a given ICSS, and taking into account propagation delays in the signal chain of one or more devices with which the ICSS interacts (and/or communicates and/or controls), the longest time between transmitting the EIS and issuing the trip signal An acceptable delay would be 10 nanoseconds. However, as noted above, the longer the EIS persists, the more likely it is that the EIS is indicative of a failure rather than just transient fluctuations. The reverse is also true; the shorter the EIS, the greater the probability that the EIS is caused by instantaneous fluctuations. Therefore, there is a trade-off between ensuring that errors are resolved immediately (e.g. by powering down components) and avoiding effects on false alarms (e.g. transient fluctuations caused by extraneous signal fluctuations).

In one or more examples of the invention, the ICSS user can adjust the response time to avoid contributing to false detections. In some instances, the user may change the settings of the transient fluctuation filter, such as by extending or shortening the EIS requiring the transient fluctuation filter to send the TEIS to the trip signal controller (eg, the logic illustrated in FIG. 4B ) circuit 421) length. Typical transient filter settings are from 10 ns to 100 ns. In at least one example, if the transient filter is not set to zero (0), the transient filter will remove all noise, but (as explained) will also increase the propagation delay. In some examples, the user may also adjust the sensitivity of the trip signal controller (e.g., logic circuit 421 illustrated in Figure 4B) itself. Here, the user can increase or decrease the time required for the trip signal controller to read one or more incoming TEIS (eg, from one or more error signal sources) before the trip signal controller will trip the PWM length.

At least one example within this disclosure is a system including a position feedback interface, a motor current and voltage interface, a pulse width modulator (PWM), a programmable real-time unit, and trip generation hardware configured To generate a trip signal based on a set of static and/or dynamic input events for each motor controlled by a given PWM. In one or more instances, the system can be dynamically configured. In at least one example, the system enables programmable selection of input events to the trip signal generation logic. An example of the present invention is a system configured to enable programming of event-based transient volatility mitigation.

At least one example of the present invention is a programmable state machine having an active state and a reset state. In some examples within the present invention, the reset state is used for a pulse width modulation cycle. In one or more examples, the reset state is controlled by a software reset and/or a timer. In an example of the present invention, the system includes a reset function that enables single-shot and/or cycle-by-cycle EIS analysis.

An example of the present invention is a configurable hardware state machine capable of managing pulse width modulation with minimal latency. An example of the present invention is a configurable hardware state machine capable of managing a power stage shutdown regardless of the source of the event requiring this power stage shutdown. In at least one example, all EIS inputs are ingested for EIS management by a single hardware device with the least latency and least jitter.

As used in the present invention, the term jitter refers to the deviation from the true periodicity of a roughly periodic signal (which is usually related to a reference clock signal).

In an example of the present invention, a communication protocol is a system of rules that allow two or more entities of a communication system to transmit information. Certain communication protocols such as EtherCAT (Ethernet for Control Automation Technology) can have multiple datagrams within a packet, which requires parsing the packet multiple times with variable start offsets. EtherCAT is an Ethernet-based fieldbus system. Fieldbus systems are industrial network systems for real-time distributed control. The EtherCAT protocol is standardized in IEC 61158 and is suitable for both hard and soft real-time computing requirements in automation technology. A real-time system like EtherCAT needs to have its packets parsed during the receive process and make processing/forwarding decisions during the receive process before the end of the packet has been reached - eg where to send the received packet.

As mentioned, many different communication protocols have been developed across different industries and market segments to address real-time communication for data exchange running on proprietary developed processing devices such as SoCs, DSPs, ASICs and FPGAs. Examples of the present invention are directed to providing and/or enabling multi-protocol flexibility for communications between such processing devices. At least one example of the present invention is directed to providing and/or enabling real-time Ethernet communications at speeds of 1 gigabit/second or faster.

At least one example of the present invention is an architecture for an Industrial Communication Subsystem (ICSS) that addresses the flexibility requirements of multiple protocols and the performance requirements of real-time Gigabit Ethernet. With integration into the directory processor, industrial communication is made as easy as standard Ethernet. ICSS has a hybrid architecture. In one example, the ICSS includes four 32-bit reduced instruction set computer (RISC) cores, called programmable real-time units (PRUs), coupled with a tightly integrated set of hardware accelerators. A reduced instruction set computer (RISC) is a computer whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).

The combination of 128/256 gigabit/second data transfer with a deterministic programming resolution of 4 nanoseconds (ns) is a highly distinguishable approach to communication interfaces. A detailed view of a hardware accelerator combined with a 128/512 Gigabit/sec data bus architecture is illustrated in Figures 2A-2C.

Examples of the present invention relate to a Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) that includes dual 32-bit RISC cores (PRUs), data and instruction memory, internal peripheral modules, and an interrupt controller ( INTC). The programmable nature of the PRU-ICSS, along with its access to pins, events, and all SoC resources, provides for fast real-time responses, specialized data handling operations, peripheral interface control, and other processing from a system-on-a-chip (SoC) Flexibility when the server core offloads tasks.

For industrial Ethernet use cases, ICSS may require a compromise between programmability (flexibility) and the need to maintain line rate packet load. In one example, the programmable unit (PRU) will run at a 250MHz clock and thus limit the firmware (f/w) budget to about 84 cycles per packet (for minimum sized transmit and receive frames). This may be insufficient for fully 802.1D compliant packet processing at 1 GHz rate. Thus, exemplary ICSSs of the present invention include hardware (HW) accelerators for time-consuming bridging tasks.

According to the disclosed example, the PRU microprocessor core has a load/store interface to external memory. Using data I/O instructions (load/store), data can be read from or written to external memory at the expense of stalling the core while the access is being made. Reads of N-32 bit words typically take about 3+N cycles, while writes take about 2+N cycles.

In at least one example, broadside RAM and/or broadside interfaces are optimized for 32-byte wide transfers. Lower transfer widths can be supported by padding the size to 32 bytes. In at least one example, the read location is first written to the attached RAM using the xout broadside instruction, and then the data is read using the xin broadside instruction. Therefore, the read operation will take two loops. For write transfers, the address is placed in the register just after the register holds 32 bytes of data, and the data plus address is transferred to the attached RAM with one xout instruction. In at least one example, this method has the additional advantage of being able to also perform operations on the data, possibly in parallel with the transfer.

In addition to speeding up writes and transfers, embodiments of the present invention also provide advantages such as glue logic between RAM and broadside interface that locally stores the last accessed RAM address, which allows an auto-increment mode of operation so firmware does not have to constantly Update addresses (especially useful for bulk reads). Embodiments of the present invention enable useful manipulation of data using this interface in parallel with write operations. For example, a cut through data may be run through a checksum circuit to compute a running checksum of a packet while the packet is stored in RAM. In at least one example, the processor may perform endian flipping on data within a packet at various data size boundaries. In at least one example, this interface can be used to perform a pivot/swap operation, for example, to swap registers r2-r5 with r6-r9. This is useful when moving data between interfaces with different block sizes (e.g., a 32-byte RX FIFO and a 16-byte PSI interface). In alternative examples, separate memory 'views' are achieved by using different broadside identifiers (IDs) (parameters to broadside instructions) to associate organizations with attached memory or through different firmware tasks. Broadside IDs can be mapped to different read or write memory addresses (maintained by glue logic) so that data structures such as FIFOs (first in, first out) and queues can be implemented in a flexible and firmware managed manner via attached RAM. At least one instance utilizes embedded processing.

In at least one example of the present invention, ingress filter hardware, in conjunction with ingress classifiers, enables hardware decisions for real-time forwarding and processing. This filter hardware is placed at the variable content-dependent start address, reloaded within the packet at the variable content-dependent start address, masked against the application address range and compared using greater and less than operations.

In an example of the present invention, multiple hardware filters can be combined with binary logic to form a complex receive decision matrix. In an example, multiple hardware filters may be combined with time windows to make time-aware reception decisions. Multiple hardware filters can also be combined with rate counters for rate-limited reception decisions.

In at least one example of the present invention, hardware filters and classifiers enable packet-related decisions to be received and forwarded with relatively small bridging delays. In an example, the combination of content, time window, and data rate provides robust ingress classification for Ethernet bridging while maintaining relatively small bridging delays. As will be explained in more detail below, examples of the present invention achieve bridging delays of less than 1 microsecond.

1 is a functional block diagram of an ICSS architecture-based system 100, which may be a component of SoC 130, according to one example of the present invention. In Figure 1, a 16 kilobyte broadside random access memory (BS-RAM) 101 is coupled to (in signal communication with) an AUX_PRU 112. BS-RAM 101 is coupled to PRU 116 via AUX_PRU 112 . BS-RAM 101 can transfer 32 data bytes in one clock cycle of system 100. BS-RAM 101 has ultra-high bandwidth and ultra-low latency. Within the present invention, coupled components (eg, circuits) are capable of communicating with each other. Connected components are components that are coupled via direct or indirect connections. Within the present invention, components that are coupled to each other are also connected unless an indication to the contrary is provided.

As illustrated in FIG. 1 , incoming data through interface circuit 104 , which is a real-time interface, is passed to FIFO receive circuit 105 . As the data passes through the receive circuit 105, a classifier 108 is applied to this incoming data. The combinational logic of filter 106, rate counter 107, and classification engine 108 is applied to the received packets.

Management data input/output (MDIO) circuit 102 is a media interface. MDIO circuit 102 uses PRU 116 to communicate with the external reduced gigabit media independent interface (RGMII) physical layer and media independent interface (MII) physical layer (interface circuit 104, interface circuit 119). MDIO circuit 102 has low latency and is dedicated to PRU 116 . As shown in FIG. 1, the system 100 also includes a statistics counter circuit 103 that tracks statistics of the Ethernet ports of the real-time interface circuit 104, such as packet size, errors, and the like. Real-time interface circuits 104 (including RGMII, Serial Gigabit Media Independent Interface (SGMII), and Real-Time Media Independent Interfaces 231 , 259 (RTMII)) are connected to input/output (IO) of system 100 (eg, MDIO circuit 102 ) hardware layer. The real-time interface circuit 104 is coupled to a FIFO receive circuit 105, which includes a level one first in first out (FIFO) receive layer (RX_L1) and a level two FIFO receive layer (RX_L2). The FIFO receiving circuit 105 can receive the level 1 FIFO data and the level 2 FIFO data.

As described, system 100 includes filter 106, which is a filter for eight filter type 1 data streams and/or sixteen filter type 3 data streams. Filter 106 determines whether a given packet is a particular "type" of packet. Filter type 3 packets have variable start addresses, depending on whether or not the virtual LAN is used to deliver the packet. The system 100 also includes a rate tracker 107 . In at least one example, system 100 includes eight rate trackers 107 . Based on the filter type hit rate, the rate tracker 107 calculates the throughput rate of the FIFO receive circuit 105 . The system 100 also includes a filter database (FDB) 109. FDB 109 is used for routing and redundancy. The receive circuit 105 includes a level one receive layer (RX_L1) and a level two receive layer (RX_L2), the receive layers include physical receive ports. The level one receive layer (RX_L1) and level two receive layer (RX_L2) of the receive circuit 105 can access the FDB 109 to manage receive and forwarding decisions based on IEEE 802.1Q learning bridge mode 1. FDB 109 contains a look-up table (LUT) that stores results that can be given to PRU 116 to help PRU 116 make data routing decisions. In at least one example, system 100 also includes virtual local area network tag (VLAN TAG) circuitry 110. Tags (a/k/a'ID') are keywords or terms assigned to pieces of information such as Internet bookmarks, digital images, database records, computer files or VLANs. Statistics tracker 103, filter 106, rate tracker 107, classifier 108, FDB 109 and (optionally) VLAN TAG 110 are aspects of receiving circuit 105.

The MDIO circuit 102 controls the interaction with the external physical layer (not shown) of the system according to the Open Systems Interconnection (OSI) model. The physical layer connects link layer devices such as media access controllers (MACs) (see 206 ( 266 ) and 220 ( 290 ) of FIG. 2A , and 266 and 290 of FIG. 2C ) to host (eg, 246 ) devices The physical medium of the system/system, the subsystem 200 is a component of the host device/system or the subsystem 200 is coupled to the host device/system. The physical layer includes both Physical Coding Sublayer (PCS) functionality and Physical Media Dependency (PMD) layer functionality. There are transceivers external to the SoC 130 in which the system 100 is embedded. MDIO circuit 102 configures one or more external physical layers (not shown) and minimizes ICSS latency.

Each central processing unit (CPU) (e.g., programmable real-time unit 116) includes a task manager circuit (e.g., task manager circuit 111). In at least one example, task manager circuit 111 and task manager circuit 121 may recognize 200 events or more. Events correspond to, for example, hardware status signals from filter 106, from rate tracker 107, or from interrupt controller 123. AUX_PRU 112 is responsible for control. For example, based on the start frame, the PRU-RTU 112 detects that a new packet is going to the data processor—PRU 116, and in parallel with the data processor gathering the data, the PRU-RTU 112 will set the address per packet and directly as needed Memory access (DMA) to get the packet to the host (130, 246). Although data is pushed to BS-RAM 117, data can also be pushed to checksum accelerators such as CRC 120. Therefore, CRC 120 can cause BS-RAM 117 to suspend. Transmission circuit 113 communicates with AUX_PRU 112 and PRU 116 . The transmit circuit 113 may receive (RX) and transmit (TX) information, as indicated by the symbol 'RX/TX' in FIG. 1 . Transfer circuit 113 is configured with a DMA that enables both AUX_PRU 112 and PRU 116 to access main system 100 memory. When AUX_PRU 112 or PRU 116 initiates a transaction, transfer circuit 113 will manage the movement of data to SoC 130 memory to pull or push data. The transfer circuit 113 is therefore a general asset that can be used for data transfer. In at least one example, in the architecture of FIG. 1, AUX_PRU 112 may control address locations while PRU 116 pushes data. Thus, the architecture is flexible because a single CPU (eg, 112, 116) is not responsible for both data management and control functions.

In at least one example subsystem 100, there is a structure with local memory. The structures in the example subsystem 100 of Figure 1 may be 4 bytes wide. However, there are two sets of data memory 114 dedicated to each CPU (e.g., 112, 116), and another set of larger memory 115 is shared across the CPUs (112, 116). Data memory 114 may be used with scratchpad 126 and scratchpad 127, while shared memory 115 is used for link lists, which are used for DMA or for storing metadata. Scratchpads 126, 127 are like BS-RAMs 101, 117. However, the scratchpad 126 and the scratchpad 127 are different from the BS-RAM 101 and the BS-RAM 117 in that the scratchpads 126 and 127 are shared among slices (see slice_0 of FIG. 2A and slice_1 of FIG. 2C ), and The memories 126, 127 are more flexible than the BS-RAMs 101, 117. Scratchpads (e.g., 126, 127) may save and/or restore register sets. Scratchpads 126, 127 may be used for slice-to-slice communication and to perform barrel shifting or remapping of register sets to physical locations. BS-RAM 117 is similar to BS-RAM 101 except that BS-RAM 117 also has an FDB containing a lookup table. When a packet enters the system 100 at the receive circuit 105 , the hardware performs a lookup of the FDB 109 and presents the data to the PRU 116 . Based on the response of the FDB of BS-RAM 117, PRU 116 makes routing decisions, such as whether to route the received packet to the host via transport circuit 113 and/or to a different port, eg, via transport circuit 118. PRU 116 also accesses BS-RAM 125. The PRU 116 acts as a switch, while the BS-RAM 117 enables simultaneous execution of actions. The BS-RAM 117 is thus a dual purpose component. Hardware may be connected to the BS-RAM 117 while the BS-RAM 117 is performing a lookup of the FDB 109 for the PRU 116 . Just as checksums may be performed by CRC 120 while RAM (eg, 114) is loaded, FDB operations may be performed by BS-RAM 117 against PRU 116 while BS-RAM 125 is interacting with hardware.

Transmission circuitry 118 handles data outgoing from PRU 116 . Transmission circuitry 118 performs preemption, tag insertion, and padding. Transport circuitry 118 enables firmware to cleanly terminate packets. Thereafter, the task manager circuit 121 will perform the necessary steps to generate the final CRC and if the packet in question is small, the transport circuit 118 will perform padding. Transport circuitry 118 may insert tags so that PRU 116 does not have to keep track of the packets. The transmission circuit 118 can thus assist the hardware of the SoC 130 . Transmission circuit 118 is coupled to interface circuit 119 . The interface circuit 119 is the final layer. Outside the transport circuit 118, there are different media independent interfaces, such as RGMII, SGMII and real-time MII (see 104, 119, 225(295)). Other types of interfaces on system 100 are also possible within the present invention. The FIFO transfer circuit 118 is agnostic with respect to such interfaces. The interface circuit 119 is a demultiplexer. Interface circuitry 119 provides protocol conversion to transport circuitry 118, enabling transport circuitry 118, and therefore PRU 116, to communicate with a given piece of hardware in a protocol appropriate to the hardware. The PRU 116 and the transmission unit 118 are thus not constrained to operate in a manner corresponding to only one protocol, thereby making the PRU 116 and the transmission circuit 118 more versatile than they would be if the interface circuit 119 were not present. In at least one example of the present invention, system 100 constrains the data flow of interface circuit 119 to connect to an external physical layer. Referring to the levels of the Open Systems Interconnection (OSI) model, the transport circuit 118 has a level one FIFO transport layer (TX_L1) and a level two FIFO transport layer (TX_L2). Level (or 'layer') one corresponds to the physical layer of the OSI model and level two corresponds to the data link layer of the OSI model. This dual layer connectivity offers several options. For example, the level two FIFO transport layer (TX_L2) can be bypassed and data can be sent to the level one FIFO transport layer (TX_L1), which reduces latency. In at least one example, the level two FIFO transport layer (TX_L2) has a wider interface than the level one FIFO transport layer (TX_L1). In at least one example, the level two FIFO transport layer (TX_L2) has a 32-byte interface, and the level one FIFO transport layer (TX_L1) has a 4-byte interface. In at least one example, if, at receive circuitry 105, the data packet goes from the tier-one receive layer (RX_L1) to the tier-two receive layer (RX_L2) 272 (257), and the PRU 116 resides at the tier-two receive layer (RX_L2) To fetch the packet, then the data will first be pushed to the level two FIFO transport layer (TX_L2) of the FIFO transport circuit 118, and then the hardware of the FIFO transport circuit 118 will push the data packet directly to the level one FIFO transport layer (TX_L1). However, when communicating with a very low latency interface such as EtherCAT, the level two FIFO transport layer (TX_L2) can be bypassed; the data output from the PRU 116 can be pushed directly to the level one FIFO transport layer (TX_L1), ( As mentioned, it has a width of 4 bytes).

Interface circuit 104 and interface circuit 119 are at level zero of the OSI model. Thus, data enters system 100 at level zero through interface circuit 104, moving from level zero to level one receive layer (RX_L1) of FIFO receive circuit 105 or level two receive layer (RX_L2) of FIFO receive circuit 105 272 (257) All the way up to PRU 116 (which exists at both level one and level two), and from level one or level two of PRU 116 through FIFO transfer circuit 118 and back at interface circuit 119 back to level zero. In at least one example, cyclic redundancy check (CRC) circuit 120 is an accelerator that assists PRU 116 in performing calculations. PRU 116 interfaces with CRC circuit 120 through BS-RAM 117 . CRC circuit 120 applies a hash function to the PRU 116 data. The CRC circuit 120 is used to check the integrity of the data packets. For example, all Ethernet packets contain CRC values. CRC circuit 120 performs a CRC check on the packet to see if the CRC value of the packet agrees with the result calculated by CRC circuit 120 . That is, the packet contains a CRC signature and after computing the signature, the result is compared to the signature attached to the packet to verify the integrity of the packet.

The system 100 also includes an interrupt controller (INTC) 123 . INTC 123 aggregates CPU (eg, AUX_PRU 112, PRU 116) level events into host (eg, 130, 146) events. For example, there may be ten host events. INTC 123 determines that a given set of subordinate-level events should be aggregated, mapped, and classified into a single entity. A single entity may be routed to and used by the PRU 116 or task manager circuit 121 to cause events for the host (130, 146). In that sense, INTC 123 is both an aggregator and a router.

Enhanced/External Capture (eCAP) circuit 124 is a timer that enables PRU 116 to generate an output response based on a time match with Industrial Ethernet Peripheral (IEP) circuit 122 and capture events of events external to system 100 time.

The IEP circuit 122 has two sets of independent timers that enable time synchronization, time stamping, and quality of service for data outgoing from the system 100. There are several independent capture circuits associated with the IEP circuit 122 . For example, if there is a receive (RX) start frame event and it is important to push the frame to the host at a particular time, IEP circuitry 122 may time stamp the event to indicate the particular time. If the event is a time-triggered transmission for the egress circuit 118, and if the packet is expected to be delivered at a precise time (within 2 nanoseconds to 3 nanoseconds), then independent of the PRU 116, the packet transmission begins when the timer expires transmission. Thus, the transmission of packets is effectively decoupled from the PRU 116 .

In addition to the described timer, the IEP circuit 122 also contains an enhanced digital input/output interface (EDIO). EDIO is similar to a general-purpose input/output (GPIO) interface, but is smarter and better calibrated for Ethernet communication. For example, transmitting a start frame or receiving a start frame can cause an event on EDIO, which in turn can cause an event external to SoC 130. Sync out and lock in as part of time synchronization. It is also possible for the IEP 120 to receive frames and capture analog voltages. In conventional systems, this would require a read operation. But for EDIO, the capture can be event-triggered and/or time-triggered, thus making the capture more precise than in conventional systems. EDIO enables the system 100 to determine precisely when an incoming frame arrives, which in turn enables the system 100 to sample one or more specific values (eg, temperature, voltage, etc.) and when sampling due to the time stamping of the IEP circuit 122 Track precisely. The frame in question can be augmented. When the frame is transmitted by transmit circuitry 118, the frame may contain time-stamped samples without adding overhead or latency. The IEP circuit 122 also includes a watchdog (WD) timer. Certain events should occur under normal operating conditions. When such an event occurs, the PRU 116 will normally clear the WD timer. If the WD timer fires, this means that the PRU 116 did not clear the WD timer in a timely manner, or did not reset the WD timer in a timely manner, indicating that there is an undesired timeout or some type of wait time. The WD timer is therefore used to track errors.

As described, task manager circuit 111 and task manager circuit 121 can recognize a large number of events. PRU 116 is the primary data engine of system 100 . The system 100 begins to prepare and serve the receive circuit 105 when the frame is started. Once the frame is in the transmission circuit 118, the input of the next packet can begin. Since PRU 116 is the main processor, PRU 116 needs to access all events in real time. Another operation associated with PRU 116 is watermarking. Watermarks may be formed at interface circuit 104 , receive circuit 105 , transmit circuit 118 , and interface circuit 119 . It is not expected to wait until the FIFO is full before loading or unloading a packet, as this will be too late, and it is not expected to wait until the FIFO is empty because it will be too early, when a certain amount of emptiness is reached ) (or full scale), the task manager circuit 121 may fire and the PRU 116 will determine whether to watermark the packet.

An aspect of the BS-RAM 117 is that it enables the PRU 116 to snoop on the packet while the system 100 can save the context and variables at the BS-RAM 117, and can interpret the context and variables without overhead cost. The operation is performed because there is no need to move the packet's data twice. In at least one example of the invention, incoming data packets can be moved to a storage location while operations are performed on the data. This is different from conventional systems where incoming packets are moved to a processing circuit and then to a storage location. System 100 thus performs a single operation, whereas a conventional system would perform two operations.

AUX_PRU 112 interacts with BS-RAM 101 as described. AUX_PRU 112 has task manager circuitry 111 that can preempt PRU 116 based on the occurrence of certain events or context switches. AUX_PRU 112 also interacts with transmit circuit 113 . In at least one example, the system 100 in accordance with the present invention also includes eight kilobytes of data RAM 114 and 64 kilobytes of shared RAM 115. Both AUX_PRU 112 and transmit circuit 113 interact with PRU 116. The task manager circuit 121 inputs real-time tasks for reception and transmission processing based on the FIFO watermark. PRU 116 is also coupled to a 16 Kbyte BS-RAM filter database 117. The output from PRU 116 goes to FIFO transfer circuit 118 . Then, the output from the FIFO transfer circuit 118 goes to the real-time interface circuit 119 . PRU 116 also interacts with CRC 120, which computes checksums within Ethernet packets. In at least one example, system 100 includes IEP/timer/EDIO/WD circuit 122. As described, the system 100 may also include an interrupt controller (INTC) 123 and an eCAP circuit 124 .

2A-2C illustrate an example Industrial Communication Subsystem (ICSS) (hereinafter referred to simply as subsystem 200). Figures 2A-2C illustrate many of the same components as shown in Figure 1, but in different details. The description set forth in relation to Figure 1 is closely related to Figures 2A-2C, and vice versa. The slice_0 201 on the left side of the internal bus 248 and the external bus 247 is symmetrical with the slice_1 261 on the right side. (Note that similar letter names indicate similar components.) Descriptions of components in slice_0 201 apply to their counterparts in slice_1 261. As illustrated in FIG. 2, subsystem 200 includes processing hardware elements including one or more hardware processors, such as auxiliary programmable real-time unit (AUX_PRU_0) 205 and PRU_0 219, where each hardware processor may have one or more processor cores. In at least one example, a processor (eg, AUX_PRU_0 205, PRU_0 219) may include at least one shared cache that stores one or more of the processors (AUX_PRU_0 205, PRU_0 219) Data utilized by other components (eg, computational instructions). For example, the shared cache may be locally cached data stored in memory for access by the components that make up the processing elements of the processor (AUX_PRU_0 205, PRU_0 219). In some cases, shared caches may include one or more mid-level caches, such as level 2 caches, level 3 caches, level 4 caches, or other levels of caches, last level caches buffer memory or a combination thereof. Examples of processors include, but are not limited to, CPU microprocessors. Although not explicitly illustrated in FIG. 2, the processing elements comprising processors AUX_PRU_0 205 and processors PRU_0 219 may also include one or more other types of hardware processing components, such as graphics processing units, ASICs, FPGAs, and/or DSPs . Another accelerator for PRU_1 is BSWAP circuit 224 (294). BSWAP circuit 224 ( 294 ) may swap words depending on the size, little endian, and/or big endian of the packet in question. BSWAP circuit 224 (294) may reorder the bytes in the packet depending on the word size.

Subsystem 200 includes slice_0 201 mirrored by slice_1 in Figure 2C. As can be seen in Figure 2A, slice_0201 has multiple components. The main components are auxiliary PRU (AUX_PRU_0) 205 , PRU_0 219 and MII 228 . AUX_PRU_0 205 has several accelerators (a/k/a widgets). AUX_PRU_0 205 is used as the control processor for slice_0 201. Throughout this disclosure, the terms 'control processor', 'AUX_PRU' and 'RTU_PRU' are synonymous and interchangeable unless otherwise indicated or dictated by the context in which they appear, although their function and configuration may vary.

2A illustrates that a memory (eg, 204 (264)) may be operatively and communicatively coupled to AUX_PRU_0 205. Memory 204 (264) may be a non-transitory medium configured to store various types of data. For example, memory 204 (264) may include one or more storage devices including volatile memory. Volatile memory, such as random access memory (RAM), can be any suitable non-persistent storage device. In a particular example, if the allocated RAM is not large enough to hold all working data, non-volatile storage (not shown) may be used to store overflow data. This non-volatile storage device may also be used to store programs loaded into RAM when such programs are selected for execution.

Software programs can be developed, coded and compiled in various computing languages for various software platforms and/or operating systems and then loaded and executed by AUX_PRU_0 205. In at least one example, a compilation process of a software program can transform program code written in a programming language into another computer language, enabling AUX_PRU_0 205 to execute the programming code. For example, a compilation process of a software program may produce an executable program that provides encoded instructions (e.g., machine code instructions) to cause AUX_PRU_0 205 to implement certain non-generic computing functions.

Following the compilation process, the encoded instructions may then be loaded from storage 220 ( 290 ), from memory 210 into AUX_PRU_0 205 , and/or embedded within AUX_PRU_0 205 as computer-executable instructions or process steps (eg, via cache memory) or on-board ROM). In at least one example, AUX_PRU_0 205 is configured to execute stored instructions or process steps to perform instructions or process steps to transform subsystem 200 into a non-generic and specially programmed machine or device. Stored data (e.g., data stored by storage device 220 (290)) may be accessed by AUX_PRU_0 205 during execution of computer-executable instructions or process steps to indicate one or more components within subsystem 200.

2B illustrates components and resources shared by slice_0 of FIG. 2A and slice_1 of FIG. 2C. Figure 2C includes the same hardware as Figure 2A. slice_0 201 and slice_1 261 are symmetrical with respect to FIG. 2B. The description within the present invention relating to Fig. 2A applies mutatis mutandis to Fig. 2C. Subsystem 200 includes Subsystem 200 also includes corresponding ports 276 at slice_0 201 and on slice_1 261 . There is a third port (see Figure 2B), host port 245, which connects subsystem 200 to host 246, which may be a component of said host. Both port 253 and port 276 can be connected to Ethernet. Subsystem 200 can thus function as a three-port switch. Host 246 may be a local source/sync or SoC (130). Although the subsystem 200 option itself may be the SoC (130), in some implementations the subsystem 200 will be a subcomponent of the larger SoC (130). In some instances, host 246 will be a CPU from ARM Holdings PLC of Cambridge, England, UK. In at least one instance, host 246 includes several CPUs. There are various types of CPUs. An example of a small CPU is the Arm Cortex-R5-CPU. An example of a large CPU is the Arm Cortex-A57-CPU. In at least one example, subsystem 200 may be controlled by another such CPU.

As shown, subsystem 200 includes XFR2TR circuitry 202 (FIG. 2A) that interacts with internal configurable bus array subsystem (CBASS) 248 (FIG. 2B). 'XFR' in XFR2TR circuit 202 (280) stands for transfer. The XFR2TR circuit 202 (280) has a broadside interface. XFR2TR circuit 202 (280) is adjoined to AUX_PRU_0 205 via the broadside interface of XFR2TR circuit 202 (280). The internal register set of AUX_PRU_0 205 is exposed to accelerator MAC 206, CRC 207 (267), SUM32 circuit 208 (268), byte swapping (BSWAP) circuit 203 (263), and BS-RAM 204 (264). In at least one example subsystem 200 of the present invention, the internal register set of AUX_PRU_0 205 is directly exposed to accelerators such as those mentioned above, unlike the architecture of conventional systems. In conventional systems, a load-store operation on the structure would be required for AUX_PRU_0 205 to access the accelerator. However, in the example shown in Figure 2, the accelerator is actually part of the data path of AUX_PRU_0 205. AUX_PRU_0 205 may import and export its register file to a given accelerator (a/k/a 'gadget') based on the broadside ID of the given register. For example, XFR2TR circuit 202 (280), which is part of DMA, may perform a transfer request. A transfer request (TR) may start with a starting address to move with starting data, specifying the amount of data to be moved (for example, 200 bytes). XFR2TR circuit 202 (280) may perform a simple DMA memory copy to SMEM 235 containing a list of predetermined transfer requests (TR). The software running on AUX_PRU_0 205 is aware of the list of preexisting TRs for SMEM 235 . In operation, AUX_PRU_0 205 sends instructions to the DMA engine to move data. Since transferring instructions can be extremely complex and/or complex, predefined instructions reside within a 'work order pool' stored in SMEM 235. Based on the type of packet in question, AUX_PRU_0 205 determines which 'work commands' should be used and in what sequence to cause the packet to be sent to the correct destination. XFR2TR circuit 202 (280) may create a work order list as directed by AUX_PRU_0 205, and once the work order list is created, XFR2TR circuit 202 (280) will notify a DMA engine (not shown). The DMA engine will then pull the specified work order from SMEM 235 and execute the pulled work order. Thus, XFR2TR 202 (280) minimizes the computational overhead and transfers necessary to construct a DMA list (like a link list) to perform data movement. TR stands for transfer request.

Another accelerator for AUX_PRU_0 is the BSWAP circuit 203 (263). BSWAP circuit 203 (263) may swap words depending on the size of the packet in question, little endian and/or big endian. The BSWAP circuit 203 (263) may reorder the bytes in the packet depending on the word size. BSWAP circuit 203 (263) is thus an accelerator that will automatically perform such swaps. BS-RAM 204 ( 264 ) corresponds to BS-RAM 101 discussed with respect to FIG. 1 . BS-RAM 204 ( 264 ) is tightly coupled to AUX_PRU_0 205 . When AUX_PRU_0 205 pushes a data element to BS-RAM 204 (264), the CRC for that element may be computed simultaneously by CRC 207 (267) or the checksum for that data element may be computed simultaneously by checksum circuit 208. Based on the ID of the packet, AUX_PRU_0 205 will simultaneously snoop for necessary transactions (eg, checksum, multiply, accumulate, etc.), which means that pushing data elements to BS-RAM 204 (264) and performing acceleration constitute a single transaction while Non-Dual Transaction. This operational simultaneity is achieved by BS-RAM 204 ( 264 ) because BS-RAM 204 ( 264 ) can be used while data is being transferred to physical RAM (eg, data RAM 114 and shared RAM shown in FIG. 1 ) 115) while enabling and/or disabling the functionality of the widget.

Although peripherals BSWAP 203 ( 263 ), XFR2TR circuit 202 ( 280 ), MAC 206 ( 266 ), CRC 207 ( 267 ), and SUM32 208 are illustrated as being external to BS-RAM 204 ( 264 ) for purposes of explanation, all The peripherals will be embedded within BS-RAM 204 (264) under most operating conditions. Multiplier-Accumulator (MAC) 206 (266) is a simple accelerator that includes a 32-bit by 32-bit multiplier and a 64-bit accumulator. Cyclic Redundancy Check (CRC) circuit 207 (267) performs redundancy checks cyclically. CRC circuit 207 (267) supports different polynomials. Checksum circuit 208 is like CRC circuit 207 (267), except that checksum circuit 208 uses a hash operation to determine the integrity of the payload at AUX_PRU_0 205 before performing a checksum on the payload.

Task manager circuit 209 is a critical part of AUX_PRU_0 205 . The task manager circuit may prompt AUX_PRU_0 205 to perform a given function based on which of the 196 events is detected.

There are two ways that data can be moved into and out of subsystem 200 and to SoC 130 memory and from the SoC memory and/or to external devices. One way is through the Packet Streaming Interface (PSI) 211 (281), which provides the ability to push data to and pull data from the host (e.g., 246). This action of PSI 211 (281) is different from a read request. Instead, the main (writer) component of PSI 211 (281) is attached to AUX_PRU_0 205. There is a mapping of received packets to destinations. Under normal operating conditions, the destination will be ready to receive the packet. For this reason, the PSI 211 (281) does not read the data, but transmits the data to the destination endpoint. PSI 211 (281) receives data from Navigation Subsystem (NAVSS) 210 and sends data to the NAVSS. NAVSS 210 enables complex data movement. NAVSS 210 has a DMA engine and an advanced TR called a reengine. NAVSS 210 supports PSI 211 (281) and can map PSI 211 (281) to other devices (e.g., via Peripheral Component Interconnect Express). Using PSI 211(281), data can go directly from the ICSS to the peripheral component interconnect at high speed while bypassing the host and/or the main DMA engine, thereby enabling data to pass from an Ethernet interface (eg, interface circuit 225(295) ) to another interface, such as Universal Serial Bus or Peripheral Component Interconnect High Speed.

AUX_PRU_0 205 communicates with Inter-Processor Communication Pad (IPC SPAD) 212 ( 282 ), which in turn communicates with PRU_0 219 . IPC SPAD 212 (282) is not a temporary SPAD owned by a single CPU. For at least the purpose, IPC SPAD 212 (282) is capable of transferring data or full controller state across AUX_PRU_0 205 and PRU_0 219. The transfer to virtual bus circuit (XFR2VBUS) circuit 213 (or simply 'transfer circuit 213') corresponds to and operates in the same manner as transfer circuit 113 shown in Figure 1 . The transfer circuit 213 (283) is attached to the BS-RAM 214 (284). Transfer circuit 213 (283) has broadside interfaces to external CBASS 247, internal CBASS 248, and spinlock circuit 249. Transfer circuitry 213 may request reads and writes from memory (eg, 204, 214) to broadside and from broadside to memory. This read/write function differs from read/write operations at, for example, dedicated memory (DMEM0) 233 . Conventional DMA copy operations move information in SoC (130) memory to DMEM0 233 or shared memory SMEM 235. Internal CBASS 248 is the network-on-chip of subsystem 200 .

Internal CBASS 248 is 4 bytes wide. In at least one example, to access the internal CBASS 248, load and store operations must be performed, which are high latency low throughput operations. However, using a tightly coupled and more direct transfer circuit 213 (283) reduces latency and overhead, while also providing greater bandwidth due to the broadside of the transfer circuit 213 (283). Thus, transfer circuit 213 (283) may act as a direct mapping from the register file to subsystem 200 memory (eg, 233). The intermediate memory locations are bypassed and the transfer circuit 213 (283) goes directly to the register file, which reduces latency.

As mentioned, like AUX_PRU_0 205, PRU_0 219 also has accelerators. PRU_0 219 corresponds to PRU 116 of FIG. 1 . Like PRU 116, PRU_0 219 has a task manager circuit 223. The main difference between AUX_PRU_0 205 and PRU_0 219 is that PRU_0 219 and interface circuit 104, receive circuit 105, transmit circuit 118, and interface circuit 119 (see FIG. 1) (which are collectively shown in FIGS. 2A-2C as interface circuit 225 (295) )) interaction. Interface circuit 225 (295) includes receive circuit 270, which includes a level one FIFO transport layer (TX_L1) 226 (296) and a level two transport layer (TX_L2) 262 (256) (see Figure 1, 118). The transmission circuit 271 includes a level one receive layer (RX_L1) and a level two receive layer (RX_L2) 272 (257) (see 105, Fig. 1).

The BS-RAM 214 (284) of the PRU_0 219 of the AUX_PRU 205 is the same as the BS-RAM 204 (264). General purpose input/output (GPIO) circuitry 215 (285) enables subsystem 200 to access additional hardwired SoCs (eg, 130, 246). Sigma-delta circuit 216 (286) is an analog-to-digital converter that interacts with one or more external sensors (not shown). A sigma-delta circuit 216 (286) converts the analog data stream from the sensor to a digital data stream. Sigma-delta circuit 216 (286) is a filter. The data stream from the sensor corresponds to the voltage or temperature at an external device such as a motor. The sigma-delta circuit 216 ( 286 ) informs the PRU_0 219 of certain events (eg, if there is a current spike, voltage spike, or temperature spike). PRU_0 219 determines what action (if any) needs to be taken due to the spike.

The peripheral interface 217 (287) is used to detect the position or orientation of the device under the control of the subsystem 200 (e.g., motors or robotic joints). For example, the peripheral interface 217 (287) uses a protocol to determine the precise radial position of the arm. The sigma-delta circuit 216 ( 286 ) and the peripheral interface 217 ( 287 ) are thus used for device control, such as robot control. Sigma-delta circuitry 216 (286) and peripheral interface 217 (287) are tightly coupled to PRU_0 219, which enables subsystem 200 to be useful in industrial contexts.

The packet streaming interface PSI 218 (288) of 219 is like PSI 211 (281) of 205 PSI. 211 ( 281 ) and PSI 218 ( 288 ) interact with Navigation Subsystem (NAVSS) PSI 210 . However, while PSI 211 (281) has four receive (RX) inputs and one transmit (TX) output, PSI 218 (288) has a single transmit (TX) output. As described, PRU_0 219 may move the register file of PRU_0 219 directly to Ethernet wire (port) 253 . Thus, data packets enter through the level one receive layer (RX_L1) 227 of the receive circuit 271 and the level two receive layer (RX_L2) 272 of the receive circuit 271 (RX_L2) 272 (257); no memory read or DMA is required. Alternatively, packets can be popped (pushed) to PRU_0219 immediately in a single data loop. If desired, the packet may be pushed to the tier one transport layer (TX_L1) 226 (296) or the tier two transport layer (TX_L2) 262 (256) in the next clock cycle, which may be referred to as a 'bridge- to-layer-cut-through)' operation. In at least one example, cross-layer bridging operations are faster than store-and-forward operations. The cross-layer bridging operation may be performed while the packet is being pushed to host 246 (eg, SoC 130) or slice_1 261 (as appropriate) via PRU_0 219 and port 245.

PRU_0 219 is a RISC CPU whose register file can access the Ethernet buffer without requiring access or through other memory. Interface 228 (298), interface 229 (299), and interface 230 (258) are physical media interfaces and include at least one RGMII. Real-time media independent interface 228 (298) is a 4-bit interface. Interface 229 (299) is gigabit wide. Interface 229 (299) is a Reduced Gigabit Media Interface (RGMII). Interface 230 (258) is a Serial Gigabit Media Independent Interface (SGMII). In one or more instances, these identified interfaces execute in real-time.

Ethernet interface circuit 225 (295) includes receive (RX) classifier circuit 232 (108) that employs rate data (107) and filter data (106) and other data, and is based on a predefined mapping function (eg, a time function), Classifier circuit 232 (108) classifies packets according to this mapping function. The classification of a packet will determine the priority of the packet, which will specify which queue (high priority queue, low priority queue, etc.) the packet is placed in. Port 253 of 225(295) is essentially a wire dedicated to Ethernet interface circuit 225(295). Port 253 is at level zero of the OSI model. Interface 252 (255) is the interface between PRU_0 219 and Ethernet interface circuit 225 (295). As mentioned, 270 (273) and 271 (274) are FIFO configured circuits. The FIFO transmission circuit 270 ( 273 ) corresponds to the transmission circuit 118 of FIG. 1 , and the FIFO reception circuit 271 ( 274 ) corresponds to the circuit 105 of FIG. 1 . While the data is being pushed into the FIFO circuit 270 (273), the classifier circuit 232 operates on the data.

Slice_0 201 shares several resources 301 with slice_1 261, such as illustrated in Figure 2B. Slice_0 201 and slice_1 261 are coupled to each other via internal CBASS 248 . Internal CBASS 248 is coupled to interrupt controller 236 . The interrupt controller 236 is an aggregator that aggregates several event instances (recall that there are 196 possible events). Some of the events may come from the host (130) 246, but most events are internal to the subsystem 200. Because of the large number of possible events, events must be aggregated or merged into a smaller number of superpackages for sharing with large amounts of data from hosts (e.g., 246). Software running on PRU_0 219 determines the mapping of sources to output destinations.

As described, subsystem 200 includes an internal configurable bus array subsystem (CBASS) 248 as a shared resource. Internal CBASS 248 receives data from external CBASS 247 via a 32-bit slave port. Internal CBASS 248 communicates with private memory_0 233, private memory_1 234 and shared memory (SMEM) 235 (115). SMEM 235 is general purpose memory. SMEM 235 may be used for direct memory access (DMA) operations for the DMA instruction set, among other functions. DMAs are like registers (126, 127) and may contain control and status information. The internal CBASS 248 also communicates with an enhanced capture module (eCAP) 237, which also communicates with an external configurable bus array subsystem (CBASS) 247. The enhanced capture module 237 is a timer for time management of external devices such as motors.

In at least one instance, subsystem 200 has different modes of operation. AUX_PRU_0 205 and PRU_0 219 each have memory mapped registers. Host 246 writes the information to configuration manager circuit 238 . For example, if host 246 needs to enable RGMII mode, configuration manager 238 will enable RGMII 229 (299), which is an instance of a configuration register.

The Universal Asynchronous Receiver-Transmitter (UART) 239 is a hardware device for asynchronous serial communication in which the data format and transmission speed are configurable. Electrical signaling levels and methods are handled by driver circuits external to UART 239. The UART must operate at a specific bod-rate, which requires a fixed clock rate. Asynchronous bridge (AVBUSP2P) 240 communicates with internal CBASS 248 and UART 239. The UART 239 in turn communicates with the external CBASS 247. AVBUSP2P 240 is a bridge that allows independent timing of UART 239 . External CBASS 247 is coupled to Industrial Ethernet Peripheral_0 (IEP0) 241A and Industrial Ethernet Peripheral_1 (IEP1) 241B. IEP0 241 and IEP1 273 each include a timer, EDIO and WD(122). IEP0 241A and IEP1 241B collectively enable two time domain managers to run simultaneously. Similar AP 237 timer searches for timers for IEP0 and IIP2 must operate on a given frequency (eg, 200 MHz), but the PRU can be decoupled from these. Likewise, AVBUSP2P 240, AVBUSP2P 242, and AVBUSP2P 243 are couplers that allow UART 239, IEP0 241A, and IEP1 241B to operate at different frequencies, if desired.

As shown in FIG. 2B , there is a second AVBUSP2P circuit 242 communicatively interposed between the IEP0 241A and the Internal Configurable Bus Array Subsystem (CBASS) 248. There is also a third AVBUSP2P 243 communicatively interposed between the IEP1 241B and the internal CBASS 248. Subsystem 200 also includes a pulse width modulator (PWM) 244 communicatively interposed between internal CBASS 248 and external components.

Components 236, 237, 238, 239, 241A, 241B, and 244 are each connected to a particular SoC line. That is, they each communicate with the IO of the host 246 .

FIG. 2B also shows that subsystem 200 may include spinlock 249 , AUX_SPAD 275 , and PRU_SPAD 250 . Spinlock 249 is a hardware mechanism that provides synchronization between the various cores (eg, 205, 219) of subsystem 200 and host 246. Conventionally, a spinlock is a lock that causes a thread attempting to acquire it atomically to simply wait in a loop ("spin") while repeatedly checking whether the lock is available. Using this lock is a busy-green wait since the thread remains active but not performing useful tasks. Once acquired, a spinlock will typically be held until it is explicitly released, but in some embodiments, if the waiting thread (the thread holding the lock) blocks or "goes to sleep", it can be automatically Release the spinlock. Locks are synchronization mechanisms used to enforce restricted access to resources in environments where many threads of execution exist. Locks enforce a mutually exclusive concurrency control strategy. Based on this principle, spinlock 249 provides automation of the operation of the components of subsystem 200. For example, spinlock 249 enables each of the cores of the subsystem (e.g., AUX_PRU_0 205) to access shared data structures (e.g., data structures stored in SMEM 235), which ensures that the various cores are updated simultaneously. Access to the various cores is serialized through spinlocks 249 .

As shown in example subsystem 200, auxiliary scratchpad (PRU SPAD) 250 and AUX SPAD 275 each hold three sets of thirty 32-bit registers. Subsystem 200 also includes a filter database (FDB) 251 (109) (which includes two 8-kilobyte groups) and filter database control circuitry. FDB 251 is broadside RAM accessed by AUX_PRU_0 205 and PRU_0 219. FDB 251 is also accessible by hardware engine sigma-delta 216 (286) and peripheral interface 217 (287). FDB 251 is also accessible by receive circuitry 271, which includes a level one receive layer (RX_L1) 227 (297) and a level two receive layer (RX_L2) 272 (257). FDB 251 is broadside RAM relative to AUX_PRU_0 205 and PRU_0 219 to read and write entries, but hardware also uses FDB 251 to provide an accelerated compressed view of packets arriving through port 253. The hardware will consult the memory of FDB 251 using a hashing mechanism and deliver the result to PRU_0 219 along with the packet. Determining where the packet will go next is the routing function. AUX_PRU_0 205 and PRU_0 219 access FDB 251 via the broadside interface of FDB 251 to add and delete information. FDB 251 may also be accessed by receiving hardware 225 (295).

Subsystem 200 may also include a communication interface 225 (295) that may be communicatively coupled to processor 205, such as network communication circuitry that may include wired communication components and/or wireless communication components. Network communication circuitry 225 may utilize any of a variety of proprietary or standardized network protocols (eg, Ethernet, TCP/IP, to name a few of the many protocols) to enable communication between devices. The network communication circuitry may also include one or more transceivers utilizing Ethernet, powerline Wi-Fi, cellular, and/or other communication methods.

As mentioned, in an example of the present invention, data packets are processed in a real-time deterministic manner, as opposed to conventional Ethernet or IEEE Ethernet processing, which defines more of a 'best effort' (bestefforts)' business systems where packet loss occurs depending on the load on a given network. While conventional Ethernet management is acceptable for many applications (eg, video streaming), in industrial environments (eg, robotic assembly lines), sent data packets are delivered accurately and according to a predetermined schedule (at under ideal conditions). In industry, packets must arrive according to a strict schedule. Of course, packet loss can occur in an industrial environment, but there are different methods to take care of packet loss at various layers (above the tier 0, tier 1 and tier 2 to which the examples of the present invention are concerned).

When a packet is received from the physical layer (not shown) at the layer one receive layer (RX_L1) 227 and/or the layer two receive layer (RX_L2) 272 (257), the packet classifier 232 (108) analyzes the packet and identifies all Which part of the packet is the content (a/k/a 'payload'). A packet classifier (a/k/a 'packet classification engine') 232 then makes an immediate decision about what to do with the packet. Ethernet bridge 225 (295) makes forwarding and receiving decisions regarding each packet received (via receive circuit 271 and/or ingress 253). In conventional IEEE Ethernet bridges, such forwarding and receiving operations are performed in a 'store and forward fashion', where incoming data packets are received in a first step, and once the data packets have been received, then in a second step review content. In conventional IEEE Ethernet bridges, once the packet is fully received and the content reviewed, a third step forward and receive determination is made. After forwarding and receiving determinations are made, the data packets are then provided to the mechanical transport layer (e.g., via transport element 226 (296)). In at least one example of the present invention, these steps are simplified in a manner that minimizes latency and jitter. In at least one example, classification engine 232 ( 260 ) is configured to execute the procedures of a conventional IEEE Ethernet bridge in an overlapping manner, whereby classification engine 232 ( 260 ) has received the packet in its entirety at 271 ( 272 ). Determining what needs to be done about the packet, where the packet needs to be sent, and through what routing.

In an example of the present invention, the bridging delay is the amount of time between when a packet arrives at port 253 and leaves on another port 276. During the time between the incoming of the data packet and the outgoing of the data packet, as described, the subsystem 200 makes a switching decision (determination) and then performs the transmission function. In the standard Ethernet IEEE community, a store-and-forward architecture is used to perform the handover function, which necessarily has variable latency. Under variable latency conditions, there is no guarantee that when a packet is received at time zero on incoming port 253 (104, 105), the packet will be fixed on a different port (eg, 276, 245) leave at a (known a priori) time. At least one benefit of the subsystem 200 is that the classification engine 232 makes it known that if a packet is received at time zero, the packet will be sent out through another port (eg, 245) within a predetermined (deterministic) period . In at least one example, this period is 1 microsecond. In at least one instance, when a component (e.g., slice_0 201) has this short switching time, the component is considered a real-time component, capable of performing its assigned function 'in real-time'. In an example of the present invention, real-time computing (RTC) describes hardware and software systems that are subject to "real-time constraints" (eg, from events to system responses). For example, a real-time program must guarantee a response within a specified time constraint (a/k/a 'deadline'). In some examples within the present invention, the real-time response is on the order of milliseconds. In some examples within the present invention, the real-time response is on the order of microseconds.

Examples of the present invention relate to communication bridges operating in real-time systems. A communication bridge is a real-time control system in which input data and output data are exchanged in a deterministic manner. Examples of this disclosure include control devices (eg, 217 ( 287 ), 244 ) and multiple slave devices (not shown) or devices (not shown) that consume input/output data from control devices 217 ( 287 ), 244 in real-time . The real-time systems 100, 200 have a communication bridge 255 real-time capability. Therefore, the amount of time to forward packets is deterministic, with minimal jitter and latency. In at least one example, jitter and latency are minimized (to the range of a few nanoseconds) by a hardware timer (not shown) that defines the time when a packet leaves physical ports 253, 252 (255). The real-time operability of subsystem 200 differs from standard Ethernet where jitters of at least tens of microseconds are common. In such conventional systems, the amount of time it takes to make forwarding/routing determinations varies depending on when packets arrive, the rate at which data packets are received, and the contents of the packets. In the real-time system (eg, 200) of the present invention, there is a cyclic execution of the switching function. For example, new data may be exchanged in subsystem 200 every 31 microseconds. A predetermined exchange rate (eg, 31 microseconds) is used as a time reference. Depending on when a packet comes in (eg, via port 253), forward the packet with a deterministic latency (31 microseconds in this example), or alternatively handle the packet according to a store-and-forward approach, as above The text is described for conventional systems. Thus, the packet arrival time can be a discriminator of how a given data packet will be processed by subsystem 200. Another factor considered by the receive (RX) classifier 232 in determining what to do with incoming packets is the data (transmission) rate typically associated with the type of packet in question. For example, if the average data rate of received packets exceeds a certain data rate threshold, the system may drop (less important) packets to help ensure sufficient bandwidth exists for higher priority packets. In at least one example, classifier 232 determines the importance of a given packet based at least in part on the payload of the packet.

In at least one example, classifier 232 examines packet content by first accessing a location in the packet, such as the packet's Ethernet Media Access Control (MAC) address. A device's MAC address is a unique identifier assigned to a network interface controller (NIC) for communication at the data link layer of a network segment. MAC addresses are used as network addresses for most IEEE 802 network technologies, including Ethernet, Wi-Fi, and Bluetooth. In at least one example, the MAC address is used in the medium access control protocol sublayer of subsystem 200. In accordance with the present invention, a MAC address is recognizable as six groups of two hexadecimal digits separated by hyphens, colons, or using other symbology.

The packets may be filtered by filter 106 based on their designated delivery addresses (not shown). The packet contains six-byte source and destination addresses. In at least one example, interface circuitry 225 (295) filters (106) the packets based on the information. For example, interface circuitry 225 (295) may read the network address of the packet and determine whether to accept the packet, forward the packet, or discard the packet. In at least one example, the accept-forward-drop decision can be based on the MAC header of the packet. In at least one example, upon making the accept-forward-discard determination, the interface circuit can go further into the packet, into the payload, and filter 106 the determination based on the name in the payload. In some implementations of SoC 200, the device name is concatenated in the payload, and then content filter 106 looks at the payload.

In embodiments of the present invention, a data packet will typically contain multiple datagrams. This datagram multiplicity requires delivery of the packet or part of it to multiple addresses. In other words, there can be multiple sub-packets in an Ethernet packet. Since subpackets can each have their own address, the address must be parsed. In situations where there are multiple addresses in a packet, subsystem 200 will restart parsing each time a subaddress is detected. Therefore, interface circuit 225 (295) will have a variable starting offset for filter 106 to enable interface circuit 225 (295) to place multiple sub-packets into a single Ethernet packet. In at least one instance, this means that sub-packets derived from a single data packet are sent to different devices (eg, via peripheral interface 217 (287)); in an example of the invention, a single Ethernet packet may contain sub-packets, One or more of the subpackages are intended for (addressed to) different devices. Unless otherwise indicated, the communications (packet switching) of the present invention are not point-to-point communications. The communication of the present invention is based on a master-to-slave architecture. In embodiments of the present invention, a single master device (e.g., master 246) controls tens, hundreds, or even thousands of slave devices.

Due to this asymmetric relationship between the master and slave devices (1 to N, where N can be a very large number) and the requirement for the communication to occur in real time, an interface circuit 225 that includes the ingress filter hardware 106 is provided (295) . Ingress filter 106 (and its accompanying logic), in conjunction with ingress classifier 232, enables hardware decisions for real-time forwarding and processing. In an example of the present invention, all information that must be read in order for the forwarding and receiving determination regarding a packet to occur is located in the first 32 bytes in the packet. Once the first 32 bytes of the packet are read, PRU_0 219 can look for headers and additional headers depending on the protocol the packet conforms to. The headers can be looked up in real-time (eg, in the filter database 251). Thus, once interface circuit 225 (295) has received the first 32 bytes of the packet, interface circuit 225 (295) has sufficient information to determine whether to forward the packet or whether to receive the packet, as described above describe. It should be noted that the depicted 32-byte header size is an example header size. The systems 100, 200 of the present invention may be configured to work with packets having other header sizes.

As described, the (packet) reception process is done in real time. In an implementation of the invention, AUX_PRU_0 205, PRU_0 219, and interface circuit 225 (295) are programmable and configured such that all packet processing is fully deterministic. Reception of 32 bytes of header information is done in interface circuit 225 (295) at 64 gigabits per second, which enables interface circuit 225 (295) to send 32 bytes of information forward or receive 32 bytes of information. The filter 106 of the present invention is very flexible, as long as the filter can be moved to filter specific parts of the packet. If there are multiple subpackets, filter 106 may be reloaded via interface circuit 225 (295) as needed. Additionally, interface circuitry 225 (295) may apply masks to set packet ranges or addresses within packets and/or sub-packets. By grouping packets using greater than and less than operations, interface circuitry 225 (295) can, for example, determine that packets will be received when they have address numbers from 15 to 29. In some examples, a binary mask may be applied such that subpackets with addresses starting with even numbers (eg, 8-7) are forwarded and subpackets with addresses starting with odd numbers are not forwarded (at least not immediately). Therefore, it may be advantageous to have greater/less than operation for sub-packet address classification. In some examples, different filters (e.g., 106 and 107) may be operatively combined with other components (e.g., MAC 206(266), 220(290)) to further process packets by their MAC addresses.

As described, multiple filters may be combined to cause interface circuit 225 (295) to make switching determinations. Additional logic may also be applied. For example, classifier 232 may classify the packet and apply classification-dependent logic, such as 'for packet type A, if conditions one, two, and three are true, the packet will be received'. As another example, where a packet is classified as type B, if condition one is true and condition two is false, then the packet will be discarded. Subsystem 200 may be configured such that conditions may also include a time window in which packets are received. For example, interface circuit 225 (295) may determine that at a certain point in time, interface circuit 225 (295) will only allow very important (higher priority) input/output data to be forwarded. Interface circuitry 225 (295) may be configured such that during specified periods (eg, after a predetermined event has occurred), a set of filter combinations will be applied, while during other times, all types of data traffic may be allowed. This described programmability is advantageous in an industrial environment because industrial communications operate based on hard time windows (as opposed to teleconferencing, for example).

In an example of the present invention, multiple hardware filters may be combined with rate filter 107 so that packets may also be classified according to rate. The filter 106, 107 and hardware 220 (290) operations used may be performed incrementally. Packets can be filtered using any combination of content, time and rate (all in real time). A given filter 106 may be restarted multiple times for a packet. Filter 106 may have a starting address whose value is determined based at least in part on the content and/or content type of a given packet/sub-packet.

In at least one example of the present invention, interface circuitry 225 (295) is configured to automatically detect whether a packet contains a virtual local area network (VLAN) tag. Some Ethernet packets have labels for the label bytes in the middle of the packet or at the trailing MAC address. It can happen that if a filter is applied to the data trailing the MAC address, the MAC address will be undesirably shifted by four bytes. The exemplary interface circuit 225 (295) of the present invention solves this problem by: automatically detecting whether a packet has a VLAN tag, and if the packet does contain a VLAN tag, restarting using the location of the VLAN tag as the starting address Start correlation filter 106. Thereafter, interface circuit 225 (295) makes a determination (e.g., whether to receive or discard the packet) using combinatorial logic, which may involve any suitable combination of AND, OR, and filter flags. In one or more examples of the invention, the rate counter 107, which may be a hardware rate counter, determines the rate depending on the type of traffic in question and a predetermined time window for the type of packet. Thus, there may be specific times for high priority packets and different times for non-real-time packets, and different filters may be applied depending on the situation. In some instances, filters 106 that produce immediate results during receive time (instant) processing will forward the packet in question regardless of the length of the packet. This operational capability is in stark contrast to conventional Ethernet, where packets are first received, one or more lookup tables are consulted, and then handover decisions are finally made. In some examples of the invention, the packet size is predetermined and communications occur at a fixed rate per packet. In other instances, information about the packet length is contained within the packet's header. In either case, the packet length is determined on-the-fly in hard real-time.

At least one technical benefit of the architecture described in this invention is that the architecture enables handover/forwarding determinations to be completed in a single microsecond, even for packets having a length of up to twelve microseconds. The time and data rate based combinatorial logic of interface circuit 225 (295) enables classification engine 232 to perform in a robust manner. The ability of subsystem 200 to restart filter 106 to apply filter 106 multiple times in a packet enhances the ability of subsystem 200 to make packet switching decisions in real time. In an exemplary embodiment, the length of the filter 106 is limited. If the packet is longer than the filter, then the filter 106 will need to be reloaded. If the Ethernet contains subpackets, the filter 106 can be reused for multiple locations with a single packet. In some instances, the subpackets will each have their own address. For example, if three subpackets are included, the address filter 106 may be loaded three times to apply the same address filter 106 to each subpacket. PRU_0 219 writes data to TX_L2 via interface 252 (255), and the data then leaves slice_0 201 along communication path 253. The described real-time processing supports the resource availability and allocation management described below.

As noted, aspects of the present invention and components of ICSS 200 relate to motor control. Motor control signals can be communicated using application site communications. In an industrial environment, devices and components may communicate input/output data between each other according to one or more Ethernet protocols. In the case of motor drive and motor control, there is always the application side of this input/output data. The motor may be driven by a plurality of pulse width modulated signals. Pulse width modulation is used to control motor applications in the context of robotics, machine tools, and conveyor belts. Proper pulse width modulation of mechanical devices like these is an important factor in maintaining safe operation in places such as factories and work sites. One aspect of safety is device error mitigation. Another aspect of safety is the minimization of device errors. One way to mitigate and minimize installation errors is to understand the causes and effects of past errors. One or more examples of the present disclosure are directed to identifying and tracking the sources of errors (sometimes referred to as 'transient fluctuations') and tracking when transient fluctuations occur. Examples of the invention include systems and methods for safely controlling a pulse width modulated driven device, such as a motor, in the presence of transient fluctuations, thereby mitigating any damage that may be caused by such transient fluctuations.

As described, a pulse width modulator (eg, PWM 244 in Figure 2B) controls the motor. In an example of the present invention, PWM drives the motor at a specific speed and a specific torque by controlling the motor using a pulse width modulated signal. In industrial applications, there are typically six pulse width modulated signals used to drive a three-phase electrical machine (eg, a three-phase motor). Additionally, there is a signal called a trip signal that is sent to the PWM to cause the PWM to shut down the motor power stage. As previously explained, the pulse width modulated signal is converted to a high power signal to drive a high power motor. The trip signal can go from the control unit to the power unit, eg PWM.

One way to enhance safety in environments involving industrial applications such as robotics, server drives, computer numerical controls (CNC) is to be able to quickly (and safely) shut down the power stage of such applications. Examples of power stages within the present invention are metal oxide field effect transformers (MOSFETs), insulated gate bipolar transistors (IGBTs) and other electronic devices that drive motors.

A duty cycle or power cycle is the portion of a period (T) in which a signal or system is active. The period is the time it takes for the signal to complete an on-off cycle. Duty cycle (D) is the ratio of pulse width (PW) (pulse active time) to period (T). The duty cycle (D) can be defined according to the following formula: D=PW/T. The nature of the duty cycle of the PWM is intended for three-phase motors, for which up to six of those pulse width modulated signals are necessary for control. Within the present invention, a trip signal is a signal sent by the pulse width modulator 244 to cut off the power level in the event of an error condition.

There are many situations where it may be necessary to stop the power generating hardware. A trip signal indicates that this condition exists. For example, a fault condition, such as a short circuit, may exist in the power stage itself. A trip can be signaled because the temperature in the component is too high, or there is too much current flowing. A trip can be signaled because one or more motors are in an incorrect position, or because the motors are running at the wrong speed.

In some industrial environments, there can be significant amounts of electromagnetic interference that can affect the signal output of electronic devices. Changes in the signal output can be interpreted as indicating transient fluctuations and errors in the component from which the signal output came. Sometimes this can cause false positives in false detections. Furthermore, not all error detections require power stage shutdown. As will be described in more detail below, examples of the present invention include systems and methods for filtering transient fluctuation indicative signals. In some examples, transient fluctuation filtering is performed by one or more logic blocks configured to differentiate between PTOS that require power stage shutdown and PTOS that do not require power stage shutdown. In some instances, combining multiple PTOSs into a single PTOS is an aspect of instantaneous fluctuation filtering.

Aspects of the invention relate to capturing data for diagnostic purposes. For example, if a fault condition is detected once for a component (instant fluctuation), it may be appropriate to ignore the fault condition, whereas if the same fault condition is detected three times in close proximity, investigating the cause of the transient fluctuation may be as appropriate. In one or more instances of the invention, the PTOS is recorded and summarized. In this way, PTOS data from different information sources is fed to a transient filter (which may be a state machine) in order to improve the accuracy of the operation of the transient filter over time. In some instances, the filter logic can be reprogrammed based on the described transient fluctuation analysis. In some instances, the transient fluctuation data is analyzed in real-time and fed back to the transient fluctuation filter.

The signal between the PWM and the motor driven by the PWM is the motor side communication. The motor-side communication is performed according to the motor-side communication protocol that is not the Ethernet protocol. Motor side communication is serial based, but it is real time communication of position data to the control unit and then motor current, these are bit streams typically from an analog/digital computer using the delta-sigma method 216 with data on the current value contained in the bitstream. Some motor-side communications are protocol-based communications (like position feedback signals), while other motor-side communications (like motor currents) are sent in the bit stream. A pulse width modulated signal is an example of a digital control signal.

In at least one example of the invention, a filter state machine receives a signal indicating that one or more events have occurred. The filter state machine can have a static trip configuration or a dynamic trip configuration. A filter that operates in a static configuration (or mode) will issue a trip signal when certain events (eg, transient fluctuations) are detected. A filter state machine operating in dynamic mode detects patterns of events. For example, a dynamically configured filter may issue a trip signal if the same error is detected multiple times (depending on the severity of the error) in a particular period.

In at least one example of the present invention, a transient fluctuation filter can be programmed to issue a trip event indication signal (TEIS) depending on what event signal the filter receives. Signals (412A, 422) input to transient fluctuation filters (412, 417) through logic block (414) or amplifier (417A) or other components may experience impulse noise, where the signal briefly switches from one state to another a state and then return. For example, going from inactive to active, and then quickly back to inactive. The transient fluctuation filter (412, 417) will remove short-term state changes in the inactive input signal (eg, low) and ensure that the output signal from the filter remains inactive (does not switch to the incoming state), The active input signal is assumed to be within a predefined instantaneous fluctuation width.

In one or more examples, the burst filter has an active state and a reset state. When the ICSS 200 is powered up, the components of the ICSS need to go into a defined reset state. After the reset state, a component (eg, a motor application) can enter an active state. The timing of the reset state is controlled by the state machine. The state machine (421) can be programmed for a single detection. When programmed for single-shot detection, once the state machine (421) determines that an event or combination of events worthy of a trip signal has occurred (as long as the state machine receives a valid and unmasked (active) trip input (411 to 420)), And as a result the trip signal is output (becomes a predefined value, becomes active), the output signal (408) will remain active (also referred to as 'latching') even if the input trip signal returns to an inactive state.

The state machine can be programmed so that the detection and trip output settings are reset with the cycle time of the cycle of the motor control loop. In this cycle-by-cycle mode, when the inputs (411 to 420) disappear, the trip signal (408) will end and the PWM (244) will resume normal operation. A single detection helps ensure that the power stage is completely shut down and the motor current goes to zero (until reset externally, albeit manually). Single detection is more suitable for critical fault conditions such as short circuit detection or position error faults. Note that in some examples, the state machine ( 421 ) may be configured to handle some trip inputs in a single shot, while for other trip inputs, the state machine will stop issuing trips when these other inputs become inactive in the next cycle signal (408). Therefore, the ICSS can be tailored according to the user's needs. In some embodiments, the state machine may scan for transient fluctuations in one or more multiples of 31.25 microseconds. In at least one embodiment, the transient fluctuation filter scans the transient fluctuation signal at a rate of 60 kilohertz. In at least one embodiment, the transient fluctuation filter scans the transient fluctuation signal at a rate of 80 kilohertz.

Unlike in conventional systems, the ICSS 200 manages all aspects of protection source and pulse width modulated power control. In one or more embodiments, the transient fluctuation filter component of ICSS 200 is highly customizable in that the transient fluctuation filter component is programmable and configurable to to operate. Despite the versatility and programmability of the instant fluctuation filter, the instant fluctuation filter also has a low latency. In one or more examples, information is moved through ICSS 200 at five nanosecond intervals. In some examples, positional information (with respect to external devices, such as motors) is communicated through one or more communication interfaces (eg, 270, 271, and 272 in Figure 2B). This location information can be real-time information. In some instances, since the location information is received in real-time, if the location information indicates that there is an error, information about the positioning error is transmitted to the hardware state machine. If the hardware state machine is configured (for example) to trigger on a position error, the hardware state machine will immediately output a trip signal. In at least one instance of ICSS 200 , there is a combination of hardware state machines and computational logic that resides in the real-time processing and communication domains of ICSS 200 . This arrangement differs from conventional solutions in which the communication on the control function is controlled by an external ASIC or SPGA and the information on the control function is passed to the controlling PRU through the interface.

In at least one example of the present invention, low latency in ICSS 200 is enhanced by integrating all trip inputs into one hardware device. Management of all trip inputs occurs in a single hardware state machine (421).

3 illustrates aspects of pulse width generation 301 in accordance with an example of the present disclosure. In the example shown in Figure 3, nine complementary pulse width modulated outputs are matched to three motors 311. Pulse width modulated signal 308 and pulse width modulated signal 309 are generated by pulse width modulator (PWM) 244 . For example, the 'x' suffix in the 'PWMx' indicator (308) and the '/PWMx' indicator (309) reflects the fact that more than one pair of pulse width modulated signals (272) are used to drive a three-phase motor. Control signal 305 and comparator signal 306 are generated by IEP0 241 . Control signal 305 and comparator signal 306 go to PWM 244 . Also shown is the trip output signal 307 (425), which goes to the PWM 244 when certain types of events occur, as will be explained in more detail in the discussion of Figures 4A and 4B. Control signal 305 and pulse width modulated signal 308 and pulse width modulated signal 309 are generated by PWM 244. Location event indicator 302 is an indication that an error event has occurred. Location event indicator 303 is an indication that another error event has occurred. PRU 219 and peripheral interface 217 form a feedback system that tracks the motor's position data and generates a trip event number five indication signal (420) when a position error is detected. The sawtooth signal 305 is output from the compare0 register (402). Period 304 of signal 305 is also shown in FIG. 3 . Trip event indicator 307 indicates that external output pin 432 has sent a signal (TEIS-2) indicating that trip event-2 has occurred. Pin 432 is connected to PWM 244. The delta-sigma current measurement 312 is produced by the sigma-delta 216 of FIG. 2 and the PRU.

4A illustrates a logical configuration 400 of a pulse width modulation monitor and controller of an example ICSS (200). FIG. 4B illustrates the trip signal logic circuit 421 of the ICSS (200) interacting with the logic configuration 400. As shown in FIG. 4B and as discussed above, each trip signal logic circuit 421 may generate a single trip output signal 425 . The value of selector signal 426 specifies whether trip signal logic circuit 421 operates in a one-shot mode or alternatively in a cycle-by-cycle mode, as explained above. In the example illustrated in Figure 4B, trip signal logic 421 is configured to track five trip input signals each corresponding to a trip event.

The gate 414 shown in FIG. 4A monitors the PWM output signal 308 of the PWM terminal 430 and the PWM output signal 309 of the PWM terminal 431. If both signal 308 and signal 309 are active (high), gate 414 outputs event indicator signal number one (EIS-1) 412A to transient filter 412. Depending on how the transient fluctuation filter is configured, when transient fluctuation filter 412 receives EIS-1 412A, transient fluctuation filter 412 sends Trip Event Indication Signal No. 1 (TEIS-1) 411 to TRIP Signal logic circuit 421 . As noted, PWM (244) produces nine complementary pulse width modulated outputs for each group of three motors. Based on EIS 412A from gate 414, TEIS-1 411 monitors the pulse width modulated signal generated by PWM (244) to ensure that pulse width modulated signals 308, 309 are complementary to each other (in phase, not activating both transistors at the same time, etc.). The transient surge filter 412 may be configured using the configuration memory map register 413 to filter or block EIS-1 412A from the gate 414 that does not meet a certain threshold, such as when the trip signal is too brief. Momentary fluctuations such as these are reflected in small peaks of 1 or 0, which are usually caused by external electromagnetic interference.

Event indication signal number two (EIS-2) 432A (shown in FIG. 4A ) corresponds to a signal from external source 432 . For example, an external power board can be configured to transmit EIS-2432A if the temperature of the power board exceeds a certain threshold. As in the case of TEIS-1 411, a transient surge filter 417 is interposed between the external source 432 and the input 415A of the TEIS-2 415 (corresponding to trip event-2), which may 416 is configured to filter error signals indicating false positives (eg, EIS-2 432A). The transient fluctuation filter 417 only sends the trip event indication signal (TEIS-2) 415 to the trip signal logic circuit 421 if the EIS-2 432A from the external source 432 meets certain customizable criteria. In practice, the filters 412 and 417 will be programmed based on the needs of the environment in which the ICSS (200) operates. For example, if a signal error such as jittering or ringing occurs while the robotic arm is being used to paint, then such signal error is more likely to indicate a real fault than if it occurs in a welding environment (where electromagnetic interference is not uncommon) . The programmability of the filters 412, 417 allows fine tuning of the sensitivity of error detection in the ICSS. Trip event number three indicating signal 418 indicates that the sigma-delta (216) has detected a short circuit. Trip event number four indication signal 419 indicates that an overcurrent has been detected in, for example, one or more motors controlled by the ICSS (200). Trip Event Indication Signal Number Five (TEIS-5) 420 is based on feedback received by the PRU 219 (using a serial-based protocol). If the PRU determines that an external component controlled by the ICSS ( 200 ) is in an incorrect position, the PRU 219 sends the TEIS-5 420 to the trip signal logic circuit 421 . The trip signal logic 421 may be configured 427 to mask one or more trip input signals, which means that the trip signal logic 421 may be configured to send a trip output signal 425, e.g., to cause the motor to shut down (only for the desired combination of trip events).

The trip capture block 401, comparator 0 403, counter 403, drift compensation input 404, comparator 1 405, and comparator 2 409 illustrated in Figure 4A are components of IEP0 (241). The hit signal 405A is sent from the comparator 405 of the IEP0 241 to the input PWM1 of the PWM 244. Output buffer 407 is interposed between IEP0 and PWM 244 . Buffer flip-flop 406, output buffer 407, buffer 410, glitch filter 412, configuration input 413, gate 414, trip event two input 415A, glitch filter configuration input 416, buffer 417 and Trip signal logic 421 is a component of PWM 244 . The output pin 430 and the output pin 431 are the output pins of the PWM 244 . Signal 308 is sent from output pin 430 and signal 309 is sent from output pin 431 . Comparator 1 405 compares its programmed value (cmp_1) with the value in counter 403 (IEP_counter). If the value in comparator 1 405 is equal to the value in counter 403, then comparator 1 will issue a hit signal 405A.

In at least one embodiment, when comparator 1 405 sends hit signal 405A (see 306 of FIG. 3 ) to PWM 244 , the hit signal forms a rising edge in signal 308 . Similarly, when comparator 2 409 sends hit signal 409A to PWM 244, the hit signal forms a rising edge in signal 309. IEP counter 403 counts errors and the number of errors detected is represented by the rising edge of sawtooth waveform 305. Like comparator 1 405, comparator 2 409 compares its programmed period value (cmp_0) with the value in IEP counter 403 (iep_counter). When the number of errors in the IEP counter 403 reaches the value in the comparator 402, the IEP counter 403 is reset to zero. (If the values in comparator 2 409 and IEP counter 403 are the same, then the value of IEP counter 403 is reset to zero.)

In at least one example of the present invention, it may be beneficial to synchronize the pulse width modulated signal from PWM 244 with other cycles (eg, communication cycles). As shown in Figure 4A, drift compensation 404 is used to shift the output signals 308, 309 from the PWM 244 to keep the output signals in phase with other components, such as an external clock. The PWM 244 has an active mode 406A and an initialization mode 406B; an input 406 selects the operating modes 406A, 406B of the PWM 244 . During initialization mode 406B, the pulse width modulated output signal 272 is set to high impedance H or low impedance L. If PWM 244 receives hit signal 405A at input buffer 407 when PWM 244 is in active mode 406A, then PWM 244 will output 272 a high impedance signal H or a low impedance signal L or will output 430 ( 272 ) from a ( The current) output signal (H or L) toggles to the other output signal, depending on how the input buffer 407 is programmed. In one or more examples, input buffer 407 can be easily reprogrammed according to the needs of the user and/or the environment in which ICSS 200 operates. Trip signal 408 is transmitted by trip signal logic circuit 421 (when the trip condition is determined by trip signal logic circuit 421) and enters input buffer 407, as shown. When PWM 244 is in active mode 406A, trip signal 408 will cause output 430 of PWM 244 to be high impedance (Z), high (H) or low (L), depending on how buffer 407 is configured. Trip signal 408 will override hit signal 405A. Comparator-2 409 has the same function as Comparator-1, but for the negated pulse width modulated signal 309. Comparator-2 409 of IEP0 241, when asserted, sends hit signal 409A to filter 410, which, depending on the setting of the filter, outputs hit signal 409A to output 431 of PWM 244 via signal 410A. Signal 410A also goes to gate 414 . If both signals 410A and 407A are active, gate 414 will generate an EIS at 412 which will trigger TEIS 411 at transient filter 412 which will cause trip logic 421 to issue a trip signal 408, the trip signal will again make the PWM (244) inactive. A situation where both the (complementary) PWM signals PWM1 and /PWM1 are active is catastrophic because this would turn on and create a short circuit in both the high-side and low-side switches in the power stage. This condition is called shoot-through, which should be avoided due to possible damage or injury that can be caused by a short circuit in the power stage.

Filter 410 is controlled by a state machine (421), as will be explained in more detail below. During the first state (initialization) of filter 410, signal 410A is the initialization signal, during the second (active) state, signal 410A corresponds to hit signal 409A, and during the third (error) state, signal 410A is tripped according to signal 408 is set.

TEIS-1 411 corresponds to an error condition in which output signal 308 from PWM 244 terminal 430 and output signal 309 from PWM 244 are both active (high). If both output signal 308 from PWM 244 terminal 430 and output signal 309 from PWM 244 are in an active state (eg, both are high), the power stage of the motor being driven by PWM 244 may be damaged (due to short circuit). Gate 414 monitors PWM output terminal 430 and PWM output terminal 431 . If gate 414 determines that PWM output terminal 430 and PWM output terminal 431 have the same high output, which means that a trip event has occurred, gate 414 sends EIS-1 412A to transient ripple filter 412 in this case. (When both signal 308 and signal 309 are low, it is not an error condition.) If transient fluctuation filter 412 determines that EIS-1 412A corresponds to a true error or fault condition rather than transient fluctuation, then the transient fluctuation of FIG. 4A The burst filter 412 sends the TEIS-1 411 to the trip signal logic circuit 421 of Figure 4B.

Filter 412 may be configured, for example, to ignore EIS-1 412A when EIS-1 412A falls below a threshold. For example, in robotics and machine environments, if there is minimal tripping, it can be attributable to electromagnetic disturbances in the environment (momentary fluctuations), rather than a true error condition that authorizes the shutdown to be caused by Power stage for PWM 244 driven devices. Again, the sensitivity of PWM 244 to transient fluctuations can be adjusted by configuring transient fluctuation filter 412 (and transient fluctuation filter 417). Instantaneous fluctuation filter 412 may be configured 413 to mask (or mask) EIS-1 412A shorter than a threshold period; the threshold period may be set to 10 nanoseconds or 100 nanoseconds, and between 10 nanoseconds and 100 nanoseconds any period between seconds. The configuration memory mapped register stores the thresholds for the transient fluctuation filter 412 . The transient fluctuation filter 417 can be configured using the configuration memory map register 416 to mask (or mask) event indication signals shorter than a threshold period (eg, EIS-2 432A); the threshold period can be set to 10 nanoseconds or 100 nanoseconds, and any period between 10 nanoseconds and 100 nanoseconds. The configuration memory map register 416 stores the threshold value for the transient fluctuation filter 417.

In at least one example, trip signal logic 421 may receive five trip signals. TEIS-1 411 comes from the transient fluctuation filter 412 and indicates that the output terminals 430, 431 of the PWM 244 are high at the same time. The trip event-1 input 411a is marked '[2..0]' because the three-phase motor is driven by three pairs of pulse width modulated signals 308, 309, 430, 431. Trip event number two indicating signal 415 indicates a fault in external component 432 . Trip event number three indication signal 418 is from PRU 219 and sigma-delta accelerator 216 and indicates that there is a short circuit in SoC 246, of which ICSS 200 is a component. Trip event number four indication signal 419 is from PRU 219 and sigma-delta accelerator 216 and indicates that there is an overcurrent in SoC 246, of which ICSS 200 is a component. Trip event indication signal five 420 is from PRU 219 and peripheral interface 217 and may indicate that the device being controlled by ICSS 200 is in an incorrect position. Mask input 427 and compare-0 input 426 are used to configure trip signal logic circuit 421 .

FIG. 5 illustrates a system 500 according to an example of this disclosure. Block 501 highlights aspects of Figures 2A-2C. Controlling PRU-1 502 corresponds to PRU 215 of Figure 2A. Interface PRU-1 503 corresponds to PRU 219 of Figure 2A. Control PRU-2504 corresponds to PRU 265 of Figure 2C. Interface PRU-2 503 corresponds to PRU 289 of Figure 2C. IEP Timer-1 506 corresponds to IEP0 241 of Figure 2B. IEP Timer-2 corresponds to IEP1 273 of Figure 2B. System 500 ( 200 ) includes four multiplying units 508 . System 500 includes a combination 509 of broadside random access memory and triangular lookup table. Task manager 510 corresponds to task managers 209 and 223 of FIG. 2A and task managers 269 and 293 of FIG. 2C. The interrupt controller 511 corresponds to the interrupt controller 236 of Fig. 2B. PWM Block-1 512 and PWM Block-2 513 illustrate the fact that ICSS 200 includes multiple pulse width modulators like PWM 244 of Figure 2B. The delta-sigma block 514 illustrates the fact that the PRU 219 and accelerator 216 are capable of producing nine sigma-delta signals (418, 419). The delta-sigma block 513 illustrates the fact that the PRU 219 and accelerator 216 of Figure 2A are each capable of generating nine sigma-delta error signals (418, 419). The delta-sigma block 514 illustrates the fact that the PRU 265 and accelerator 286 of Figure 2C are also each capable of generating nine sigma-delta error signals (418, 419). The encoder block 516 illustrates that the peripheral interface 217 utilizes three encoders for motor position measurement. Likewise, the encoder block 517 illustrates that the peripheral interface 287 utilizes three encoders for motor position measurement.

6 is a state diagram 600 showing the relationship of the possible states of the buffer 407 of FIG. 4A. Upon power up, buffer 407 enters initialization state 601 . When the buffer 407 is in the initialization state 601, the output 407A of the buffer 407 may be high impedance (Z), high (H), or low (L). After initialization 601 of buffer 407 is complete, buffer 407 may enter an active (operational) state 602. When buffer 407 is in active state 602, if buffer 407 receives hit signal 405A, then hit signal 405A will cause output 407A of buffer 407 to be high (H), low (L), or hit signal 405A will cause The value of output signal 407A is toggled (if output 407A is high then output 407A will toggle low; if output 407A is low then output 407A will toggle high). Regardless of whether the buffer 407 is in the initialization state 601 or the active state 602, when the buffer 407 receives the trip signal 408, the buffer will be placed in the safe mode 603. In safe mode, depending on how buffer 407 is programmed, the value of output signal 407A will be high impedance (Z), high (H), or low (L). Note again that buffer 407 can be reconfigured based on the needs of the user.

7 is a block diagram of a state machine 700 (421) according to an example of the present invention. In Figure 7, block 701 represents the inputs (411 to 420) of the state machine (421), the trip input is analyzed by the state machine 700 and causes the state machine 700 to send a trip signal 703 to the input-output port 702, which input-output The port includes buffer 407 and output terminal 430 of PWM 244 . Block 704 illustrates the configurable logic of state machine 700 that determines how state machine 700 will process existing trip signals 703 depending on whether state machine 700 is in one-shot mode or cycle-by-cycle mode, as previously described. describe.

Although an SoC is primarily used as an example type of chip throughout the above disclosure, it will be appreciated that the techniques described herein may be applied to design other types of IC chips. Such IC chips may include, for example, general-purpose or special-purpose (ASIC) processors, field programmable gate arrays (FPGAs), graphics processors (GPUs), digital signal processors (DSPs) based on x86, RISC, or other architectures , System-on-a-Chip (SoC) processors, microcontrollers and/or related chipsets.

Throughout this specification and the claims, specific terms are used to refer to specific system components. As will be appreciated by those skilled in the art, different parts may refer to a component by different names. This document does not intend to distinguish between components that differ in name but are functionally identical. In this disclosure and the claims, the terms "including" and "comprising" are used in an open-ended fashion, and should therefore be interpreted to mean "including but not limited to...". Moreover, the terms "couples or couples" are intended to mean indirect or direct wired or wireless connections. Thus, if a first device is coupled to a second device, the connection can be through a direct connection or through an indirect connection through other devices and connections. The statement "based on" is intended to mean "based at least in part on." Thus, if X is based on Y, then X can be based on Y and any number of other factors.

The foregoing discussion is intended to explain the principles and various embodiments of the present invention. Numerous changes and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. The appended claims are intended to be construed to cover all such changes and modifications.

Claims (20)

1. A control system comprising: power level; a pulse width modulator coupled to the power stage, the pulse width modulator configured to switch off the power stage when the pulse width modulator receives a trip signal; a processor coupled to the pulse width modulator; a logic circuit coupled to the pulse width modulator and the processor, the logic circuit comprising: A first interface that includes a plurality of inputs, wherein the plurality of inputs include: a first input configured to receive a first trip event indication signal derived from the pulse width modulator; a second input configurable to receive a second trip event indication signal originating at an electronic device releasably coupled to the second input at a connection port; and a third input configured to receive a third trip event indication signal from the processor; and The second interface, which includes: a first selection input configured to receive the first selection; and a second selection input configured to receive the second selection, wherein the logic circuit is configured to send the trip signal to the pulse width modulator when the logic circuit receives at least one of the three trip event indication signals. 2. The control system of claim 1, wherein the plurality of inputs further comprises: a fourth input configured to receive a fourth trip event indication signal from the processor; and A fifth input configured to receive a fifth trip event indication signal from the processor. 3. The control system of claim 2, wherein: the third trip event indication signal corresponds to a short circuit condition determined by the processor; and The fourth trip event indication signal corresponds to an overcurrent condition determined by the processor. 4. The control system of claim 3, wherein the fifth trip event indication signal corresponds to a position error condition determined by the processor, the position error condition indicating that the power stage is in an incorrect position. 5. The control system of claim 1, further comprising a first filter coupled between the pulse width modulator and the first input, wherein the first filter is configured to: receiving a first error signal from the pulse width modulator, the first error signal having a duration; determining that the duration of the first trip event indication signal exceeds a first threshold; The first trip event indicator signal is sent to the logic circuit in response to the determination that the duration of the first trip event indicator signal exceeds the first threshold. 6. The control system of claim 5, wherein the pulse width modulator uses three pairs of pulse width modulation terminals to drive the power stage, and the first error signal indicates wherein the three pairs of pulse width modulation terminals An error condition in which at least one pair of two terminals transmits a high signal at the same time. 7. The control system of claim 6, further comprising a second filter coupled between the connection port and the second input, wherein the second filter is configured to: receiving a second error signal from the connection port, the second error signal having a duration; determining that the duration of the second trip event indication signal exceeds a second threshold; The second trip event indication signal is sent to the logic circuit in response to the determination that the second trip event indication signal exceeds the second threshold. 8. The control system of claim 7, wherein the first threshold is a first length of time greater than or equal to 10 nanoseconds and less than or equal to 100 nanoseconds, and the second threshold is greater than or equal to 10 nanoseconds second and less than or equal to 100 nanoseconds for a second length of time. 9. The control system of claim 1, wherein the control system is a component of a system-on-a-chip. 10. A logic circuit coupled to a pulse width modulator, the logic circuit configured to receive a plurality of inputs, the plurality of inputs comprising: a first input corresponding to a first signal originating at the pulse width modulator; a second input corresponding to a second signal originating at the electronic device; and a third input corresponding to a third signal originating at the one or more processors; wherein the logic circuit is configured to controllably select which of the plurality of inputs to output to a pulse width modulator as a trip signal to cause the pulse width modulator to turn off a signal driven by the pulse width modulator power level. 11. The logic circuit of claim 10, wherein the plurality of inputs further comprises: a fourth input corresponding to a fourth signal originating at the processor; and A fifth input corresponding to a fifth signal originating at the processor. 12. The logic circuit of claim 11, wherein: the third signal corresponds to a short circuit condition determined by the processor; and The fourth signal corresponds to an overcurrent condition determined by the processor. 13. The logic circuit of claim 12, wherein the fifth signal corresponds to a position error condition determined by the processor, the position error condition indicating that the power stage is in an incorrect position. 14. A method for managing a trip signal for a pulse width modulator, the method comprising: Use a pulse width modulator to drive the power stage; receiving a first input at a logic circuit, the first input corresponding to a first trip event indication signal originating at the pulse width modulator; receiving a second input at the logic circuit, the second input corresponding to a second trip event indication signal originating at an electronic device releasably coupled to the logic circuit at a port; receiving a third input, the third input corresponding to a third trip event indication signal from the processor; Which input is selected by the logic circuit to output to the pulse width modulator as a trip signal to cause the pulse width modulator to turn off a power stage driven by the pulse width modulator, wherein selecting includes selecting from an input, a plurality of inputs of the second input and the third input to select; and The selected input is output from the logic circuit. 15. The method of claim 14, further comprising: receiving a fourth input at the logic circuit, the fourth input corresponding to a fourth trip event indication signal from the processor; and receiving a fifth input at the logic circuit, the fifth input configured to receive a fifth trip event indication signal from the processor, wherein selecting at the logic circuit which input to output to the pulse width modulator as a trip signal to cause the pulse width modulator to turn off the power stage driven by the pulse width modulator further comprises performing from a plurality of inputs Select, wherein the plurality of inputs include the first input, the second input, the third input, and the fourth input. 16. The method of claim 15, further comprising: using the processor to determine that a short circuit condition exists; and using the processor to determine that an overcurrent condition exists, wherein the third input corresponds to the short circuit condition determined by the processor; and The fourth input corresponds to the overcurrent condition determined by the processor. 17. The method of claim 16, further comprising: using the processor to determine a position error condition, and wherein the fifth trip event indication signal corresponds to the position error condition determined by the processor, the position error condition indicating that the power stage is in an incorrect position. 18. The method of claim 14, further comprising: receiving a first error signal from the pulse width modulator at a first filter, the first error signal having a duration; determining, at the filter, that the duration of the first error signal exceeds a first threshold; The first error signal is sent from the first filter to the logic circuit in response to the determination that the duration of the first trip event indication signal exceeds the first threshold. 19. The method of claim 18, wherein driving the power stage further comprises driving the power stage using three pairs of pulse width modulation terminals, and wherein the first error signal indicates wherein the three pairs of pulse width modulation An error condition in which two terminals of at least one pair of terminals emit a high signal at the same time. 20. The method of claim 17, further comprising: receiving a second trip event indication signal from the port at a second filter, the second trip event indication signal having a duration; determining, at the second filter, that the duration of the second trip event indication signal exceeds a second threshold; and The second trip event indication signal is sent to the logic circuit from the logic circuit to the pulse width modulator in response to the determination that the second trip event indication signal exceeds the second threshold.

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