CN111554619A

CN111554619A - Chip packaging method

Info

Publication number: CN111554619A
Application number: CN202010365970.7A
Authority: CN
Inventors: 夏鑫; 李红雷
Original assignee: Nantong Fujitsu Microelectronics Co Ltd
Current assignee: Nantong Fujitsu Microelectronics Co Ltd; Tongfu Microelectronics Co Ltd
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-08-18

Abstract

The application discloses a chip packaging method, which comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the periphery of the connecting chip is provided with a plurality of first conductive columns, and the first plastic packaging layer covers the side face of the connecting chip and the side face of the first conductive columns; the non-functional surface of the connecting chip faces the packaging substrate, and the first conductive column is electrically connected with the packaging substrate through first welding flux; the first main chip and the second main chip are arranged on one side of the functional surface of the connecting chip respectively, the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns. The chip packaging method provided by the application can reduce the packaging cost and improve the performance of the packaged device.

Description

Chip packaging method

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.

Background

The existing polymer-based 2D packaging technology is the most basic and widely applied packaging form, is mature in technology and low in cost, but has no connection in the third direction and is large in line width. The recently developed packaging technology based on the silicon interposer is small in line width, and the formed packaged device is excellent in electrical performance and thermal conductivity, but high in cost, and the silicon material is high in brittleness, so that the stability of the packaged device is low. Therefore, there is a need to develop a new packaging technique that combines the advantages of the existing packaging techniques, can reduce the cost, and can form a packaged device with excellent performance.

Disclosure of Invention

The technical problem mainly solved by the application is to provide a chip packaging method, which can reduce the packaging cost and improve the performance of a packaged device.

In order to solve the technical problem, the application adopts a technical scheme that:

a chip packaging method is provided, which comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the periphery of the connecting chip is provided with a plurality of first conductive columns, and the first plastic packaging layer covers the side face of the connecting chip and the side face of each first conductive column; enabling the non-functional surface of the connecting chip to face a packaging substrate, and enabling the first conductive column to be electrically connected with the packaging substrate through first welding flux; respectively with first main chip and second main chip set up in connect the functional surface one side of chip, just first main chip with the signal transmission district of second main chip is adjacent to be set up, first main chip with the second main chip the pad in signal transmission district with it is connected the chip electricity, first main chip with the pad in the non-signal transmission district of second main chip with first leading electrical pillar electricity is connected.

Wherein the providing a first package comprises: providing a removable carrier plate, wherein the carrier plate is defined with at least one area; forming a plurality of the first conductive pillars at an edge of each of the regions; adhering the connecting chip to the inner side of each region, wherein the non-functional surface of the connecting chip faces the carrier plate, and second conductive posts are respectively arranged at the positions of bonding pads on the functional surface of the connecting chip; forming a first plastic package layer on one side of the carrier plate, where the connection chip is arranged, and exposing surfaces of the second conductive columns and one side of the first conductive columns, which are far away from the carrier plate, from the first plastic package layer; and removing the carrier plate.

Alternatively, the providing of the first package body includes: providing a removable carrier plate, wherein the carrier plate is defined with at least one area; forming a plurality of first conductive pillars at each of the region edges; adhering the connecting chip to the inner side of each region, wherein the functional surface of the connecting chip faces the carrier plate, and second conductive posts are respectively arranged at the positions of bonding pads on the functional surface of the connecting chip; forming a first plastic package layer on one side of the carrier plate, where the connection chip is arranged, and exposing the surface of one side, away from the carrier plate, of the first conductive column from the first plastic package layer; and removing the carrier plate.

Wherein, the non-functional surface of the connecting chip faces to a package substrate, and the first conductive pillar is electrically connected with the package substrate through a first solder, before, including: and forming the first solder on the surface of one side, facing the package substrate, of the first conductive pillar, or forming the first solder on the surface of one side of the package substrate.

Wherein, the non-functional surface of the connecting chip faces to a package substrate, and the first conductive pillar is electrically connected with the package substrate through a first solder, and then, the method comprises: and forming a first underfill between the first plastic packaging layer and the packaging substrate.

Wherein, set up first main chip and second main chip in respectively connect chip's function face one side, preceding, include: forming a third conductive pillar on the pad of the signal transmission area of the first main chip and the second main chip, and forming a fourth conductive pillar on the pad of the non-signal transmission area of the first main chip and the second main chip; forming a second solder on the third conductive pillar and the fourth conductive pillar.

The surfaces of one sides, far away from the package substrate, of the first conductive pillars and the second conductive pillars are flush, and the heights of the third conductive pillars and the fourth conductive pillars are equal.

Wherein, set up first main chip and second main chip in respectively connect chip's functional surface one side, later, include: and forming a second underfill between the functional surfaces of the first main chip and the second main chip and the first molding layer.

Wherein after the forming the second underfill, including: and forming a second plastic packaging layer on the first plastic packaging layer and the second underfill, wherein the second plastic packaging layer covers the side surfaces of the first main chip and the second main chip.

The first packaging body comprises at least two packaging units, each packaging unit comprises at least one connecting chip and a plurality of first conductive columns located on the periphery of the connecting chip, and the first plastic packaging layer continuously covers all the packaging units; before the step of directing the non-functional surface of the connection chip to a package substrate and electrically connecting the first conductive pillar to the package substrate through a first solder, the method further includes: cutting off the area between the adjacent packaging units to obtain the first packaging body containing the single packaging unit.

The beneficial effect of this application is: different from the prior art, the chip packaging method provided by the application adopts different connection modes for the signal transmission area and the non-signal transmission area of the main chip: for the signal transmission area, a connecting chip is adopted to connect the two main chips, so that the signal transmission rate between the main chips is improved, and the performance of a packaged device is improved; for the non-signal transmission area, the common conductive column is connected with the packaging substrate, so that the packaging cost can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:

FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;

FIG. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 1;

FIG. 3 is a flowchart illustrating an embodiment corresponding to step S101 in FIG. 1;

FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 3;

FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 3;

FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 3;

FIG. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in FIG. 3;

FIG. 5 is a schematic flow chart illustrating another embodiment corresponding to step S101 in FIG. 1;

FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S303 in FIG. 5;

FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S304 in FIG. 5;

FIG. 6c is a schematic structural diagram of an embodiment corresponding to step S305 in FIG. 5;

FIG. 7 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;

FIG. 8 is a schematic structural diagram of an embodiment corresponding to the step included after the step S102 in FIG. 1;

FIG. 9 is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;

FIG. 10 is a schematic flow chart diagram illustrating one embodiment of steps included prior to step S103 in FIG. 1;

FIG. 11 is a schematic structural diagram of an embodiment corresponding to step S402 in FIG. 10;

FIG. 12 is a schematic structural diagram of an embodiment corresponding to steps included after step S103 in FIG. 1;

FIG. 13 is a schematic structural diagram of another embodiment corresponding to the step included after step S103 in FIG. 1;

fig. 14 is a schematic structural diagram of an embodiment of a first package.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the chip packaging method including the following steps:

s101, providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the periphery of the connecting chip is provided with a plurality of first conductive columns, and the first plastic packaging layer covers the side face of the connecting chip and the side face of the first conductive columns.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 1, in fig. 2, only a case that the first package 20 includes a connection chip 21 is schematically shown, the first package 20 further includes a plurality of first conductive pillars 22 and a first molding layer 23, wherein a plurality of first conductive pillars 22 are disposed on the periphery of the connection chip 21, and the first molding layer 23 covers a side surface of the connection chip 21 and a side surface of the first conductive pillars 22. In other embodiments, the first package body 20 may include a plurality of connection chips 21, and the first molding compound layer 23 continuously covers the plurality of connection chips 21.

In one embodiment, please refer to fig. 3, fig. 3 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:

s201, providing a removable carrier plate, wherein the carrier plate is defined with at least one area.

Specifically, referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 3. The carrier 24 is schematically illustrated as defining an area, wherein the carrier 24 is made of a rigid material such as metal, plastic, etc.

S202, a plurality of first conductive pillars are formed at the edge of each region.

Specifically, please refer to fig. 4b, wherein fig. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 3. In the present embodiment, a plurality of first conductive pillars 22 are formed at the edge of the region of the carrier 24 where one region is defined, and the first conductive pillars 22 are made of copper-containing alloy, and can be formed by electroplating or the like. For example, a patterned mask layer may be formed on the surface of the carrier 24, a via hole is formed on the mask layer, the first conductive pillar 22 is formed in the via hole, and finally the mask layer is removed.

S203, adhering a connecting chip on the inner side of each area, wherein the non-functional surface of the connecting chip faces the carrier plate, and second conductive columns are respectively arranged at the positions of the pads on the functional surface of the connecting chip.

Specifically, please refer to fig. 4c, wherein fig. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 3. In the present embodiment, the connection chip 21 is attached to the inner side of the area of the carrier 24 defining one area, the non-functional surface 210 of the connection chip 21 faces the carrier 24, and the second conductive posts 25 are respectively disposed at the pad positions on the functional surface 211 of the connection chip 21. Specifically, the non-functional surface 210 of the connecting chip 21 can be adhered to the carrier 24 by a peelable adhesive such as a double-sided adhesive.

In addition, the present application is not limited to the point in time when the second conductive pillar 25 is formed. For example, before the step S201 or the step S202, the second conductive posts 25 may be formed on the functional surface 211 of the connection chip 21, or when the step S203 is performed, the non-functional surface 210 of the connection chip 21 and the carrier board 24 are attached first, and then the second conductive posts 25 are formed on the functional surface 211 of the connection chip 21. The second conductive pillars 25 may be made of a material similar to that of the first conductive pillars 22, such as copper, and may be formed in a similar manner.

And S204, forming a first plastic package layer on one side of the carrier plate, which is provided with the connecting chip, and exposing the surfaces of the second conductive columns and one side of the first conductive columns, which is far away from the carrier plate, from the first plastic package layer.

Specifically, please refer to fig. 4d, wherein fig. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in fig. 3. A first molding layer 23 is formed on the side of the carrier plate 24 where the connection chip 21 is disposed, and the surfaces of the second conductive pillars 25 and the first conductive pillars 22 away from the carrier plate 24 are exposed from the first molding layer 23. The first molding compound layer 23 may be made of epoxy resin, and can protect the connection chip 21, the first conductive pillars 22, and the second conductive pillars 25.

In addition, in the step S203, the height of the first conductive pillar 22 may be greater than the thickness of the connection chip 21, and the height of the first conductive pillar 22 may be greater than or equal to the sum of the thickness of the connection chip 21 and the height of the second conductive pillar 25, and more preferably, the height of the first conductive pillar 22 is equal to the sum of the thickness of the connection chip 21 and the height of the second conductive pillar 25. In the step S204, a first molding compound layer 23 may be formed on one side of the carrier plate 24, and the first molding compound layer 23 covers one side surfaces of the first conductive pillars 22 and the second conductive pillars 25 away from the carrier plate 24; then, a surface of one side of the first plastic package layer 23 away from the carrier plate 24 is ground, so that the first conductive pillars 22 and the second conductive pillars 25 are flush with the surface of one side of the carrier plate 24 and are exposed from the first plastic package layer 23.

And S205, removing the carrier plate.

With reference to fig. 2, after the carrier 24 is removed, the first package body 20 is obtained, which includes a connection chip 21, a plurality of first conductive pillars 22, and a first molding compound layer 23, wherein the periphery of the connection chip 21 is provided with the plurality of first conductive pillars 22, and the first molding compound layer 23 covers the side surface of the connection chip 21 and the side surface of the first conductive pillars 22.

In another embodiment, please refer to fig. 5, fig. 5 is a schematic flowchart illustrating another embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:

s301, providing a removable carrier plate, wherein the carrier plate is defined with at least one area.

S302, a plurality of first conductive pillars are formed at the edge of each region.

Step S301 and step S302 are the same as step S201 and step S202, respectively, and are not described again here.

And S303, adhering a connecting chip on the inner side of each area, wherein the functional surface of the connecting chip faces the carrier plate, and second conductive columns are respectively arranged at the positions of the pads on the functional surface of the connecting chip.

Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to step S303 in fig. 5. The carrier 34 is schematically illustrated to define an area, a plurality of first conductive pillars 32 are formed at an edge of the area, the connecting chip 31 is adhered to an inner side of the area, the functional surface 311 of the connecting chip 31 faces the carrier 34, second conductive pillars 35 are respectively disposed at pad positions on the functional surface 311 of the connecting chip 31, and the non-functional surface 310 of the connecting chip 31 is far away from the carrier 34.

In addition, the time point of forming the second conductive pillar 35 in the present embodiment may be formed on the functional surface 311 of the connection chip 31 in advance before the above step S303.

And S304, forming a first plastic package layer on one side of the carrier plate, where the chip is connected, and exposing the surface of one side, away from the carrier plate, of the first conductive post from the first plastic package layer.

Specifically, please refer to fig. 6b, wherein fig. 6b is a schematic structural diagram of an embodiment corresponding to step S304 in fig. 5. In this embodiment, the first molding layer 33 is formed on the side of the carrier plate 34 where the connection chip 31 is disposed, the thickness of the first molding layer 33 is the same as the height of the first conductive pillars 32, the height of the first conductive pillars 32 is greater than or equal to the sum of the thickness of the connection chip 31 and the height of the second conductive pillars 32, and at this time, the surface of the first conductive pillars 32 on the side away from the carrier plate 34 is exposed from the first molding layer 33. The non-functional surface 310 of the connection chip 31 may or may not be exposed from the first molding layer 33. The first molding compound layer 33 may be made of epoxy resin, and can protect the connection chip 31, the first conductive pillar 32, and the second conductive pillar 35.

S305, removing the carrier plate.

Specifically, please refer to fig. 6c, wherein fig. 6c is a schematic structural diagram of an embodiment corresponding to step S305 in fig. 5. After removing the carrier 34, a first package 30 is obtained, which includes a connection chip 31, a plurality of first conductive pillars 32, and a first molding compound 33, wherein the periphery of the connection chip 31 is provided with the plurality of first conductive pillars 32, and the first molding compound 33 covers the side surface of the connection chip 31 and the side surface of the first conductive pillars 32.

S102, enabling the non-functional surface of the connecting chip to face the packaging substrate, and enabling the first conductive column to be electrically connected with the packaging substrate through the first solder.

Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1. After the first package 20 is formed, the non-functional surface 210 of the connection chip 21 is directed toward the package substrate 500, and the first conductive pillars 22 are electrically connected to the package substrate 500 through the first solder 26. In another embodiment, as shown in fig. 6c, after the first package 30 is formed, the first package 30 may be turned over so that the non-functional surface 310 of the connecting chip 31 faces downward toward the package substrate 500, so that the first conductive pillars 32 are electrically connected to the package substrate 500 through the first solder.

In this embodiment, before step S102, the first solder 26 may be formed on the surface of the first conductive pillar 22 facing the package substrate 500, or the first solder 26 may be formed on the surface of the package substrate 500, so that the first conductive pillar 22 is electrically connected to the package substrate 500 through the first solder 26.

Further, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment corresponding to the step included after the step S102 in fig. 1, in this embodiment, after the step S102, that is, after the first package body 20 is electrically connected to the package substrate 500, the first underfill 27 is formed between the first molding compound layer 23 and the package substrate 500. The first underfill 27 is made of epoxy resin, etc., so that the connection between the first package body 20 and the package substrate 500 is more stable.

S103, the first main chip and the second main chip are respectively arranged on one side of the functional surface of the connecting chip, the signal transmission areas of the first main chip and the second main chip are arranged adjacently, the bonding pads of the signal transmission areas of the first main chip and the second main chip are electrically connected with the connecting chip, and the bonding pads of the non-signal transmission areas of the first main chip and the second main chip are electrically connected with the first conductive columns.

Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1. The first package body 20 is electrically connected to the package substrate 500, and after the first underfill 27 is formed between the first molding compound layer 23 and the package substrate 500, the first main chip 300 and the second main chip 400 are respectively disposed on one side of the functional surface 211 of the connection chip 21, the signal transmission regions 600 of the first main chip 300 and the second main chip 400 are adjacently disposed, the pads of the signal transmission regions 600 of the first main chip 300 and the second main chip 400 are electrically connected to the connection chip 21, and the pads of the non-signal transmission regions 700 of the first main chip 300 and the second main chip 400 are electrically connected to the first conductive pillars 22. In other embodiments, after the first package 30 and the package substrate 500 shown in fig. 6c are electrically connected, the first main chip 300 and the second main chip 400 may be connected to the functional surface side of the chip 31, respectively, and the detailed operations are the same, and are not described herein again.

In addition, referring to fig. 10, fig. 10 is a schematic flowchart illustrating an embodiment of steps included before step S103 in fig. 1, and step S103 further includes the following steps:

s401, forming a third conductive pillar on the pad of the signal transmission area of the first main chip and the second main chip, and forming a fourth conductive pillar on the pad of the non-signal transmission area of the first main chip and the second main chip.

S402, forming a second solder on the third conductive pillar and the fourth conductive pillar.

Specifically, referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment corresponding to step S402 in fig. 10, which only schematically illustrates that the first main chip 300 is taken as an example, such that the functional surface 341 thereof faces upward, the third conductive pillar 301 is formed on the pad of the signal transmission region 600, the fourth conductive pillar 302 is formed on the pad of the non-signal transmission region 700, and then the second solder 303 is formed on the third conductive pillar 301 and the fourth conductive pillar 302. After the third and fourth conductive pillars and the second solder are formed on the first and second

main chips

300 and 400, the first and second

main chips

300 and 400 are turned over as a whole so that their functional surfaces face down, facilitating electrical connection of the first and second

main chips

300 and 400 with the connection chip 21, respectively. In another embodiment, before step S103, only the third conductive pillars and the fourth conductive pillars may be formed on the first main chip 300 and the second main chip 400, and the second solder is not formed, but the second solder is formed on the surfaces of the first conductive pillars 22 and the second conductive pillars 25 of the connection chip 21 on the side away from the package substrate 500.

In addition, with reference to fig. 9 and fig. 11, in the present embodiment, the surfaces of the first conductive pillars 22 and the second conductive pillars 25 in the first package body 20, which are far away from the package substrate 500, are flush, and at this time, the heights of the third conductive pillars 301 and the fourth conductive pillars 302 are preferably equal, so that the functional surfaces of the first main chip 300 and the second main chip 400 are flush, and the overall structure of the package device can be more stable.

In another embodiment, instead of forming the third conductive pillars and the fourth conductive pillars, a second solder may be formed on the surfaces of the first conductive pillars 22 and the second conductive pillars 25 on the sides away from the package substrate 500, and then directly connected to the pads of the first main chip 300 and the second main chip 400, so that signal transmission can be achieved as well.

In addition, the first main chip 300 may be a CPU or the like, the second main chip 400 may be a GPU or the like, and one first main chip 300 may be electrically connected to at least one second main chip 400 through the connection chip 21. For example, the four corners of the first main chip 300 are provided with signal transmission area pads, and the number of the second main chips 400 corresponding to one first main chip 300 may be four, and the chip types of the four second main chips 400 may be the same or different.

Further, referring to fig. 12, fig. 12 is a schematic structural diagram of an embodiment corresponding to the step included after the step S103 in fig. 1, after the pads of the signal transmission areas 600 of the first main chip 300 and the second main chip 400 are electrically connected to the connection chip 21, and the pads of the non-signal transmission areas 700 of the first main chip 300 and the second main chip 400 are electrically connected to the first conductive pillars 22, the second underfill 28 is formed between the functional surfaces of the first main chip 300 and the second main chip 400 and the first molding layer. The second underfill 28 can protect the third conductive pillars and the fourth conductive pillars, so that the connections between the first main chip 300 and the second main chip 400 and the first package 20 are more stable.

Further, referring to fig. 13, fig. 13 is a schematic structural diagram of another embodiment corresponding to the step included after step S103 in fig. 1, after the second underfill 28 is formed, a second molding layer 29 is formed on the first molding layer 23 and the second underfill 28, and the second molding layer 29 covers the side surfaces of the first main chip 300 and the second main chip 400. In other embodiments, the second underfill may not be formed, and the second molding layer 29 may be directly formed. The second plastic package layer 29 can further protect the packaged device, so that the whole structure of the packaged device is more stable.

In another embodiment, please refer to fig. 14 in combination with fig. 7, fig. 14 is a schematic structural diagram of an embodiment of a first package body, the first package body includes at least two package units 50, each package unit 50 includes at least one connection chip 51 and a plurality of first conductive pillars 52 located at the periphery of the connection chip 51, a first molding compound layer 53 continuously covers all the package units 50, and fig. 14 schematically illustrates a case where the first package body includes two package units 50. Before the non-functional surface 510 of the connecting chip 51 is faced to the package substrate and the first conductive pillar 52 is electrically connected to the package substrate through the first solder 56, the method further includes: the area between adjacent package units 50 is cut away, for example, along the dotted line 800 in the figure, to obtain a first package containing a single package unit 50. Then, step S102 and step S103 described in the above embodiment are performed to obtain a packaged device similar to that shown in fig. 13.

The embodiment can obtain the first packaging body comprising a plurality of packaging units on the wafer level, can improve the packaging efficiency, and in the finally formed packaging device, the signal transmission areas of two main chips are connected by adopting the connecting chip, so that the signal transmission rate between the main chips can be improved, and the performance of the packaging device can be improved; the non-signal transmission area of the main chip is connected with the packaging substrate by adopting a common conductive column, so that the packaging cost can be reduced.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A chip packaging method is characterized by comprising the following steps:

providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the periphery of the connecting chip is provided with a plurality of first conductive columns, and the first plastic packaging layer covers the side face of the connecting chip and the side face of each first conductive column;

enabling the non-functional surface of the connecting chip to face a packaging substrate, and enabling the first conductive column to be electrically connected with the packaging substrate through first welding flux;

respectively with first main chip and second main chip set up in connect the functional surface one side of chip, just first main chip with the signal transmission district of second main chip is adjacent to be set up, first main chip with the second main chip the pad in signal transmission district with it is connected the chip electricity, first main chip with the pad in the non-signal transmission district of second main chip with first leading electrical pillar electricity is connected.

2. The chip packaging method according to claim 1, wherein the providing the first package body comprises:

providing a removable carrier plate, wherein the carrier plate is defined with at least one area;

forming a plurality of the first conductive pillars at an edge of each of the regions;

adhering the connecting chip to the inner side of each region, wherein the non-functional surface of the connecting chip faces the carrier plate, and second conductive posts are respectively arranged at the positions of bonding pads on the functional surface of the connecting chip;

forming a first plastic package layer on one side of the carrier plate, where the connection chip is arranged, and exposing surfaces of the second conductive columns and one side of the first conductive columns, which are far away from the carrier plate, from the first plastic package layer;

and removing the carrier plate.

3. The chip packaging method according to claim 1, wherein the providing the first package body comprises:

forming a plurality of first conductive pillars at each of the region edges;

adhering the connecting chip to the inner side of each region, wherein the functional surface of the connecting chip faces the carrier plate, and second conductive posts are respectively arranged at the positions of bonding pads on the functional surface of the connecting chip;

forming a first plastic package layer on one side of the carrier plate, where the connection chip is arranged, and exposing the surface of one side, away from the carrier plate, of the first conductive column from the first plastic package layer;

and removing the carrier plate.

4. The chip packaging method according to claim 2 or 3, wherein the step of directing the non-functional surface of the connection chip to a package substrate and electrically connecting the first conductive pillar to the package substrate through a first solder comprises:

and forming the first solder on the surface of one side, facing the package substrate, of the first conductive pillar, or forming the first solder on the surface of one side of the package substrate.

5. The chip packaging method according to claim 4, wherein the step of directing the non-functional surface of the connection chip to a package substrate and electrically connecting the first conductive pillar to the package substrate via a first solder comprises:

and forming a first underfill between the first plastic packaging layer and the packaging substrate.

6. The chip packaging method according to claim 1, wherein the disposing the first main chip and the second main chip on the functional surface side of the connection chip respectively comprises:

forming a third conductive pillar on the pad of the signal transmission area of the first main chip and the second main chip, and forming a fourth conductive pillar on the pad of the non-signal transmission area of the first main chip and the second main chip;

forming a second solder on the third conductive pillar and the fourth conductive pillar.

7. The chip packaging method according to claim 5,

the first conductive column and the second conductive column are flush with the surface of one side, away from the packaging substrate, of the packaging substrate, and the heights of the third conductive column and the fourth conductive column are equal.

8. The chip packaging method according to claim 1, wherein the disposing the first main chip and the second main chip on the functional surface side of the connection chip respectively comprises:

and forming a second underfill between the functional surfaces of the first main chip and the second main chip and the first molding layer.

9. The chip packaging method according to claim 8, wherein after the forming the second underfill, the method comprises:

and forming a second plastic packaging layer on the first plastic packaging layer and the second underfill, wherein the second plastic packaging layer covers the side surfaces of the first main chip and the second main chip.

10. The chip packaging method according to claim 1,

the first packaging body comprises at least two packaging units, each packaging unit comprises at least one connecting chip and a plurality of first conductive columns positioned on the periphery of the connecting chip, and the first plastic packaging layer continuously covers all the packaging units;

before the step of directing the non-functional surface of the connection chip to a package substrate and electrically connecting the first conductive pillar to the package substrate through a first solder, the method further includes: cutting off the area between the adjacent packaging units to obtain the first packaging body containing the single packaging unit.