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CN111554335A - Dual port static random access memory - Google Patents

Dual port static random access memory Download PDF

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Publication number
CN111554335A
CN111554335A CN202010466157.9A CN202010466157A CN111554335A CN 111554335 A CN111554335 A CN 111554335A CN 202010466157 A CN202010466157 A CN 202010466157A CN 111554335 A CN111554335 A CN 111554335A
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China
Prior art keywords
mos
port
dual
active regions
bit line
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Pending
Application number
CN202010466157.9A
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Chinese (zh)
Inventor
陈品翰
王钰林
李巍
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202010466157.9A priority Critical patent/CN111554335A/en
Publication of CN111554335A publication Critical patent/CN111554335A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a dual-port static random access memory, which comprises a first MOS (metal oxide semiconductor) first end serving as a first port A of a differential bit line, a second MOS second end connected with a second MOS second end, a third MOS third end, a fifth MOS second end, a sixth MOS second end and a seventh MOS third end, wherein the first MOS third end is connected with a fourth MOS third end serving as a memory word line A; the first end of the second MOS is connected with a power supply voltage, and the third end of the second MOS is connected with the second end of the third MOS, the second end of the fourth MOS, the third end of the sixth MOS, the second end of the seventh MOS and the second end of the eighth MOS; the first end of the third MOS is connected with a power supply voltage; the first end of the fourth MOS is used as a second port of a differential bit line A; the first end of the fifth MOS is used as a second port of the differential bit line B, and the third end of the fifth MOS PG4 is connected with the third end of the eighth MOS to be used as a word line B; the first end of the sixth MOS and the first end of the seventh MOS are connected to the ground; the first end of the eighth MOS is used as a first port of a differential bit line B; the critical dimensions of the fourth MOS PG2 and the fifth MOS PG4 are different from those of the first to third and sixth to eighth MOS.

Description

Dual port static random access memory
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a dual-Port static random access memory (8TDual Port SRAM).
Background
Static Random-Access Memory (SRAM) is one type of Random Access Memory. SRAM is more expensive than Dynamic Random Access Memory (DRAM), but is faster and very low power consuming (especially in idle state). SRAM is therefore preferred for high bandwidth requirements, low power requirements, or both.
In the digital logic chip foundry of semiconductor, Static Random Access Memory (SRAM) is often used as a bit storage tool, wherein a Dual port SRAM (Dual port SRAM) consisting of eight transistors (8T:8 transistors) has Dual ports capable of reading and writing. As shown in fig. 1 and fig. 2, a dual port sram circuit formed by conventional transistors includes 8 transistors PD1, PD2, PU1, PU2, PG1, PG2, PG3, and PG 4. One address line is matched with two differential bit lines and called a port, the first port of the dual port is word lines A _ WL control PG1 and PG2 which are respectively connected with differential bit lines A _ BL and A _ BLB, and the second port of the dual port is word lines B _ WL control PG3 and PG4 which are respectively connected with differential bit lines B _ BL and B _ BLB.
Conventionally, the paths of transistors in the same Port during reading are not consistent, PG1 and PG2 in a Port are not consistent, and PG3 and PG4 in B Port are not consistent. Generally, the ports of the dual port sram composed of eight transistors are uniform, so the critical dimensions (width/length) of the cells PG1, PG2, PG3, PG4 are the same, but the read path is different due to the non-uniformity caused by the conventional layout.
Referring to fig. 3 and 4, the paths of the a _ BL (PG1) read current Iread1 and the B _ BL (PG3) read current Iread 3 are shown. The Iread1(PG1) path from A _ BL through PG1, PD1 to Vss, the Iread 3(PG3) path from B _ BL through PG2, PD2 to Vss.
Referring to fig. 5 and 6, the paths of the a _ BLB (PG2) read current Iread2 and the B _ BLB (PG4) read current Iread 4 are shown. Iread2(PG2) path from A _ BLB through PG2, Poly and Metal lines, PD1 to Vss, Iread 4(PG4) path from B _ BLB through PG4, Poly and Metal lines, PD2 to Vss. In fig. 5 and 6, the circuit is larger than that in fig. 3 and 4 by a section of polysilicon Poly and Metal layer Metal circuit, which means that the circuit has some more resistance, so that the read currents of Iread2 and Iread 4 are lower than those of Iread1 and Iread 3, and the read operation speed is slower. In a conventional Dual-Port static random access memory (8T Dual Port SRAM), reading currents are inconsistent due to different current paths, so that different ports are read at asymmetric speeds, and different Port speeds have different speeds.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing a dual-port static random access memory which can overcome the defect of asymmetric reading speed of different ports caused by inconsistent reading current due to different current paths in the prior art.
To solve the above technical problem, the dual port sram provided in the present invention includes:
a first end of a first MOS PG1 is used as a first A _ BL of the dual-port SRAM differential bit line A port, a second end of the first MOS PG1 is connected with a second end of a second MOS PU1, a third end of a third MOS PU2, a second end of a fifth MOS PG4, a second end of a sixth MOS PD1 and a third end of a seventh MOS PD2, and a third end of the first MOS PG1 is connected with a third end of a fourth MOS PG2 to be used as a dual-port SRAM word line A A _ WL;
the first end of the second MOS PU1 is connected with a power supply voltage Vdd, and the third end of the second MOS PU1 is connected with the second end of the third MOS PU2, the second end of the fourth MOS PG2, the third end of the sixth MOS PD1, the second end of the seventh MOS PD2 and the second end of the eighth MOS PG 3;
the first end of the third MOS PU2 is connected with a power supply voltage Vdd;
the first end of the fourth MOS PG2 is used as a second port A _ BLB of a dual-port SRAM differential bit line A;
a first end of the fifth MOS PG4 is used as a two-port sram differential bit line B port two B _ BLB, and a third end of the fifth MOS PG4 is connected to a third end of the eighth MOS PG3 and is used as the two-port sram word line B B _ WL;
the first end of the sixth MOS PD1 and the first end of the seventh MOS PD2 are connected to the ground;
the first end of the eighth MOS PG3 is used as a dual port sram differential bit line B port-B _ BL;
wherein the critical dimensions of the fourth MOS PG2 and the fifth MOS PG4 are different from the first, second, third, sixth, seventh, and eighth MOS.
In an optional further refinement, the widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are greater than the widths of the first, second, third, sixth, seventh and eighth MOS active regions.
The widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, and the widths of the first, second, third, sixth, seventh and eighth MOS active regions are the same.
In an optional further refinement, the lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are less than the lengths of the first, second, third, sixth, seventh and eighth MOS active regions.
The lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, and the lengths of the first, second, third, sixth, seventh and eighth MOS active regions are the same.
In an optional further refinement, the widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are greater than the widths of the first, second, third, sixth, seventh and eighth MOS active regions, and the lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are less than the lengths of the first, second, third, sixth, seventh and eighth MOS active regions.
The lengths and widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, and the lengths and widths of the first, second, third, sixth, seventh and eighth MOS active regions are the same.
Wherein the second MOS PU1 and the third MOS PU2 are PMOS, and the first, second, third, sixth, seventh, and eighth MOS are NMOS.
The invention provides three specific embodiments, and the principles of the three embodiments are as follows:
1. in the first embodiment, the width (device width scaling) of the active regions of the elements PG2 and PG4 is increased, so that the on-currents of PG2 and PG4 are increased, which means that the on-resistances of PG2 and PG4 are slightly decreased, and the read currents Iread2(PG2) and Iread (PG4) can be increased, thereby improving the dual port sram and making the port operation more symmetrical during reading.
2. In a second embodiment, the active region lengths (device length scaling down) of the elements PG2 and PG4 are reduced, and by using this method, the on-state currents of PG2 and PG4 are increased, which means that the on-state impedances of PG2 and PG4 are decreased, and the read currents Iread2(PG2) and Iread (PG4) can be increased, thereby improving the dual port sram and making the port operation thereof more symmetrical when reading.
3. In the third embodiment, the widths of the active regions of the elements PG2 and PG4 are increased, and the lengths of the active regions of the elements PG2 and PG4 are decreased (device width sizing up + device length sizing down), so that the on-currents of PG2 and PG4 can be greatly increased, which means that PG2 is represented, and the on-resistance of PG4 is greatly decreased, so that the read currents Iread2(PG2) and Iread (PG4) can be greatly increased, thereby improving the dual-port sram and making the port operation thereof more symmetrical during reading.
The invention can at least realize the following technical effects:
1) by means of device scaling, the on-currents of the devices PG2 and PG4 are increased, thereby increasing the read currents Iread2 and Iread 4.
2) The port operation of the dual-port static random access memory is symmetrical.
3) The invention does not need additional light shield, does not need to change the process technology and does not increase the production cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic diagram of a conventional 8T Dual port SRAM circuit.
FIG. 2 is a schematic diagram of a layout of an existing 8T Dual port SRAM.
FIG. 3 is a schematic diagram of Iread1(PG1) and Iread 3(PG3) path layouts.
FIG. 4 is a schematic diagram of Iread1(PG1) and Iread 3(PG3) path circuits.
FIG. 5 is a schematic diagram of Iread2(PG2) and Iread 4(PG4) path layouts.
FIG. 6 is a schematic diagram of Iread2(PG2) and Iread 4(PG4) path circuits.
Fig. 7 is a schematic diagram of a first embodiment of the present invention.
Fig. 8 is a schematic diagram of a second embodiment of the present invention.
Fig. 9 is a schematic diagram of a third embodiment of the present invention.
Description of the reference numerals
Pull down, down pipe PD
PU pull up pipe
PG pass gate tube
Word line, word line
BL bit line, differential bit line
Bit line bar differential bit line
Read current, read current
Circuit
layout of layout
PG 1: first MOS
PU 1: second MOS
PU 2: third MOS
PG 2: fourth MOS
PG 4: fifth MOS
PD 1: sixth MOS
PD 2: seventh MOS
PG 3: eighth MOS
Poly: polycrystalline silicon
Active: active region
CT: contact hole
M1 Metal layer one
Vss: ground
Vdd power supply voltage
A _ WL: a Port word line Control PG1 and PG2, Dual Port SRAM wordline A
B _ WL: port word line Control PG3 and PG4, dual port SRAM wordline B
A _ BL: dual-port SRAM word line differential bit line A port I
A _ BLB: dual-port SRAM word line differential bit line A port two
B _ BL: dual-port SRAM word line differential bit line port B
B _ BLB: and a second port of the word line differential bit line B of the dual-port static random access memory.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
In a first embodiment, as shown in fig. 7, the dual port sram provided in the present invention includes:
a first end of a first MOS PG1 is used as a first A _ BL of the dual-port SRAM differential bit line A port, a second end of the first MOS PG1 is connected with a second end of a second MOS PU1, a third end of a third MOS PU2, a second end of a fifth MOS PG4, a second end of a sixth MOS PD1 and a third end of a seventh MOS PD2, and a third end of the first MOS PG1 is connected with a third end of a fourth MOS PG2 to be used as a dual-port SRAM word line A A _ WL;
the first end of the second MOS PU1 is connected with a power supply voltage Vdd, and the third end of the second MOS PU1 is connected with the second end of the third MOS PU2, the second end of the fourth MOS PG2, the third end of the sixth MOS PD1, the second end of the seventh MOS PD2 and the second end of the eighth MOS PG 3;
the first end of the third MOS PU2 is connected with a power supply voltage Vdd;
the first end of the fourth MOS PG2 is used as a second port A _ BLB of a dual-port SRAM differential bit line A;
a first end of the fifth MOS PG4 is used as a two-port sram differential bit line B port two B _ BLB, and a third end of the fifth MOS PG4 is connected to a third end of the eighth MOS PG3 and is used as the two-port sram word line B B _ WL;
the first end of the sixth MOS PD1 and the first end of the seventh MOS PD2 are connected to the ground;
the first end of the eighth MOS PG3 is used as a dual port sram differential bit line B port-B _ BL;
the widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, the widths of the first, second, third, sixth, seventh and eighth MOS active regions are the same, and the widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are greater than the widths of the first, second, third, sixth, seventh and eighth MOS active regions.
The second MOS PU1 and the third MOS PU2 are PMOS, and the first, second, third, sixth, seventh, and eighth MOS are NMOS.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the drawings. Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
In a second embodiment, as shown in fig. 8, the dual port sram provided in the present invention includes:
a first end of a first MOS PG1 is used as a first A _ BL of the dual-port SRAM differential bit line A port, a second end of the first MOS PG1 is connected with a second end of a second MOS PU1, a third end of a third MOS PU2, a second end of a fifth MOS PG4, a second end of a sixth MOS PD1 and a third end of a seventh MOS PD2, and a third end of the first MOS PG1 is connected with a third end of a fourth MOS PG2 to be used as a dual-port SRAM word line A A _ WL;
the first end of the second MOS PU1 is connected with a power supply voltage Vdd, and the third end of the second MOS PU1 is connected with the second end of the third MOS PU2, the second end of the fourth MOS PG2, the third end of the sixth MOS PD1, the second end of the seventh MOS PD2 and the second end of the eighth MOS PG 3;
the first end of the third MOS PU2 is connected with a power supply voltage Vdd;
the first end of the fourth MOS PG2 is used as a second port A _ BLB of a dual-port SRAM differential bit line A;
a first end of the fifth MOS PG4 is used as a two-port sram differential bit line B port two B _ BLB, and a third end of the fifth MOS PG4 is connected to a third end of the eighth MOS PG3 and is used as the two-port sram word line B B _ WL;
the first end of the sixth MOS PD1 and the first end of the seventh MOS PD2 are connected to the ground;
the first end of the eighth MOS PG3 is used as a dual port sram differential bit line B port-B _ BL;
the lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, the lengths of the first, second, third, sixth, seventh and eighth MOS active regions are the same, and the lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are smaller than the lengths of the first, second, third, sixth, seventh and eighth MOS active regions.
The second MOS PU1 and the third MOS PU2 are PMOS, and the first, second, third, sixth, seventh, and eighth MOS are NMOS.
In a third embodiment, as shown in fig. 9, the dual port sram provided in the present invention includes:
a first end of a first MOS PG1 is used as a first A _ BL of the dual-port SRAM differential bit line A port, a second end of the first MOS PG1 is connected with a second end of a second MOS PU1, a third end of a third MOS PU2, a second end of a fifth MOS PG4, a second end of a sixth MOS PD1 and a third end of a seventh MOS PD2, and a third end of the first MOS PG1 is connected with a third end of a fourth MOS PG2 to be used as a dual-port SRAM word line A A _ WL;
the first end of the second MOS PU1 is connected with a power supply voltage Vdd, and the third end of the second MOS PU1 is connected with the second end of the third MOS PU2, the second end of the fourth MOS PG2, the third end of the sixth MOS PD1, the second end of the seventh MOS PD2 and the second end of the eighth MOS PG 3;
the first end of the third MOS PU2 is connected with a power supply voltage Vdd;
the first end of the fourth MOS PG2 is used as a second port A _ BLB of a dual-port SRAM differential bit line A;
a first end of the fifth MOS PG4 is used as a two-port sram differential bit line B port two B _ BLB, and a third end of the fifth MOS PG4 is connected to a third end of the eighth MOS PG3 and is used as the two-port sram word line B B _ WL;
the first end of the sixth MOS PD1 and the first end of the seventh MOS PD2 are connected to the ground;
the first end of the eighth MOS PG3 is used as a dual port sram differential bit line B port-B _ BL;
the lengths and widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are the same, and the lengths and widths of the first, second, third, sixth, seventh and eighth MOS active regions are the same.
The widths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are greater than the widths of the first, second, third, sixth, seventh, and eighth MOS active regions, and the lengths of the active regions of the fourth MOS PG2 and the fifth MOS PG4 are less than the lengths of the first, second, third, sixth, seventh, and eighth MOS active regions.
The second MOS PU1 and the third MOS PU2 are PMOS, and the first, second, third, sixth, seventh, and eighth MOS are NMOS.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (8)

1. A dual port static random access memory comprising: a first end of a first MOS (PG1) is used as a first port (A _ BL) of the dual-port static random access memory differential bit line A, a second end of the first MOS (PG1) is connected with a second end of a second MOS (PU1), a third end of a third MOS (PU2), a second end of a fifth MOS (PG4), a second end of a sixth MOS (PD1) and a third end of a seventh MOS (PD2), and a third end of the first MOS (PG1) is connected with a third end of a fourth MOS (PG2) and used as a word line A (A _ WL) of the dual-port static random access memory;
a first end of the second MOS (PU1) is connected with the power supply voltage (Vdd), and a third end of the second MOS (PU1) is connected with a second end of the third MOS (PU2), a second end of the fourth MOS (PG2), a third end of the sixth MOS (PD1), a second end of the seventh MOS (PD2) and a second end of the eighth MOS (PG 3);
the first end of the third MOS (PU2) is connected with the power supply voltage (Vdd);
the first end of the fourth MOS (PG2) is used as a second port (A _ BLB) of a differential bit line A of the dual-port static random access memory;
a first end of a fifth MOS (PG4) is used as a second port (B _ BLB) of a differential bit line B of the dual-port static random access memory, and a third end of the fifth MOS (PG4) is connected with a third end of an eighth MOS (PG3) and is used as a word line B (B _ WL) of the dual-port static random access memory;
a sixth MOS (PD1) first terminal and a seventh MOS (PD2) first terminal are connected to ground;
the first end of the eighth MOS (PG3) is used as a first port (B _ BL) of a differential bit line B of the dual-port SRAM; the method is characterized in that:
the critical dimensions of the fourth MOS (PG2) and the fifth MOS (PG4) are different from the first, second, third, sixth, seventh, and eighth MOS.
2. The dual port sram of claim 1, wherein:
the widths of the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are greater than the widths of the active regions of the first, second, third, sixth, seventh, and eighth MOS.
3. The dual port sram of claim 2, wherein:
the widths of the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are the same, and the widths of the first, second, third, sixth, seventh, and eighth MOS active regions are the same.
4. The dual port sram of claim 1, wherein:
the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) have lengths less than the lengths of the first, second, third, sixth, seventh, and eighth MOS active regions.
5. The dual port sram of claim 4, wherein:
the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are the same in length, and the first, second, third, sixth, seventh, and eighth MOS active regions are the same in length.
6. The dual port sram of claim 1, wherein:
the widths of the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are greater than the widths of the active regions of the first, second, third, sixth, seventh and eighth MOS, and the lengths of the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are less than the lengths of the active regions of the first, second, third, sixth, seventh and eighth MOS.
7. The dual port sram of claim 6, wherein:
the lengths and widths of the active regions of the fourth MOS (PG2) and the fifth MOS (PG4) are the same, and the lengths and widths of the first, second, third, sixth, seventh, and eighth MOS active regions are the same.
8. A dual port sram as claimed in any one of claims 1-7, wherein:
the second MOS (PU1) and the third MOS (PU2) are PMOS, and the first, second, third, sixth, seventh, and eighth MOS are NMOS.
CN202010466157.9A 2020-05-28 2020-05-28 Dual port static random access memory Pending CN111554335A (en)

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