CN111524979A - Array substrate and display panel - Google Patents

Abstract

Array substrate and display panel, the array substrate includes a substrate, a pixel array, an insulating layer and a covering layer. The pixel array is located on the substrate. The pixel array includes a plurality of pixel structures, and each pixel structure includes a thin film transistor. An insulating layer is located on the thin film transistor. The covering layer is located on the insulating layer and contacts the insulating layer, wherein the difference between the refractive index of the covering layer and the refractive index of the insulating layer is between 0 and 0.1, and the light absorption coefficient of the covering layer is between 0 and 0.5.

Description

Array substrate and display panel

technical field

The present disclosure relates to an array substrate and a display panel.

Background technique

Thin film transistor displays are currently the mainstream in the market, such as well-known public information displays (PID) and 8K ultra-high definition (UHD) displays, which have the advantages of high brightness and high resolution. The thin film transistor display is composed of a thin film transistor array, a color filter array and a liquid crystal layer, and produces a display function with the help of a backlight source. The internal reflection of the insulating layer (gate insulating layer; GI layer), the diffraction generated by different interfaces and then hitting the channel layer in the thin film transistor array cause more and more serious leakage.

If a black photo spacer (BPS) is used to fabricate a thin film transistor array substrate (black matrix on array; BOA) to fabricate a display, the leakage can be reduced. Because the black photo spacer needs to use full tone and halftone masks to make the step difference like the transparent photo spacer (PS); however, the black photo spacer will be exposed during exposure. Because of its black color, the light cannot reach the bottom, resulting in uneven bottom cross-linking, resulting in poor uniformity and yield at the level difference of the black optical gap material, while the film thickness stability of the transparent gap material will be better; for example , when the size and exposure of the gap material are changed, the level difference of the black optical gap material will be much larger than that of the transparent gap material. In addition, when the display is repaired for defects, it is also difficult to detect residues on the channel layer due to the coverage of the black gap material, which further causes the problem of lowering the yield of the display.

SUMMARY OF THE INVENTION

The present disclosure provides a covering layer with high refractive index and low light absorption coefficient covering the thin film transistor, which can reduce the leakage of the thin film transistor, improve the uniformity of the step difference and improve the yield of the display.

The array substrate of the present invention includes a substrate, a pixel array, an insulating layer and a cover layer. The pixel array is located on the substrate, and the pixel array includes a plurality of pixel structures, and each pixel structure includes a thin film transistor. The insulating layer is on the thin film transistor. The cover layer is located on and in contact with the insulating layer, wherein the difference between the refractive index of the cover layer and the refractive index of the insulating layer is between 0 and 0.1, and the light absorption coefficient of the cover layer is between 0 and 0.5.

In an embodiment of the present invention, the above-mentioned thin film transistor includes a gate electrode, and the orthographic projection of the cover layer on the substrate overlaps the orthographic projection of the gate electrode on the substrate.

In an embodiment of the present invention, the refractive index of the above-mentioned insulating layer is 1.75, and the refractive index of the covering layer is between 1.65 and 1.85.

In an embodiment of the present invention, the above-mentioned cover layer is transparent or translucent.

In an embodiment of the present invention, the material of the above-mentioned cover layer is a transparent photo spacer (PS) or an ultra high aperture (UHA) insulating material, and its components include resin, photoresist starter, solvent, accelerator, curing accelerator and/or surfactant.

The display panel of the present invention includes an array substrate, an opposite substrate and a display medium layer. The opposite substrate and the array substrate are arranged opposite to each other, and the display medium layer is located between the opposite substrate and the array substrate. The pixel array is located on the substrate, wherein the pixel array includes a plurality of pixel structures, and each pixel structure includes a thin film transistor. The insulating layer is on the thin film transistor. The cover layer is located on and in contact with the insulating layer, wherein the difference between the refractive index of the cover layer and the refractive index of the insulating layer is between 0 and 0.1, and the light absorption coefficient of the cover layer is between 0 and 0.5.

In an embodiment of the present invention, the above-mentioned thin film transistor includes a gate, and the orthographic projection of the gate on the substrate overlaps the orthographic projection of the cover layer on the substrate.

In an embodiment of the present invention, the above-mentioned display panel further includes a common electrode. The common electrode is disposed on the opposite substrate, wherein the cover layer extends from the insulating layer toward the opposite substrate and contacts the common electrode, the insulating layer has a refractive index of 1.75, and the cover layer has a refractive index between 1.65 and 1.85.

In an embodiment of the present invention, the above-mentioned display panel further includes a green filter pattern, a blue filter pattern and a red filter pattern. The cover layer is located on the thin film transistor, the material of the cover layer is red color resist, at least one of the green filter pattern and the blue filter pattern is arranged adjacent to the cover layer, the refractive index of the insulating layer is 1.75, and the cover layer is The refractive index of the layers is between 1.65 and 1.85.

In an embodiment of the present invention, the above-mentioned display panel further includes a color filter element. The color filter element is disposed on the cover layer and contacts the cover layer, and the cover layer includes a translucent black optical gap material, the refractive index of the insulating layer is 1.75, and the refractive index of the cover layer is between 1.65 and 1.85.

Based on the above, in the array substrate and the display panel of the present disclosure, the difference between the refractive index of the transmission cover layer and the refractive index of the insulating layer is between 0 and 0.1. Since the difference between the refractive index of the cover layer and that of the insulating layer is extremely small, that is, the two can be regarded as the same medium, it can prevent the light from the backlight from occurring in the interface between the cover layer and the insulating layer. Therefore, the light absorption amount of the channel layer is reduced, thereby preventing the light leakage of the thin film transistor. Since the cover layer is transparent or semi-transparent, in the production process of the display panel, whether there is a thin residue on the channel layer can also be effectively detected, thereby improving the yield of the display panel.

Description of drawings

Various aspects of the present disclosure can be understood by reading the following detailed description in conjunction with the corresponding drawings. It should be noted that various features in the drawings are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the described features may be arbitrarily increased or decreased to facilitate clarity of discussion.

FIG. 1A is a partial top view of a display panel according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A.

FIG. 1C is a schematic diagram of a pixel array according to an embodiment of the present invention.

FIG. 1D is an enlarged schematic view of the region R of FIG. 1B .

2 to 5 are schematic cross-sectional views of a display panel according to another embodiment of the present invention.

Description of reference numbers:

10, 10a, 10b, 10c, 10d...display panel

100...Array substrate

102... Opposite substrate

104...Display medium layer

106, 106a, 106b, 106c, 106d... cover layer

108...Insulation layer

109...Insulation layer

110...Frame glue

111, 111c...color filter element

112A...Main spacer

112B...Secondary clearance

114A...Flat part

114B...Main spacer

114C...Secondary clearance

116...Passivation layer

118...Signal line

120...Conductor layer

122...Common electrode

124...passivation layer

AA...display area

AR...pixel array

BM...Black Matrix

C...contact window

CF1...Red filter pattern

CF2...Green filter pattern

CF3...Blue filter pattern

CH...channel layer

CL...Common line

D...Drain

DL... data cable

G...gate

GI...Gate Insulator

I-I'...section line

L1...path

L2...path

L3...path

P...pixel structure

PE...pixel electrode

PS1...main spacer

PS2...Secondary spacer

S...source

SB...Substrate

SL...scan line

T...thin film transistor

U...pixel unit

Detailed ways

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail as follows in conjunction with the accompanying drawings.

FIG. 1A is a partial top view of a display panel 10 according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A. FIG. 1C is a schematic diagram of a pixel array AR according to an embodiment of the present invention. 1A to FIG. 1C at the same time, the display panel 10 of the present embodiment has a display area AA and a peripheral area NA surrounding the display area AA.

In addition, in this embodiment, the display panel 10 includes an array substrate 100 , an opposite substrate 102 and a display medium layer 104 . The array substrate 100 includes a substrate SB, a pixel array AR, an insulating layer 108 and a cover layer 106 . The substrate SB and the counter substrate 102 are disposed opposite to each other. The material of the substrate SB and the opposite substrate 102 can be glass, quartz or organic polymer, respectively. The display medium layer 104 may be a liquid crystal layer, that is, in this embodiment, the display panel 10 is a liquid crystal display panel. For convenience of description, components such as the opposing substrate 102 and the display medium layer 104 are omitted in FIG. 1A .

The pixel array AR is located on the substrate SB and is located in the display area AA. The pixel array AR includes a plurality of scan lines SL, a plurality of data lines DL, a plurality of pixel structures P, and a plurality of common lines CL, and each pixel structure P is disposed corresponding to one pixel unit U. The scan lines SL and the data lines DL have different extending directions. In one embodiment, the extending direction of the scan lines SL is perpendicular to the extending direction of the data lines DL. In addition, the scan line SL and the data line DL are located in different film layers, and an insulating layer (not shown) is sandwiched between them. The scan line SL and the data line DL are mainly used to transmit driving signals for driving the pixel structure P.

Each pixel structure P is electrically connected to a corresponding scan line SL and a corresponding data line DL. In more detail, each pixel unit U is provided with a pixel structure P. According to this embodiment, the pixel structure P includes the thin film transistor T and the pixel electrode PE. The thin film transistor T is electrically connected to a corresponding scan line SL and a corresponding data line DL, and the pixel electrode PE is electrically connected to the thin film transistor T. In more detail, the thin film transistor T includes a gate G, a channel layer CH, a source S and a drain D. The gate G is electrically connected to a corresponding scan line SL. The channel layer CH is located above the gate G. The source electrode S and the drain electrode D are located above the channel layer CH, and the source electrode S is electrically connected to a corresponding data line DL. An insulating layer 109 is sandwiched between the drain electrode D, the source electrode S and the channel layer CH, respectively.

The common line CL is disposed on the substrate SB, and there are a plurality of gaps between the common line CL and the scan line SL, so the common line CL is not electrically connected to the scan line SL and the gate G. Further, in this embodiment, the common lines CL are electrically connected to each other and connected to the common voltage. In this embodiment, the gate G, the common line CL and the scan line SL of the thin film transistor T are formed together in the same process step, that is, the gate G, the common line CL and the scan line SL of the thin film transistor T belong to the same film. layer, with the same material. For example, the material of the gate G, the common line CL and the scan line SL is metal, and can be a single layer or a multi-layer. For example, the gate G, the common line CL and the scan line SL can be aluminum (Al), aluminum alloy (Al alloy), silver (Ag), silver alloy (Agalloy), copper (Cu), copper alloy (Cu alloy) ), molybdenum (Mo), molybdenum alloy (Mo alloy), chromium (Cr), titanium (Ti) and/or tantalum (Ta) as a single layer, or the gate G, the common line CL and the scan line SL can be are copper/molybdenum (Cu/Mo), aluminum/molybdenum (Al/Mo), aluminum/neodymium (Al/Nd), molybdenum/tungsten (Mo/W), molybdenum/copper/molybdenum (Mo/Cu/Mo), Multilayers composed of molybdenum/aluminum/molybdenum (Mo/Al/Mo), titanium/copper/titanium (Ti/Cu/Ti), and titanium/aluminum/titanium (Ti/Al/Ti). In this embodiment, the thicknesses of the gate G, the common line CL and the scan line SL are between 0.3 μm and 1 μm.

The material of the channel layer CH can be amorphous silicon (α-Si:H) semiconductor material, and the channel region and the source doped region and the drain doped region (not shown) at both ends of the channel region are defined by doping . In this embodiment, the source S, the drain D and the data line DL of the thin film transistor T are formed together in the same process step, that is, the source S, the drain D and the data line DL of the thin film transistor T belong to the same film. layer, with the same material. The material of the source electrode S, the drain electrode D and the data line DL is, for example, metal, and can be a single layer or multiple layers. For example, the source electrode S, the drain electrode D and the data line DL can be aluminum (Al), aluminum alloy (Al alloy), silver (Ag), silver alloy (Ag alloy), copper (Cu), copper alloy (Cu) Alloy), molybdenum (Mo), molybdenum alloy (Mo alloy), chromium (Cr), titanium (Ti) and/or tantalum (Ta) constitute a single layer, or, source S, drain D and data line DL Can be copper/molybdenum (Cu/Mo), aluminum/molybdenum (Al/Mo), molybdenum/copper/molybdenum (Mo/Cu/Mo), molybdenum/aluminum/molybdenum (Mo/Al/Mo), titanium/copper/ Multilayers composed of titanium (Ti/Cu/Ti) and titanium/aluminum/titanium (Ti/Al/Ti). In this embodiment, the thicknesses of the source electrode S, the drain electrode D and the data line DL are between 0.3 μm and 1 μm.

In this embodiment, the gate G of the thin film transistor T is further covered with a gate insulating layer GI. The material of the gate insulating layer GI is an inorganic material, such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), or a stacked layer of at least two of the above materials.

The insulating layer 108 is located on the thin film transistor T. Specifically, the insulating layer 108 is located on the source electrode S and the drain electrode D of the thin film transistor T. As shown in FIG. In this embodiment, the material of the insulating layer 108 is an inorganic material, such as silicon nitride (SiN _x ). The capping layer 106 is on the insulating layer 108 and contacts the insulating layer 108 . FIG. 1D is an enlarged schematic view of the region R of FIG. 1B . 1D, a part of the light will travel along the path L3. If the light is reflected at the interface between the cover layer 106 and the insulating layer 108, the light will also be totally internally reflected in the gate insulating layer GI along the path L1. (internal reflection), the total internal reflection light will be irradiated to the channel layer CH and absorbed by the channel layer CH. In this embodiment, the difference between the refractive index of the cover layer 106 and the refractive index of the insulating layer 108 is between 0 and 0.1. Since the difference between the refractive index of the cover layer 106 and the refractive index of the insulating layer 108 is extremely small, that is, the two can be regarded as the same medium, it can prevent the light from the backlight (not shown) from passing between the cover layer 106 and the insulating layer. The interface between the layers 108 undergoes internal reflection, thereby reducing the light absorption of the channel layer CH, thereby preventing the light leakage of the thin film transistor T (see FIG. 1C ). In one embodiment, the refractive index of the insulating layer 108 is 1.75, and the refractive index of the cover layer 106 is between 1.65 and 1.85.

The orthographic projection of the cover layer 106 on the substrate SB overlaps the orthographic projection of the gate G on the substrate SB. In this embodiment, the orthographic projection of the cover layer 106 on the substrate SB completely covers the orthographic projection of the gate G on the substrate SB, so that the light will not be diffracted along the path L2 and hit the channel layer CH, thereby avoiding The light is absorbed by the channel layer CH, thereby preventing light leakage of the thin film transistor T (see FIG. 1C ).

In this embodiment, the material of the cover layer 106 is, for example, an ultra high aperture (UHA) insulating material, which is a transparent organic photosensitive material and a high refractive index material, and the cover layer 106 is a positive photolithography material. glue. In this embodiment, the material composition of the cover layer 106 includes a resin, a photoactive compound (PAC), a solvent and an additive. The additive is, for example, a promoter and a curing accelerator. promoter) and/or surfactants. For example, the resin is, for example, acrylic resin, such as cresol novolak resin and a copolymer of 2-propenamide polymer with ethenylbenzene, and the photoactive compound is, for example, diazo Derivatives (naphthoquinone diazide derivative).

In this embodiment, the light absorption coefficient of the cover layer 106 is between 0 and 0.5. Since the light absorption coefficient is related to transparency, the cover layer 106 is transparent (ie, the light absorption coefficient is zero) or semi-transparent (ie, the light absorption coefficient is between 0 and 0.5). The cover layer 106 is formed by, for example, exposing, developing, and hard baking. Since the cover layer 106 is transparent or translucent, it can avoid the incomplete cross-linking at the bottom of the cover layer 106 during the exposure process compared to the black material, so that the cover layer 106 has good film thickness stability after the development and hard baking process. sex. In addition, since the cover layer 106 is transparent or semi-transparent, during the production process of the display panel 10 , whether there is a thin residue on the channel layer CH can be effectively detected, thereby improving the yield of the display panel 10 . In this embodiment, the thickness of the cover layer 106 is between 1 μm and 5 μm.

In addition, the pixel electrode PE is disposed on the cover layer 106 , and the contact window C is located in the cover layer 106 . The pixel electrode PE is electrically connected to the drain D of the thin film transistor T through the contact window C. The pixel electrode PE is, for example, a transparent pixel electrode, and its material includes a metal oxide, such as indium tin oxide (Indium Tin Oxide; ITO), indium zinc oxide (Indium Zinc Oxide; IZO) or other suitable oxides, or the above Stacked layers of at least both. In this embodiment, the thickness of the pixel electrode PE is between 0.04 μm and 0.2 μm.

The display panel 10 further includes a black matrix BM, a color filter element 111 , a common electrode 122 , a plurality of photo spacers PS1 , a plurality of sub spacers PS2 , a sealant 110 , a conductor layer 120 and a signal Line 118. The conductor layer 120 is connected to the signal line 118 . In this embodiment, the black matrix BM is disposed on the opposite substrate 102, the color filter element 111 is disposed on the black matrix BM, and the color filter element 111 includes, for example, a red filter pattern CF1, a green filter pattern CF2, and a blue filter. Filter pattern (not shown). Color Filter Elements The components of the color filter element 111 may include resins, monomers, pigments, dyes, photoinitiators, solvents and/or additives, such as promoters. ), curing promoter and/or surfactant. In this embodiment, the thickness of the color filter element 111 is between 2 μm and 4 μm. The common electrode 122 is disposed on the opposite substrate 102 . Specifically, the common electrode 122 is disposed on the black matrix BM and the color filter element 111 . The potential difference between the common electrode 122 and the pixel electrode PE can drive the display medium layer 104 , thereby enabling the display panel 10 to display a picture.

In some embodiments, the black matrix BM is located between the filter patterns of different colors. The components of the black matrix BM include resins, monomers, carbon, photoinitiators, solvents and/or additives, such as promoters, curing promoters and/or surfactants. In this embodiment, the thickness of the black matrix BM is between 1 μm and 3 μm. In this embodiment, the main spacer PS1 and the sub-spacer PS2 are disposed on the opposite substrate 102 . Specifically, the main spacer PS1 and the sub-spacer PS2 are disposed on the common electrode 122 to support the array substrate 100 and the opposite substrate 102 . toward the substrate 102 and form a cell gap. The height of the main spacer PS1 is greater than the height of the sub-spacer PS2, the main spacer PS1 extends from the common electrode 122 to the top surface of the contact cover layer 106, and the sub-spacer PS2 extends from the common electrode 122 and is separated from the cover layer 106 by a distance. distance. The primary spacer PS1 and the secondary spacer PS2 are organic photosensitive materials, and their components include resins, monomers, photoinitiators, solvents and/or additives, such as promoters, curing promoters and/or additives. / or surfactants. The sealant 110 is disposed between the opposite substrate 102 and the array substrate 100 and substantially surrounds the display medium layer 104 . The sealant 110 may have at least one opening (not marked) to serve as an injection port for the display medium layer 104 , but the invention is not limited thereto.

FIG. 2 is a schematic cross-sectional view of a display panel 10a according to another embodiment of the present invention. The main difference between the display panel 10a of FIG. 2 and the display panel 10 of FIG. 1B is that the cover layer 106a of the display panel 10a has a main spacer 112A and a sub spacer 112B, and the main spacer 112A and the sub spacer 112B are located on the substrate SB, The main spacer PS1 and the sub-spacer PS2 of the display panel 10 are located on the opposite substrate 102 , and the components similar to those in FIG. 1B are not repeatedly described herein.

Please refer to FIG. 2 , the material of the cover layer 106a is, for example, a photo spacer (PS), which is a transparent organic photosensitive material and a high refractive index material, and its components are resin, monomer, photoinitiator, Solvents and/or additives, such as promoters, curing promoters and/or surfactants. In this embodiment, the material of the cover layer 106a is negative photoresist. The main spacer 112A extends from the insulating layer 108 toward the opposite substrate 102 and contacts the common electrode 122 on the opposite substrate 102 , and the secondary spacer 112B extends from the insulating layer 108 toward the opposite substrate 102 and is separated from the common electrode 122 by a distance , the pixel electrode PE is separated by a distance from the main spacer 112A and the sub-spacer 112B respectively. In this embodiment, the main spacer 112A and the sub-spacer 112B can be used to support the array substrate 100 and the opposite substrate 102 and form a gap . The main spacer 112A and the secondary spacer 112B are fabricated using the same mask, which is a half tone mask. The light transmittance of the mask is related to the thickness of the photoresist after development and hard bake. For example, the light transmittance of the area of the mask corresponding to the main spacer 112A is 100%, and the light transmittance of the area of the mask corresponding to the secondary spacer 112B is 1% to 99%. Afterwards, the thickness of the main spacer 112A can be made larger than the thickness of the secondary spacer 112B.

FIG. 3 is a schematic cross-sectional view of a display panel 10b according to another embodiment of the present invention. The main difference between the display panel 10b of FIG. 3 and the display panel 10 of FIG. 1B is that the optical spacer (PS) of the display panel 10 (eg, the main spacer PS1 and the sub-spacer PS2 ) is made of a half-transmittance mask (half). tone mask), and the cover layer 106 of the display panel 10 is a full-film ultra-high aperture ratio (UHA) insulating material, the cover layer 106b of the display panel 10b further includes a flat portion 114A, and the optical spacer (PS) of the display panel 10b ) (eg the main spacer 114B, the sub-spacer 114C and the flat portion 114A) are prepared by a multi-tone mask, and the cover layer 106b of the display panel 10b is an ultra-high aperture ratio (UHA) insulating layer materials, wherein elements similar to those in FIG. 1B are not repeated here.

Referring to FIG. 3 , the material of the cover layer 106b is, for example, a multi-tone ultra high aperture insulating material prepared by a multi-transmittance mask, which is a transparent organic photosensitive material and a high refractive index material. The constituent components are resin, photoactive compound (PAC), solvent and additive, such as promoter, curing promoter and/or surfactant. In this embodiment, the material of the cover layer 106b is positive type photoresist. The main spacer 114B extends from the flat portion 114A toward the opposite substrate 102 and contacts the common electrode 122 on the opposite substrate 102 , and the secondary spacer 114C extends from the flat portion 114A toward the opposite substrate 102 and is separated from the common electrode 122 by a distance , the pixel electrode PE is separated by a distance from the main spacer 114B and the sub-spacer 114C, respectively. In this embodiment, the primary spacer 114B and the secondary spacer 114C can be used to support the array substrate 100 and the opposite substrate 102 and form a gap. The flat portion 114A, the primary spacer 114B and the secondary spacer 114C are fabricated using the same mask, for example, a so-called multi-tone mask. As mentioned earlier, the optical transmittance of the mask has a correlation with the thickness of the developed photoresist. For example, the light transmittance of the region of the mask corresponding to the flat portion 114A is 1% to 99%, the light transmittance of the region of the mask corresponding to the main spacer 114B is 0%, and the light transmittance of the mask corresponding to the main spacer 114B is 0%. The light transmittance in the region of the sub-spacer 114C is 1% to 99%, and the light transmittance of the region corresponding to the flat portion 114A of the mask is greater than that of the region corresponding to the sub-spacer 114C.

4 is a schematic cross-sectional view of a display panel 10c according to another embodiment of the present invention. The main difference between the display panel 10c of FIG. 4 and the display panel 10 of FIG. 1B is that the color filter elements 111c of the display panel 10c are located on the substrate SB to form a structure of a color filter layer on a pixel array (color filter on array), The cover layer 106c corresponds to a part of the red filter pattern and forms the color filter element 111c together with the green filter pattern CF2 and the blue filter pattern CF3, and the elements similar to those in FIG. 1B will not be repeated here.

Referring to FIG. 4 , the material of the cover layer 106c is, for example, an organic photosensitive material and a high refractive index material, such as a red color resist. For example, the cover layer 106c includes resin, monomer, photoinitiator, red pigment, solvent and/or additives, such as promoters, curing promoters and/or surfactants. The cover layer 106c, the green filter pattern CF2 and the blue filter pattern CF3 are provided corresponding to one pixel unit U, respectively. The channel layer CH of the thin film transistor T can absorb light with a wavelength between 380 nm and 580 nm. Since the wavelength of red light is outside this range, the light reflected in the cover layer 106c (ie, red light) hits the channel layer CH is also not absorbed by the channel layer CH. If the material of the cover layer 106c includes green color resist or blue color resist, since the wavelengths of blue light and green light are lower than 600 nm, in other words, the wavelengths of blue light and green light are in the range of wavelengths that can be absorbed by the channel layer CH, then The light reflected in the cover layer 106c (ie, blue light or green light) will be absorbed by the channel layer CH, resulting in light leakage of the thin film transistor T. In this embodiment, the display panel 10 c further includes a passivation layer 116 , the passivation layer 116 is located on the color filter element 111 c and the cover layer 106 c , and the pixel electrode PE is located on the passivation layer 116 . The common electrode 122 is disposed on the black matrix BM. In this embodiment, the primary spacer PS1 extends from the common electrode 122 to the top surface of the contact passivation layer 116 , and the secondary spacer PS2 extends from the common electrode 122 and is spaced apart from the passivation layer 116 by a distance.

FIG. 5 is a schematic cross-sectional view of a display panel 10d according to another embodiment of the present invention. The main difference between the display panel 10d of FIG. 5 and the display panel 10 of FIG. 1B is that the color filter elements 111 of the display panel 10d are disposed on the cover layer 106d, and the color filter elements 111 constitute a color filter layer on the pixel array ( color filter on array) structure. Elements similar to those in FIG. 1B are not repeated here. Referring to FIG. 5 , for example, the material of the cover layer 106d is, for example, an organic photosensitive material and a black photo spacer (BPS) material with a high refractive index. The components of the cover layer 106d include resin, monomer , a photoinitiator, an organic black pigment, a solvent and/or an additive, such as a promoter, a curing promoter and/or a surfactant. In this embodiment, the material of the cover layer 106d is negative photoresist. And the cover layer 106d is transparent or translucent. The display panel 10 d further includes a passivation layer 124 , the passivation layer 124 is located on the color filter element 111 , and the pixel electrode PE is located on the passivation layer 124 . The common electrode 122 is disposed on the black matrix BM. In this embodiment, the main spacer PS1 and the sub spacer PS2 are disposed on the passivation layer 124 , the main spacer PS1 extends from the passivation layer 124 to the top surface contacting the common electrode 122 , and the sub spacer PS2 is self-contained from the passivation layer 124 extends and is spaced apart from the common electrode 122 .

To sum up, in the array substrate and the display panel of the present disclosure, the difference between the refractive index of the transmission cover layer and the refractive index of the insulating layer is between 0 and 0.1. Since the difference between the refractive index of the cover layer and that of the insulating layer is extremely small, that is, the two can be regarded as the same medium, it can prevent the light from the backlight from occurring in the interface between the cover layer and the insulating layer. Therefore, the light absorption amount of the channel layer is reduced, thereby preventing the light leakage of the thin film transistor. The light absorption coefficient of the cover layer is between 0 and 0.5. Since the light absorption coefficient is related to transparency, the cover layer is transparent (ie, the light absorption coefficient is zero) or translucent (ie, the light absorption coefficient is between 0 and 0.5). The cover layer is formed by, for example, exposing, developing and hard-baking. Since the cover layer is transparent or semi-transparent, incomplete crosslinking can be avoided during the exposure process, the cover layer has good film thickness stability after developing and hard baking processes, and the yield of the cover layer is improved. Since the cover layer is transparent or semi-transparent, in the production process of the display panel, whether there is a thin residue on the channel layer can also be effectively detected, thereby improving the yield of the display panel.

Claims (10)

1. An array substrate, comprising: a substrate; a pixel array on the substrate, wherein the pixel array includes a plurality of pixel structures, and each pixel structure includes a thin film transistor; an insulating layer on the thin film transistor; and a cover layer on and in contact with the insulating layer, wherein the difference between the refractive index of the cover layer and the refractive index of the insulating layer is between 0 and 0.1, and the light absorption coefficient of the cover layer is Between 0 and 0.5. 2 . The array substrate of claim 1 , wherein the thin film transistor comprises a gate, and the orthographic projection of the cover layer on the substrate overlaps the orthographic projection of the gate on the substrate. 3 . 3 . The array substrate of claim 1 , wherein a refractive index of the insulating layer is 1.75, and a refractive index of the cover layer is between 1.65 and 1.85. 4 . 4. The array substrate of claim 1, wherein the cover layer is transparent or translucent. 5. The array substrate according to claim 1, wherein the material of the cover layer is a transparent optical spacer material or an insulating material with an ultra-high aperture ratio, and its components include resin, photoinitiator, solvent, accelerator, curing accelerator agents and/or surfactants. 6. A display panel comprising: An array substrate, comprising: a substrate; and a pixel array on the substrate, wherein the pixel array includes a plurality of pixel structures, and each pixel structure includes a thin film transistor; an insulating layer on the thin film transistor; and a cover layer, located on the insulating layer and in contact with the insulating layer, wherein the difference between the refractive index of the cover layer and the refractive index of the insulating layer is between 0 and 0.1, and the light absorption coefficient of the cover layer is between 0 and 0.1 between 0.5; a pair of facing substrates arranged opposite to the array substrate; and A display medium layer is located between the opposite substrate and the array substrate. 7 . The display panel of claim 6 , wherein the thin film transistor comprises a gate, and the orthographic projection of the gate on the substrate overlaps the orthographic projection of the cover layer on the substrate. 8 . 8. The display panel of claim 6, further comprising: a common electrode disposed on the opposite substrate, wherein the cover layer extends from the insulating layer toward the opposite substrate and contacts the common electrode, the insulating layer has a refractive index of 1.75, and the cover layer has a refractive index of 1.65 to 1.65 between 1.85. 9. The display panel of claim 6, further comprising: a green filter pattern; a blue filter pattern; and A red filter pattern, wherein the cover layer is located on the thin film transistor, the material of the cover layer is a red color resist, and at least one of the green filter pattern and the blue filter pattern is adjacent to the cover layer It is provided that the refractive index of the insulating layer is 1.75, and the refractive index of the covering layer is between 1.65 and 1.85. 10. The display panel of claim 6, further comprising: A color filter element is disposed on and in contact with the cover layer, the cover layer includes a translucent black optical gap material, the insulating layer has a refractive index of 1.75, and the cover layer has a refractive index of 1.65 to 1.85 between.

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