CN111506538A - Time slot splitting relay device for on-chip interconnection bus - Google Patents
Time slot splitting relay device for on-chip interconnection bus Download PDFInfo
- Publication number
- CN111506538A CN111506538A CN202010293897.7A CN202010293897A CN111506538A CN 111506538 A CN111506538 A CN 111506538A CN 202010293897 A CN202010293897 A CN 202010293897A CN 111506538 A CN111506538 A CN 111506538A
- Authority
- CN
- China
- Prior art keywords
- data
- bus
- arbitration
- time slot
- slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a time slot splitting relay device for an on-chip interconnection bus, which comprises an interface control module, a cache module, a bus control module and an internal bus, wherein the interface control module is used for controlling the interface control module; the control module is connected with an external bus, and the external bus comprises at least one group of arbitration bus and at least two groups of data buses. The control module compares the multilevel symbol of the relay equipment with the voltage of the arbitration bus, if the priority of the multilevel symbol is higher than the priority of the arbitration bus, the multilevel symbol is output to the arbitration bus, the relay equipment which sends the complete multilevel symbol string becomes a winner, and the winner sends the data to be sent to the data bus. By dividing the arbitration time slot and the data time slot, the arbitration process is carried out in the sub-time slot, and the data transmission is carried out in the sub-time slot or the time slot, so that the transmission efficiency of the data in a single time slot is improved. The relay equipment provided by the invention is easy to expand, the arbitration efficiency of the bus is high, and the data transmission rate of the bus is high.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a time slot splitting relay device for an on-chip interconnection bus.
Background
With the rapid development of the information industry, the single-core processor is not careful in the high-speed mass data transmission, and the limitation is exposed. Under the premise, the research on the multi-core processor is initiated for the first time from the Stanford university in 1996, and the research and development are carried out for more than 20 years. Multiple cores can be embedded in a single system on chip, 8 cores to 32 cores can be selected from the current AMD RTLONGELONGThreadIPER processor, and the number of cores in an Intel Xeon W processor can be as high as 28 cores. In the mobile phone industry closely related to the mass life, the number of processor cores of the new mobile phone is increased to 6-8 cores. Therefore, the multi-core technology meets the requirements of the public life on the electronic industry and integrates the trend of future technology development.
Multi-core technology is rapidly developing and has gained, but increasing the number of embedded cores is still limited by a number of factors, such as architecture, power consumption, operating system and balance design, etc. The internal structure is complicated due to the increase of modules on the CPU chip, and a high-efficiency on-chip bus is designed, so that the internal module structure of the CPU is optimized, and the performance resistance of the CPU caused by the complicated structure can be relieved.
On-chip bus systems come in a variety of forms, with star, ring and mesh bus architectures, respectively. The star-structure bus is applied to the connection of early CPU internal modules, the inner core is arranged in the center of the star-structure, and the contact hand extending outwards is connected with other modules except the inner core. The internal modules of the CPU are connected with the CPU, and are not connected with each other except the CPU. Although this architecture is simple and efficient, the star bus architecture is subject to distortion by the addition of cores. The cores divide and treat their respective modules, however, in order to be efficient, one core needs to be connected with the modules managed by the other cores, so that not only is the advantage of the bus structure lost, but also the number of wires of the system on chip is chaotic.
Instead of a star bus structure, a ring bus structure is used. The ring bus is characterized in that the kernel and the modules thereof are indiscriminately hung on the bus through two ring buses QPI and PCIe, the ring buses are convenient for information interaction among the modules, transfer from the kernel is not needed, and system delay is low. However, increasing the number of cores increases the overall ring of the ring bus, which increases latency and affects system performance, so the maximum number of buses that a ring bus can contain is limited to 12. And the system is used to process more than 12 cores by connecting a ring bus in parallel on the basis of the original ring bus. However, when the number of cores in the dual-ring bus system exceeds 24, the performance of the system is reduced by the ring bus processing, and the advantages of the ring bus structure are not guaranteed.
Disclosure of Invention
The invention aims to provide a time slot splitting relay device for an on-chip interconnection bus, which is easy to expand, high in bus arbitration efficiency and high in bus data transmission rate.
The invention discloses a time slot splitting relay device for an on-chip interconnection bus, which adopts the technical scheme that:
a time slot splitting relay device for an on-chip interconnection bus is characterized by comprising an interface control module, a cache module, a bus control module and an internal bus, wherein a plurality of node devices are hung under the internal bus;
the interface control module is respectively connected with the internal cache module and the external buses, and one external bus comprises at least one group of arbitration bus and at least two groups of data buses;
the data bus transmits data to be transmitted of the node equipment and the time slot splitting relay equipment through a data frame, the arbitration bus transmits a multilevel symbol string of the node equipment and the relay equipment through an arbitration frame, and the multilevel symbol comprises different voltage amplitude states separated by a plurality of thresholds;
the interface control module compares the multilevel symbol with the voltage on the arbitration bus, if the priority of the multilevel symbol is higher than the priority of the voltage on the arbitration bus, the multilevel symbol is output to the arbitration bus, the interface control module which sends the complete multilevel symbol string becomes a winner, and the winner sends the data to be sent to the data bus;
an interface control module which needs to send data to be sent sends a multilevel symbol string to the arbitration bus at the beginning of a time slot, wherein the time slot is a time interval required by the data bus for transmitting a data frame and the arbitration bus for transmitting an arbitration frame, one time slot of the data bus can be divided into at least two data sub-time slots, and one time slot of the arbitration bus can be divided into at least three arbitration sub-time slots;
the interface control module repeatedly sends a multilevel symbol string for contending for a data sub-slot or a data slot to the arbitration bus at the beginning of each arbitration sub-slot of a slot until the contention is won or the data bus is allocated,
if the data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to one group of data buses at the first data sub-time slot of the next time slot and the sending of the subsequent multilevel symbol string is stopped;
if the data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to the one group of data buses at the second data sub-time slot of the next time slot, and the subsequent multilevel symbol string is stopped being sent;
if the data to be sent only needs to be transmitted in one sub-slot and one data bus slot only comprises two data sub-slots, the data to be sent is sent to the other group of data buses at the first sub-slot of the next slot and the sending of the subsequent multi-system symbol strings is stopped, and if the data to be sent needs one complete slot to be transmitted and another group of idle data buses exist, the data to be sent is sent to the other group of idle data buses at the beginning of the next slot, and stopping sending the subsequent multi-system symbol strings, and repeating the steps until the data bus is distributed, and stopping sending the subsequent multi-system symbol strings by the interface control module until the time slot is finished.
The priority of the multilevel symbol string used in the arbitration sub-slot for the contention data sub-slot is higher than the priority of the multilevel symbol string used in the contention data sub-slot.
As a priority scheme, if the data to be transmitted in the sub-time slot cached by the cache module reaches a set value, the interface control module integrates the data to be transmitted in the sub-time slot into the data to be transmitted in the time slot.
As a priority scheme, if the number of times that the control module continuously and successfully sends the data to be sent reaches a set value, the control module reduces the probability of sending the multilevel symbol string.
As a priority scheme, the interface control module further comprises a connection to the group 2 arbitration bus, if one external bus further comprises another group arbitration bus, and the another group arbitration bus and the arbitration bus have the same slot length and arbitration sub-slot division, the another group arbitration bus and the slot of the arbitration bus have a fixed phase difference, one part of the multilevel symbol string is transmitted on the arbitration bus, and the other part is transmitted on the another group arbitration bus.
As a preferred scheme, the interface control module includes an arbitration circuit, the arbitration circuit includes a logic line or circuit, the logic line or circuit includes a field effect transistor and a first comparator, a drain of the field effect transistor serves as an input end of the logic line or circuit, a gate of the field effect transistor is connected with an output end of the first comparator, a source of the field effect transistor serves as an output end of the logic line or circuit, an inverting input end of the first comparator is connected with a source of the field effect transistor, a non-inverting input end of the first comparator is connected with a drain of the field effect transistor, if a drain voltage of the field effect transistor is higher than a source voltage of the field effect transistor, the first comparator outputs a high level to drive the field effect transistor to be turned on, the field effect transistor outputs an input multilevel symbol, otherwise, the first comparator outputs a low level, and the field effect transistor is turned.
As a preferred scheme, the logic line or circuit further includes a clearing circuit, the clearing circuit includes a current-limiting resistor and a switching tube, one end of the current-limiting resistor is connected with the logic line or output end, the other end of the current-limiting resistor is connected with the input end of the switching tube, the output end of the switching tube is grounded, the control end of the switching tube is connected with the device of the logic line or input end, and the device controls the switching tube to be turned on when the time slot is over.
As a preferred solution, the arbitration circuit further includes an error cancellation circuit, an input end of the error cancellation circuit is connected to the logical line or circuit output end, an output end of the error cancellation circuit is connected to a device at the logical line or circuit input end, and the error cancellation circuit includes:
a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish the different voltage amplitude states;
the regenerative circuit comprises a plurality of second comparators corresponding to a threshold voltage and a plurality of divider resistors, wherein the in-phase input end of each second comparator is connected with a logic line or an output end, the reverse phase input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltages to generate logic levels, and all the logic levels generate standard voltages corresponding to the multilevel symbols after being divided by the divider resistors;
the equipment compares the standard voltage output by the error elimination circuit with the multilevel symbol output by the error elimination circuit, and if the standard voltage and the multilevel symbol are consistent, the equipment successfully sends the multilevel symbol.
The embodiment disclosed by the invention has the beneficial effects that: the arbitration signal is transmitted by the arbitration bus, and the data to be sent is transmitted by the data bus, so that the data collision probability can be effectively reduced. The node equipment performs first competition in the relay equipment, the node equipment which successfully competes performs second competition on the bus through the relay equipment, and the relay equipment divides the arbitration signal into two times for competition, so that the number of the node equipment which participates in the competition at a single time is reduced, the collision probability of the node equipment is reduced, and meanwhile, part of wiring is reduced. The relay equipment is easy to expand, the relay equipment or the node equipment can be hung downwards, the access of more node equipment can be realized by continuously hanging the relay equipment in a grading mode, the data conflict probability is reduced, and the transmission efficiency is improved. Meanwhile, time slots are divided on the arbitration bus and the data bus to form sub-time slots, the priority of the multilevel symbol string transmitted by the competitive sub-time slots is higher than that of the multilevel symbol string transmitted by the competitive time slots, the condition that more data and less data to be sent in the system can be transmitted quickly is guaranteed, and the efficiency of data transmission is effectively guaranteed while the complexity of an algorithm is not increased. In addition, another group of arbitration buses can be added, the multi-system character codes of the node equipment are divided into two parts and transmitted on the two groups of arbitration buses simultaneously, and the arbitration efficiency is ensured, and meanwhile, the pressure of line data arbitration in the president is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a timeslot splitting repeater for an on-chip interconnect bus according to the present invention, in which only one arbitration bus and two data buses are provided.
Fig. 2 is a schematic diagram of the logic wired-or circuit of the slot split repeater device for on-chip interconnect bus of the present invention.
FIG. 3 is a schematic diagram of an arbitration circuit of a slot split repeater for an on-chip interconnect bus according to the present invention.
Fig. 4 is a schematic structural diagram of a timeslot splitting repeater for an on-chip interconnect bus according to the present invention, in which there are two data buses and two data buses.
Fig. 5 is a signal flow diagram of a slot split repeater device for an on-chip interconnect bus according to the present invention.
Detailed Description
The invention will be further elucidated and described with reference to the embodiments and drawings of the specification:
referring to fig. 1, the time for transmitting a complete data frame on the data bus is specified as a time slot, and the arbitration time slot and the data time slot have the same time length. One time slot of the data bus can be split into at least two data sub-time slots, one time slot of the arbitration bus can be split into at least three arbitration sub-time slots, and the number of the arbitration sub-time slots is not lower than the number of the data sub-time slots of one data bus and the number of the remaining data buses.
If the priority of the multilevel symbol of the interface control module is higher than the priority of the arbitration bus, the multilevel symbol is output to the arbitration bus, and meanwhile, the multilevel symbol is used for identifying whether the data to be sent compete for the data sub-slot or the complete data slot. If the interface control module which successfully sends the multilevel symbol string in the first arbitration sub-time slot needs to transmit the data to be sent in only one data sub-time slot, the interface control module starts to send the data to be sent to one group of data buses in the first data sub-time slot of the next time slot and stops sending the subsequent multilevel symbol string, and if the data to be sent needs a complete time slot to transmit, the interface control module starts to send the data to be sent to one group of data buses in the next time slot and stops sending the subsequent multilevel symbol string.
If the data to be transmitted only needs to be transmitted in one data sub-time slot, the data to be transmitted is transmitted to the one group of data buses at the second data sub-time slot of the next time slot, and the subsequent multilevel symbol string is stopped being transmitted.
If the data to be sent only needs to be transmitted in one sub-slot and one data bus slot only comprises two data sub-slots, the data to be sent is sent to the other group of data buses at the first sub-slot of the next slot and the sending of the subsequent multi-system symbol strings is stopped, and if the data to be sent needs one complete slot to be transmitted and another group of idle data buses exist, the data to be sent is sent to the other group of idle data buses at the beginning of the next slot, and stops transmitting subsequent multilevel symbol strings.
And repeating the steps until the data bus is distributed, and stopping sending the subsequent multi-system symbol strings by the interface control module until the time slot is finished.
The priority of the multilevel symbol string used in the arbitration sub-slot for the contention data sub-slot is higher than the priority of the multilevel symbol string used in the contention data sub-slot, so that the data bus and the data sub-slot are selected directly according to the first sub-slot and the second sub-slot of the first group of data bus until the last sub-slot; the first sub-time slot, the second time slot and the like of the second group of data buses or the sequence of the whole time slot are carried out, and the data to be sent which needs to be transmitted in the whole time slot is carried out after the data to be sent which only needs to be transmitted in the sub-time slot in the time slot is transmitted.
In another embodiment, the priority of the contention slot or the sub-slot is not identified in the multilevel symbol string, and the number of the remaining sub-slots and the number of idle data buses in the system need to be monitored in real time. If the interface control module which is successful in sending the multilevel symbol string in the first arbitration sub-time slot needs to transmit the data to be sent in only one data sub-time slot, the interface control module starts to send the data to be sent to one group of data buses in the first data sub-time slot of the next time slot and stops sending the subsequent multilevel symbol string, and if the data to be sent needs a complete time slot to transmit, the interface control module sends the data to be sent to one group of data buses in the start of the next time slot and stops sending the subsequent multilevel symbol string.
If the first sub-time slot of one group of data buses of the data buses is occupied, if the data to be sent needs to be transmitted in one data sub-time slot, the data to be sent starts to be sent to one group of data buses in the second data sub-time slot of the next time slot, and the sending of the subsequent multi-system symbol strings is stopped, and if the data to be sent needs a complete time slot for transmission, the data to be sent starts to be sent to the other group of idle data buses in the next time slot, and the sending of the subsequent multi-system symbol strings is stopped. If the whole time slot of one group of data buses is occupied, if the data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to the other group of data buses at the first data sub-time slot of the next time slot, and the sending of the subsequent multi-system symbol string is stopped.
If the data to be sent only needs to be transmitted in one sub-slot and one data bus slot only comprises two data sub-slots, the data to be sent is started to be sent to the other group of data bus in the first sub-slot of the next slot, and the subsequent multi-system symbol string is stopped to be sent; if all the time slots of a group of data buses of the data buses are occupied, if the data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to the group of data buses at the second data sub-time slot of the next time slot, and the sending of the subsequent multilevel symbol string is stopped; if all time slots of a group of data buses of the data buses and a first sub-time slot of a second group of data buses are occupied, if data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to the second group of data buses at the second data sub-time slot of the next time slot, and sending of subsequent multilevel symbol strings is stopped; if all time slots of one group of data buses of the data buses and all time slots of the second group of data buses are occupied, as long as the system has a third group of idle data buses, no matter the data buses occupy the sub-time slot transmission or the whole time slot transmission, data transmission is carried out on the third group of data buses, if no third group of data buses exists, the sending of the binary symbol string is stopped, and the next time slot is waited to participate in the competition again.
In the second data transmission process, the remaining conditions of each data bus and the sub-time slots on each bus are monitored in real time, and the transmission bus and the transmission sub-time slots occupied by the data to be sent are dynamically adjusted, so that a complex algorithm is required. Most of the data transmitted in the timeslot splitting relay device is data frames with a small data amount, so the transmission mode that the transmission of the first specified sub-timeslot is higher than the transmission priority of the timeslot does not reduce the efficiency of data transmission, and only needs to scan the occupation conditions of the data line sub-timeslots in sequence in a single timeslot and select the data bus and the sub-timeslots to transmit in sequence.
When the node device and the cache module of the timeslot split relay device have data to perform data transmission on the sub-bus, the contention mechanism for data transmission is consistent with the contention mechanism for data transmission on the system bus by the timeslot split relay device because the functions of the self-bus and the system bus are consistent, and thus, details are not repeated here.
Furthermore, each node device connected with the relay device has a preset priority code, the priority code is represented by a multilevel symbol string, and the multilevel symbol is translated into multilevel through a digital-to-analog converter and then participates in arbitration competition. The multi-system symbol comprises a time slot identifier, a device identifier and a relay device identifier, wherein the time slot identifier represents the time slot type of the data to be transmitted in the data bus, the device identifier represents a target node device of the data to be transmitted, and the relay device identifier represents a relay device connected with the target node device.
And if the identifier of the relay equipment is consistent with the identifier of the relay equipment and indicates that the target node equipment is connected with the relay equipment, sending the data to be sent to the target node equipment through an internal bus of the relay equipment. If the identifier of the relay equipment is inconsistent with the identifier of the relay equipment, the target node equipment is not connected with the relay equipment, the bus control module receives and stores the data to be sent in the cache module, and then the interface control module carries out secondary system to carry out data transmission.
When the node equipment performs the first competition in the relay equipment, if the first competition is successful, the relay equipment caches the input multilevel symbol string and the data to be sent, and performs the second competition on the system bus. And if the second competition is successful, sending the data to be sent to the system bus, and continuing to perform the next competition by other node equipment connected with the relay equipment. If the second competition fails, the data to be sent is cached continuously, competition continues on the system bus, and other node devices connected with the relay device stop competition until the relay device successfully competes, and the data to be sent is sent out. The relay device divides the arbitration signal into two times for competition, and when the second competition fails, the first competition of other node devices is stopped, so that the sending times of the arbitration signal are reduced, and the energy loss is reduced.
As a priority scheme, if the data to be transmitted in the sub-time slot stored in the cache module reaches a set value, the interface control module integrates the data to be transmitted in the sub-time slot into the data to be transmitted in the time slot. When the relay equipment transmits the data to be sent to the external bus, if the sending fails, the data to be sent is cached in the cache module. If the buffered data to be transmitted is transmitted in the sub-slots and the total length of the buffered data to be transmitted reaches a certain proportion of the length of the slot, for example, a half proportion, the control module integrates the buffered data to be transmitted in the sub-slots into the data to be transmitted in the slot. After the integration, the times of sending data to the system bus by the relay equipment can be reduced, and the data transmission efficiency is improved.
As a preferred scheme, the number of times that the interface control module successfully sends the data to be sent continuously reaches a set value, that is, the interface control module always occupies the system bus, and at this time, other relay devices that do not successfully send the data to be sent always queue up. In order to ensure that the queued relay device has an opportunity to send data to be sent, the control module delays for a set time and then sends the multilevel symbol string. Alternatively, the interface control module may also reduce the frequency or probability of transmitting the multilevel symbol string, for example, by ten percent, or stop transmitting once every several times of successful transmission. In short, the number of times of sending the multilevel symbol string by the control module can be reduced.
The above-mentioned manner of transmitting the multilevel symbol string by using the arbitration sub-slot can be replaced by a manner of controlling the number of the transmitted multilevel symbol strings in a single time slot, that is, the number of the arbitration sub-slot and the number of the multilevel symbol strings are completely consistent concepts, and both are used for competing the data sub-slot and the time slot.
As a priority scheme, referring to fig. 4, the slot split repeater device further includes another set of arbitration buses. The other group of arbitration buses are connected with the interface control module, the other group of arbitration buses and the arbitration buses have the same time slot length and time slot division, and the other group of arbitration buses and the arbitration buses have fixed phase difference. One part of the multilevel symbol string of the relay device is transmitted on the arbitration bus, and the other part of the multilevel symbol string of the relay device is transmitted on the other group of arbitration buses. The time slots of the two groups of arbitration buses have fixed phase difference, usually the phase difference is between (0 degrees and 180 degrees), the phase difference between the arbitration buses is used for identifying the precedence order of the multilevel symbol strings transmitted on the arbitration buses, namely, the arbitration bus with the phase leading transmits part of the multilevel symbol strings, and the arbitration bus with the phase lagging transmits the other part of the multilevel symbol strings. On the other hand, in order to ensure that the sequence of the two groups of arbitration buses can be accurately identified, the phase difference of the two groups of arbitration buses is between (60 degrees and 120 degrees).
In order to ensure the efficiency of data transmission, the number of the arbitration sub-time slots is at least not less than the number of the sub-time slots in a single data bus and the number of the remaining data buses, and in order to relieve the arbitration pressure of a single group of arbitration buses, the multi-system symbol strings of the relay equipment are divided into two parts to be transmitted in two groups of arbitration buses. Therefore, when the system requires a higher transmission speed and finer data sub-slot division, the difficulty of managing the arbitration slots in the slots is increased, and the arbitration pressure can be relieved and the accuracy of the arbitration data can be ensured when multiple groups of arbitration buses transmit the multi-system symbol strings in parallel.
Further, referring to fig. 2, the interface control module includes an arbitration circuit, the arbitration circuit includes a logic line or circuit, the logic line or circuit includes a field effect transistor and a first comparator, a drain of the field effect transistor is used as an input end of the logic line or circuit, a gate of the field effect transistor is connected to an output end of the first comparator, a source of the field effect transistor is used as an output end of the logic line or circuit, an inverting input end of the first comparator is connected to a source of the field effect transistor, and a non-inverting input end of the first comparator is connected to a drain of the field effect transistor.
If the voltage of the input end of the logic wired-OR circuit is higher than the voltage of the output end of the logic wired-OR circuit, namely the voltage of the in-phase input end of the first comparator is higher than the voltage of the reverse phase input end of the first comparator, the first comparator outputs high level to drive the field effect tube to be conducted, the conducting voltage of the field effect tube is reduced because the field effect tube is used as a switch, the voltage of the output end of the field effect tube is clamped to be slightly smaller than the voltage of the input end of the field effect tube, the field effect tube is equivalent to the field effect tube, the input multi-system.
The logic wired-OR circuit further comprises an input buffer, and the output end of the input buffer is connected with the input end of the field effect tube.
The logic line or circuit further comprises a clearing circuit, the clearing circuit comprises a pull-down resistor and a switch tube, one end of the pull-down resistor is connected with the logic line or the output end, the other end of the pull-down resistor is connected with the input end of the switch tube, the output end of the switch tube is grounded, the control end of the switch tube is connected with the logic line or circuit input end, and the switch tube is controlled to be switched on when the time slot is finished. The parasitic capacitance exists in the lead in a high-frequency state, which can affect the multilevel symbol output by the logic line or the circuit, and the parasitic capacitance is introduced to the conducting switch tube to eliminate the grounding at the end of the time slot, so that the influence of the parasitic capacitance can be avoided at the beginning of the next time slot, namely the output of the next multilevel symbol. Normally, a field effect transistor is selected as the switching transistor.
Further, the arbitration circuit further comprises an error elimination circuit, an input end of the error elimination circuit is connected with the logic line or the circuit output end, an output end of the error elimination circuit is connected with the logic line or the circuit input end, and the error elimination circuit comprises:
a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish states of the different voltage amplitudes;
the regenerative circuit comprises a plurality of second comparators corresponding to the threshold voltage and a plurality of divider resistors, wherein the in-phase input end of each second comparator is connected with the arbitration bus, the reverse phase input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltages to generate logic levels, all the logic levels are divided by the divider resistors to generate standard voltages corresponding to the multilevel symbols, the standard voltages output by the error elimination circuit are compared with the multilevel symbols output by the logic line or circuit input end equipment, and if the two standard voltages are consistent, the equipment successfully sends the multilevel symbols.
And the zero-gain operational amplifier is used for buffering the standard voltage and outputting the standard voltage.
The control module compares the multilevel symbol with a voltage on the arbitration bus, has priority if the voltage value of the multilevel symbol is higher than the voltage on the arbitration bus, and outputs the multilevel symbol to the arbitration bus. The characteristic is called 'OR' function, namely, the function is equivalent to logic 'OR' operation, the output end automatically selects the multilevel symbol with large voltage value for output, and collision detection is not needed. Node equipment which usually participates in arbitration outputs a multilevel symbol string, the multilevel symbol strings are compared bit by bit, multilevel symbols with priorities are output, next-bit multilevel symbols are continuously sent, equipment which completely sends a multilevel symbol string sequence can obtain arbitration priority, and data to be sent is sent to relay equipment.
In the invention, the multi-system symbol string is adopted to transmit the arbitration signal, compared with the binary symbol to transmit the arbitration signal, more information can be transmitted in the same time, and the arbitration efficiency is greatly improved. The specific implementation process is as follows:
referring to fig. 3, it is assumed that three relay devices participate in the priority arbitration.
There are correspondingly three logic wired-or circuits 100 and three error cancellation circuits 200. The output of the logical wired-or circuit 100 is connected to the input of the error cancellation circuit 200, and the output of the error cancellation circuit 200 is connected to the device at the input of the logical wired-or circuit 100.
Since the three error elimination circuits have the same structure, only three logic wired-OR circuits and one error elimination circuit are included in FIG. 3 for convenience of description.
The circuit is explained by a 5V logic system, and the multilevel symbol comprises five states, wherein the level 0 is defined to be lower than 1V, and the standard voltage is 0.5V; the level 1 is between 1.1V and 1.9V, and the standard voltage is 1.5V; the level 2 is between 2.1V and 2.9V, and the standard voltage is 2.5V; the level 3 is between 3.1V and 3.9V, and the standard voltage is 3.5V; the voltage of 4.1V or more is level 4, and the standard voltage thereof is 4.5V. Other voltage values are level transition voltages, requiring the nearest level to be rounded up. When all input ports are not switched in and assume a high impedance state, a level 0 is output by default.
The circuit of this embodiment can be used for arbitration signaling of the penta symbol. Level 0 represents the symbol "0", level 1 represents the symbol "1", and so on.
As can be seen from the above, the multilevel symbol includes four threshold voltages, which are 1V, 2V, 3V and 4V respectively. Correspondingly, the threshold circuit comprises 5 resistors connected in series, each resistor is divided into 1V voltage, and the corresponding threshold voltages are respectively 4V, 3V, 2V and 1V and respectively correspond to nodes 10-13 in FIG. 3.
Correspondingly, the regeneration circuit comprises 4 second comparators and 4 divider resistors, the non-inverting input end of each second comparator is connected with the same multi-system symbol input, the inverting input end of each second comparator is connected with different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, and the divider resistors are connected in parallel. When the voltage of the non-inverting input terminal of the second comparator is larger than that of the inverting input terminal, the second comparator outputs a logic high level, otherwise, the second comparator outputs a logic low level. And the logic high level or the logic low level output by all the second comparators generates standard voltage corresponding to the multilevel symbol after being subjected to voltage division by the voltage division resistors.
It can be known from the circuit of the embodiment that, when deriving the arbitration signal transmission circuit of other multilevel symbol strings, only the number of the threshold voltages needs to be changed, and the corresponding number change is performed on the comparators and the divider resistors.
In this embodiment, for convenience of understanding, the high level and the low level output by the comparator are 4.5V and 0.5V, and the resistance values of the voltage dividing resistors connected in series with the output end of the comparator are all equal to each other, so that the resistance value is R. It should be noted that, in practice, the high level amplitude, the low level amplitude and the resistance of the divider resistor output by the comparator can be calculated according to the required result.
Assume that node 1 inputs level 3, the reference voltage is 3.5V, node 2 inputs level 2, the reference voltage is 2.5V, and node 3 inputs level 1, and the reference voltage is 1.5V.
From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 3.5V. I.e. output level 3.
Since 3.5V is only less than the threshold voltage of 4V, node 6 outputs 0.5V low and nodes 7, 8 and 9 all output 4.5V high. The voltage of the output out at this time is:
exactly the standard voltage for level 3. The node controller compares the standard voltage output by the error elimination circuit with the input level, and finally judges that the standard voltage is consistent with the input level of the node 1, and the equipment connected with the node 1 obtains arbitration priority.
Assuming that the first bit level is inputted, the node 1 is inputted with the level 2, the standard voltage is 2.5V, the node 2 is inputted with the level 2, the standard voltage is 2.5V, the node 3 is inputted with the level 1, and the standard voltage is 1.5V. Assume that the level is disturbed during transmission and becomes 2.7V at node 1, 2.2V at node 2 and 1.3V at node 3.
From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 2.7V. Since 2.7V is greater than 2V and less than 3V, nodes 9 and 8 output 4.5V high and nodes 6 and 7 both output 0.5V low. The voltage of the output out at this time is:
exactly the standard voltage for level 2.
When the second bit level is input, the node 1 inputs the level 4, the standard voltage is 4.5V, the node 2 inputs the level 2, the standard voltage is 2.5V, the node 3 inputs the level 3, and the standard voltage is 3.5V. From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly less than 4.5V. Assuming interference during transmission, 4.5V becomes 4.8V.
Since 4.8V is greater than all threshold voltages, nodes 9, 8, 7 and 6 all output a high level of 4.5V. The voltage of the output out at this time is 4.5V, which is exactly the standard voltage corresponding to level 4. The node controller compares the standard voltage output by the error elimination circuit with the input level, when the first bit level comparison is carried out, the node 1 and the node 2 are consistent with the input level, the second bit level comparison is continued, only the node 1 is consistent with the input level, finally, the level consistent with the input level of the node 1 is judged, and the equipment connected with the node 1 obtains arbitration priority.
According to the above, the logic line or circuit can select the multilevel symbol with the highest output voltage value, the multilevel symbol generates a plurality of logic levels after passing through the regeneration circuit, and the plurality of logic levels generate the standard voltage corresponding to the multilevel symbol through the divider resistor, namely the multilevel symbol, so that the accuracy of the logic judgment of the digital circuit is ensured, and meanwhile, the on-state voltage of the logic line or circuit is reduced, and more levels in different states can be divided under the same voltage amplitude. The multi-system symbol is compared with the threshold voltage to generate a logic level, and the transmission noise and the error of the multi-system symbol are eliminated firstly. Further, since the multilevel symbol is compared with the threshold voltage, the generated logic level carries the information and characteristics of the multilevel symbol, and the logic level is converted into the standard voltage corresponding to the multilevel symbol according to the information and characteristics. As can be seen from the conventional knowledge, the more levels are divided within the same voltage amplitude, the smaller the voltage difference between the levels of the adjacent states is, which easily causes the logic judgment of the digital circuit to be misplaced. The circuit uses multilevel to represent the multilevel symbol, and simultaneously eliminates the transmission error of the multilevel symbol through the error regeneration circuit, thereby improving the accuracy of the judgment of the state of the multilevel symbol.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (7)
1. A time slot splitting relay device for an on-chip interconnection bus is characterized by comprising an interface control module, a cache module, a bus control module and an internal bus, wherein a plurality of node devices are hung under the internal bus;
the interface control module is respectively connected with the internal cache module and the external buses, and one external bus comprises at least one group of arbitration bus and at least two groups of data buses;
the data bus transmits data to be transmitted of the node equipment and the time slot splitting relay equipment through a data frame, the arbitration bus transmits a multilevel symbol string of the node equipment and the relay equipment through an arbitration frame, and the multilevel symbol comprises different voltage amplitude states separated by a plurality of thresholds;
the interface control module compares the multilevel symbol with the voltage on the arbitration bus, if the priority of the multilevel symbol is higher than the priority of the voltage on the arbitration bus, the multilevel symbol is output to the arbitration bus, the interface control module which sends the complete multilevel symbol string becomes a winner, and the winner sends the data to be sent to the data bus;
an interface control module which needs to send data to be sent sends a multilevel symbol string to the arbitration bus at the beginning of a time slot, wherein the time slot is a time interval required by the data bus for transmitting a data frame and the arbitration bus for transmitting an arbitration frame, one time slot of the data bus can be divided into at least two data sub-time slots, and one time slot of the arbitration bus can be divided into at least three arbitration sub-time slots;
the interface control module repeatedly sends a multilevel symbol string for competing the data sub-time slot or the data time slot to the arbitration bus at the beginning of each arbitration sub-time slot of one time slot until the data bus is completely distributed or wins in competition;
if the data to be sent only needs to be transmitted in one data sub-time slot, the data to be sent is sent to one group of data buses at the first data sub-time slot of the next time slot and the sending of the subsequent multilevel symbol string is stopped;
if the data to be sent of the interface control module which becomes a winner in the second arbitration sub-time slot only needs to be transmitted in one data sub-time slot, the interface control module starts to send the data to be sent to the one group of data buses in the second data sub-time slot of the next time slot and stops sending the subsequent multilevel symbol strings, and if the data to be sent needs a complete time slot to be transmitted, the interface control module starts to send the data to be sent to the other group of idle data buses in the next time slot and stops sending the subsequent multilevel symbol strings;
if the data to be sent only needs to be transmitted in one sub-slot and one data bus slot only comprises two data sub-slots, the data to be sent is sent to the other group of data buses at the first sub-slot of the next slot and the sending of the subsequent multi-system symbol strings is stopped, and if the data to be sent needs one complete slot to be transmitted and another group of idle data buses exist, the data to be sent is sent to the other group of idle data buses at the beginning of the next slot, and stopping sending the subsequent multi-system symbol strings;
repeating the steps until the data bus is distributed, and stopping sending the subsequent multi-system symbol strings by the interface control module until the time slot is finished;
the priority of the multilevel symbol string used in the arbitration sub-slot for the contention data sub-slot is higher than the priority of the multilevel symbol string used in the contention data sub-slot.
2. The slot splitting relay device for an on-chip interconnect bus as claimed in claim 1, wherein if the data to be transmitted in the sub-slots cached by the cache module reaches a set value, the interface control module integrates the data to be transmitted in the sub-slots into the data to be transmitted in the slots.
3. The slot splitting relay device for an on-chip interconnect bus as claimed in claim 1, wherein the interface control module having the data to be transmitted transmits the multilevel symbol string to the arbitration bus with a certain probability, and if the number of times of the control module continuously and successfully transmitting the data to be transmitted reaches a set value, the control module reduces the probability of transmitting the multilevel symbol string.
4. The slot split repeater device for on-chip interconnect buses as claimed in claim 1, wherein the interface control module further comprises a connection to the 2 nd group of arbitration buses, if one of the external buses further comprises another group of arbitration buses having the same slot length and arbitration sub-slot division as the arbitration buses, the another group of arbitration buses having a fixed phase difference from the slots of the arbitration buses, one part of the multilevel symbol string being transmitted on the arbitration bus and the other part being transmitted on the another group of arbitration bus.
5. The slot splitting repeater device for an on-chip interconnect bus according to claim 1, wherein the interface control module comprises an arbitration circuit, the arbitration circuit comprises a logic wired-OR circuit, the logic wired-OR circuit comprises a field effect transistor and a first comparator, the drain of the field effect transistor serves as the input end of the logic wired-OR circuit, the gate of the field effect transistor is connected with the output end of the first comparator, the source of the field effect transistor serves as the output end of the logic wired-OR circuit, the inverting input end of the first comparator is connected with the source of the field effect transistor, the non-inverting input end of the first comparator is connected with the drain of the field effect transistor, if the voltage of the drain of the field effect transistor is higher than the voltage of the source of the field effect transistor, the first comparator outputs a high level to drive the field effect transistor to be turned on, and the field effect transistor outputs an input, otherwise, the first comparator outputs low level, and the field effect tube is cut off.
6. The slot splitting repeater device for an on-chip interconnect bus of claim 5, wherein the logic wire or circuit further comprises a clearing circuit, the clearing circuit comprises a current limiting resistor and a switch tube, one end of the current limiting resistor is connected with the logic wire or output end, the other end of the current limiting resistor is connected with the input end of the switch tube, the output end of the switch tube is grounded, the control end of the switch tube is connected with a device of the logic wire or input end, and the device controls the switch tube to be turned on at the end of a slot.
7. The slot split repeater device for an on-die interconnect bus of claim 5, wherein the arbitration circuit further comprises an error cancellation circuit, an error cancellation circuit input connected to the logical wired-OR circuit output, an error cancellation circuit output connected to the device at the logical wired-OR circuit input, the error cancellation circuit comprising:
a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish the different voltage amplitude states;
the regenerative circuit comprises a plurality of second comparators corresponding to a threshold voltage and a plurality of divider resistors, wherein the in-phase input end of each second comparator is connected with a logic line or an output end, the reverse phase input end of each second comparator is used for inputting different threshold voltages, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, the second comparators compare the multilevel symbols with the threshold voltages to generate logic levels, and all the logic levels generate standard voltages corresponding to the multilevel symbols after being divided by the divider resistors;
the equipment compares the standard voltage output by the error elimination circuit with the multilevel symbol output by the error elimination circuit, and if the standard voltage and the multilevel symbol are consistent, the equipment successfully sends the multilevel symbol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010293897.7A CN111506538A (en) | 2020-04-15 | 2020-04-15 | Time slot splitting relay device for on-chip interconnection bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010293897.7A CN111506538A (en) | 2020-04-15 | 2020-04-15 | Time slot splitting relay device for on-chip interconnection bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111506538A true CN111506538A (en) | 2020-08-07 |
Family
ID=71869236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010293897.7A Pending CN111506538A (en) | 2020-04-15 | 2020-04-15 | Time slot splitting relay device for on-chip interconnection bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111506538A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506824A (en) * | 2020-12-17 | 2021-03-16 | 上海燧原智能科技有限公司 | Chip and data interaction method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124983A (en) * | 1989-06-19 | 1992-06-23 | Alcatel Business Systems | Arbitration method and device for transmit mode access to the transmission medium of a distributed switching network |
| WO1997048249A1 (en) * | 1996-06-07 | 1997-12-18 | Nokia Telecommunications Oy | Channel allocation method for a packet network |
| EP1037150A2 (en) * | 1999-03-17 | 2000-09-20 | Robert Bosch Gmbh | Method for managing access to a bus and bus system |
| JP2006251875A (en) * | 2005-03-08 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Bus arbitration device and bus arbitration method |
| CN101454763A (en) * | 2006-05-24 | 2009-06-10 | 罗伯特.博世有限公司 | Gateway for data transfer between serial buses |
| US20100014427A1 (en) * | 2008-07-18 | 2010-01-21 | Sun Microsystems, Inc. | Arbitration scheme for an optical bus |
| CN103218331B (en) * | 2012-12-07 | 2015-11-11 | 浙江大学 | Synchronous mode is adopted to switch and the self-adjusting bus unit of frame priority and method |
-
2020
- 2020-04-15 CN CN202010293897.7A patent/CN111506538A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124983A (en) * | 1989-06-19 | 1992-06-23 | Alcatel Business Systems | Arbitration method and device for transmit mode access to the transmission medium of a distributed switching network |
| WO1997048249A1 (en) * | 1996-06-07 | 1997-12-18 | Nokia Telecommunications Oy | Channel allocation method for a packet network |
| EP1037150A2 (en) * | 1999-03-17 | 2000-09-20 | Robert Bosch Gmbh | Method for managing access to a bus and bus system |
| JP2006251875A (en) * | 2005-03-08 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Bus arbitration device and bus arbitration method |
| CN101454763A (en) * | 2006-05-24 | 2009-06-10 | 罗伯特.博世有限公司 | Gateway for data transfer between serial buses |
| US20100014427A1 (en) * | 2008-07-18 | 2010-01-21 | Sun Microsystems, Inc. | Arbitration scheme for an optical bus |
| CN103218331B (en) * | 2012-12-07 | 2015-11-11 | 浙江大学 | Synchronous mode is adopted to switch and the self-adjusting bus unit of frame priority and method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506824A (en) * | 2020-12-17 | 2021-03-16 | 上海燧原智能科技有限公司 | Chip and data interaction method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0617368B1 (en) | Arbitration process for controlling data flow through an I/O controller | |
| CN110620731B (en) | Routing device and routing method of network on chip | |
| US6954821B2 (en) | Crossbar switch that supports a multi-port slave device and method of operation | |
| CN1123162C (en) | Communications bus using different transmission rates | |
| US5689644A (en) | Network switch with arbitration sytem | |
| US7826477B2 (en) | Advanced telecommunications router and crossbar switch controller | |
| CN103218331A (en) | Bus device and method by adopting synchronous mode switching and automatic adjustment of frame priority | |
| CN1262009A (en) | Electronic apparatus with a bus | |
| US7003605B2 (en) | Method and system for an improved differential form of transitional coding | |
| US5640519A (en) | Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme | |
| US6553445B1 (en) | Method and apparatus for reducing noise associated with switched outputs | |
| CN111506538A (en) | Time slot splitting relay device for on-chip interconnection bus | |
| CN111478840A (en) | Double-rate arbitration relay device for bus system | |
| CN111314193A (en) | Data transmission bus system, device and method | |
| US7430240B2 (en) | Apparatus and method for automatic polarity swap in a communications system | |
| US6538584B2 (en) | Transition reduction encoder using current and last bit sets | |
| CN111400239A (en) | On-chip distributed interconnection bus system and multi-core processor | |
| US9203739B2 (en) | Adaptive routing apparatus and method | |
| CN111313869B (en) | Clock switching circuit of gigabit Ethernet transceiver | |
| CN111343068A (en) | Double-speed arbitration bus system for giant carrier and carrier | |
| US12093202B2 (en) | DBI encoding device and DBI encoding method | |
| US5784002A (en) | Low-power random digit generator | |
| CN111343069A (en) | Distributed control communication bus based on robot sensing system and robot | |
| CN112968697A (en) | Controller applied to multiplexer and multiplexer | |
| CN111510219A (en) | Bidirectional optical fiber communication method in bus type network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20221018 |
|
| AD01 | Patent right deemed abandoned |