CN111477162A - Pixel circuit and driving method thereof, and display device - Google Patents

Abstract

The invention provides a pixel circuit, a driving method thereof, and a display device, belonging to the technical field of display. The pixel circuit of the present invention includes: a current output subcircuit and a time control subcircuit, the current output subcircuit is configured to generate a driving current and output the driving current to the time control subcircuit; the time control subcircuit is configured to: control according to the time control signal The light-emitting time of the light-emitting sub-circuit; the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp wave writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively It is connected with both ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with both ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit.

Description

Pixel circuit and driving method thereof, and display device

technical field

The invention belongs to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof, and a display device.

Background technique

A light-emitting diode (Light Emitting Diode; LED) is a common electroluminescent device that emits energy through the recombination of electrons and holes, and is widely used in the display field. Since the optical characteristics of the light-emitting diodes change with the current, controlling the brightness of the light-emitting diodes only by the current will result in poor gray-scale uniformity and problems such as color shift.

SUMMARY OF THE INVENTION

The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a pixel circuit capable of improving the duty ratio of controllable light-emitting time.

The technical solution adopted to solve the technical problem of the present invention is a pixel circuit, comprising: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit is configured to: generate a driving current and output all the signals to the time control sub-circuit. the driving current; the time control sub-circuit is configured to: control the light-emitting time of the light-emitting sub-circuit according to the time control signal; the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, a data writing unit, A ramp writing unit and a gating unit; wherein, the control signal writing unit and the data writing unit are respectively connected with both ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with both ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit;

The control signal writing unit is configured to: in response to the control of the scanning end, transmit a time control signal to one end of the capacitance reading unit to which it is connected;

The data writing unit is configured to: in response to the control of the scanning end, transmit an initial data signal to one end of the capacitance reading unit to which it is connected;

The ramp-wave writing unit is configured to: in response to the control of the light-emitting control terminal, transmit a ramp-wave signal to one end of the capacitance reading unit to which it is connected, so as to make the voltage at the other end of the capacitance reading unit change accordingly;

The gating unit is configured to control the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit to which it is connected.

Preferably, the control signal writing unit and the gating unit are connected to the first end of the capacitance reading unit;

the data writing unit and the ramp writing unit are connected to the second end of the capacitance reading unit;

The control signal writing unit is configured to: in response to the control of the scanning end, transmit a time control signal to the first end of the capacitance reading unit;

The data writing unit is configured to: in response to the control of the scanning terminal, transmit an initial data signal to the second terminal of the capacitive reading unit, so as to generate a fixed voltage difference between two ends of the capacitive reading unit.

Preferably, the gating unit includes: a gating transistor and at least one-stage inverter module;

The input end of the first-stage inversion module is connected to one end of the capacitance reading unit, and the output end of the last-stage inversion module is connected to the gate of the gate transistor, and the first pole of the gate transistor is connected to the gate of the gate transistor. The output end of the current output sub-circuit is connected, and the second pole of the gate transistor is connected with the light-emitting sub-circuit;

The inverting module is configured to provide a gate signal or a turn-off signal to the gate transistor in response to a voltage at one end of the capacitance reading unit to which it is connected

Further preferably, the control signal writing unit and the ramp wave writing unit are connected to the first end of the capacitance reading unit;

the data writing unit and the gating unit are connected to the second end of the capacitance reading unit;

The control signal writing unit is configured to transmit a time control signal to the first end of the capacitance reading unit in response to the control of the scanning end.

Further preferably, the capacitance reading unit includes: a second capacitance and a third capacitance; the first-stage inversion module includes: a first driving transistor and a second driving transistor and a light-emitting control unit; the data writing unit Including: a first compensation transistor and a second compensation transistor;

the control signal writing unit, the ramp writing unit, the second capacitor and the first end of the third capacitor are connected to the first node;

The control electrode of the first compensation transistor is connected to the scan terminal; the first electrode of the first compensation transistor is connected to the second electrode of the first driving transistor; the second electrode of the first compensation transistor is connected to the The control electrode of the first driving transistor and the second end of the second capacitor are connected to the second node;

The control electrode of the second compensation transistor is connected to the scan terminal; the first electrode of the second compensation transistor is connected to the first electrode of the second driving transistor; the second electrode of the second compensation transistor is connected to the first electrode of the second driving transistor; The control electrodes of the two driving transistors and the second end of the third capacitor are connected to the third node;

The first pole of the first driving transistor is connected to the first voltage terminal, the second pole is the output terminal of the first-stage inverting module; the first pole of the second driving transistor is connected to the second voltage terminal, and the first pole is connected to the second voltage terminal. The diode passes through the output terminal of the light-emitting control unit and the first-stage inverter module; one of the first driving transistor and the second driving transistor is an N-type transistor, and the other is a P-type transistor ;

The first compensation transistor is configured to: in response to the control of the scan terminal, write the threshold voltage of the first drive transistor and the voltage of the first voltage terminal into the second capacitor;

The second compensation transistor is configured to write the threshold voltage of the second driving transistor and the voltage of the second voltage terminal into the third capacitor in response to the control of the scan terminal.

The light-emitting control unit is configured to: in response to the control of the light-emitting control terminal, turn on the second pole of the second driving transistor and the output terminal of the first-stage inverting module.

Further preferably, the time control sub-circuit element further comprises: a time reset unit;

The time reset unit is configured to provide a reset signal to the control electrode of the first driving transistor and the control electrode of the second driving transistor in response to the control of the second reset terminal.

Further preferably, the time reset unit includes: a second reset transistor and a third reset transistor;

The first pole of the second reset transistor is connected to the first initial voltage terminal, and the second pole of the second reset transistor is connected to the second node;

The first pole of the third reset transistor is connected to the second initial voltage terminal, and the second pole of the third reset transistor is connected to the third node;

Both the control electrode of the second reset transistor and the control electrode of the third reset transistor are connected to the second reset terminal.

Another technical solution adopted to solve the technical problem of the present invention is a display device, which includes the above-mentioned pixel circuit.

Another technical solution adopted to solve the technical problem of the present invention is a driving method applied to any of the above pixel circuits, the driving method comprising:

In the scanning stage, an active level signal is provided to the scanning terminal, so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; at the same time, the control signal writing unit causes the time the control signal is transmitted to the other end of the capacitance reading unit;

In the light-emitting stage, an active level signal is provided to the light-emitting control terminal, so that the ramp-wave writing unit transmits the ramp-wave signal to one end of the capacitance reading unit, so that the other end of the capacitance reading unit is The voltage at one end changes accordingly.

Preferably, the pixel circuit is the pixel circuit of claim 6, and the driving method further comprises:

In the reset phase, an active level signal is provided to the second reset terminal, so that the time reset unit provides a reset signal for the first driving transistor and the second driving transistor.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and together with the following specific embodiments, are used to explain the present invention, but do not constitute a limitation to the present invention. In the attached image:

1-5 and FIG. 7 are schematic structural diagrams of a pixel circuit provided by an embodiment of the present invention;

FIG. 6 is a signal timing diagram of the pixel circuit provided in FIGS. 2-5;

FIG. 8 is a signal timing diagram of the pixel circuit provided in FIG. 7 .

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, but not to limit the present invention.

Unless otherwise defined, the technical or scientific terms used in the embodiments of the present invention shall have the usual meanings understood by those with ordinary skill in the art to which the present invention belongs. The terms "first," "second," and similar terms used herein do not denote any order, quantity, or importance, but are merely used to distinguish different components. Likewise, words like "comprising" or "comprising" mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

At present, the light-emitting time control circuit can be used to adjust the time of the current passing through the light-emitting diode, so as to compensate the brightness of the light-emitting diode and improve the uniformity of gray scale. However, due to the problems of threshold voltage drift and response hysteresis of thin film transistors, it is difficult to accurately control the light-emitting time. Therefore, the light-emitting time control circuit often requires more transistors to compensate for light-emitting control, and the space occupied by the light-emitting time control circuit is relatively small. It is large, which severely limits the resolution (Pixelsperinch; PPI) of the display device.

In view of this, the present invention provides a pixel circuit. FIG. 1 is a schematic structural diagram of the pixel circuit provided by the embodiment of the present invention. As shown in FIG. 1 , the pixel circuit includes: a current output sub-circuit and a light-emitting time control sub-circuit .

Example 1:

As shown in FIGS. 1 to 8 , this embodiment provides a pixel circuit, including: a current output subcircuit and a time control subcircuit, where the current output subcircuit is configured to: generate a driving current and output the driving current to the time control subcircuit; The control sub-circuit is configured to: control the light-emitting time of the light-emitting sub-circuit according to the time control signal; wherein, the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a selection unit A pass unit; wherein, the control signal writing unit and the data writing unit are respectively connected with both ends of the capacitance reading unit; the ramp wave writing unit and the gating unit are respectively connected with both ends of the capacitance reading unit; the current output subcircuit Connect with the gating unit.

In an embodiment of the present invention, the control signal writing unit is configured to: in response to the control of the scanning terminal GateT, transmit the time control signal to one end of the capacitance reading unit connected thereto. As shown in FIG. 1, the control signal writing unit may include a control signal writing transistor T7, the control electrode of the control signal writing transistor T7 is connected to the scanning terminal GateT, and the first electrode of the control signal writing transistor T7 is outputted with the time control signal The terminal DataT is connected, and the second pole of the control signal writing transistor T7 is connected to one terminal of the capacitance reading unit.

The data writing unit is configured to: in response to the control of the scanning terminal GateT, transmit the initial data signal to one end of the capacitance reading unit connected to it; as shown in FIG. 1, opposite to the control signal writing unit, the data writing unit The input unit is connected to the other end of the capacitance reading unit.

The ramp wave writing unit is configured to: in response to the control of the light-emitting control terminal EM, transmit the ramp wave signal to one end of the capacitance reading unit connected thereto, so that the voltage of the other end of the capacitance reading unit changes correspondingly; The gating unit is configured to control the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit connected thereto. As shown in FIG. 1 , the ramp writing unit and the gating unit are respectively connected to two ends of the capacitance reading unit. It should be noted here that, in this embodiment, the control signal writing unit and the ramp signal writing unit may be connected to the same end or different ends of the capacitance reading unit.

Taking a light-emitting period as an example, in the scanning stage (specifically, the time scanning stage), an active level signal is provided to the scanning terminal GateT, and the time control signal writing transistor control signal writing transistor T7 connects the time control signal output terminal DataT with the conduction. , thereby transmitting the time control signal V2 to one end of the capacitance reading unit; at the same time, the data writing unit transmits the initial data signal to one end of the capacitance reading unit connected to it under the control of the scanning terminal GateT, and the capacitance A certain voltage difference is formed between the two ends of the short reading unit. In the light-emitting stage, an effective level signal is provided to the light-emitting control terminal EM, and the ramp-wave writing unit transmits the ramp-wave voltage signal of the reference voltage terminal to one end of the capacitance reading unit. At this time, the voltage difference between the two ends of the capacitance reading unit remains unchanged. As the ramp voltage signal changes, based on the bootstrap effect of the capacitor, the voltage at the other end of the capacitor reading unit (that is, the node connected to the gating unit; the control end of the gating unit) also follows the ramp wave. When the voltage signal rises or falls, when the voltage of the node drops to meet the first voltage, the gating unit turns on the current output sub-circuit and the light-emitting sub-circuit; when the voltage of the node continues to drop to meet the second voltage, The gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.

Among them, the voltage at the control terminal of the gating unit is determined by the voltage difference between the two ends of the capacitance reading unit. Under the condition that the initial data signal is constant, the control terminal of the gating unit can be controlled by adjusting the magnitude and change of the ramp voltage. The duration from the voltage to the threshold voltage that can make the gate unit switch from the "off" state to the "on" state from the start of the display stage, that is, the gate unit is in the "off" state in the display stage. duration. In one cycle (for example, one frame), under the condition that the total duration of the display stage is certain, the duration of controlling the gating unit to be in the “closed” state can be achieved by controlling the duration of the gating unit to be in the “off” state. . Therefore, by adjusting the magnitude and variation of the ramp voltage, the light-emitting duration of the light-emitting device in one cycle can be controlled.

In the embodiment of the present invention, in the light-emitting stage, the ramp voltage signal can be used to drive the voltage of the input terminal of the gate unit to increase or decrease, and the gate unit can be controlled according to the time control signal written to the capacitance reading unit in the scanning stage The speed of the voltage change at the input terminal controls the length of time that the gating unit conducts the current output sub-circuit and the light-emitting sub-circuit, so as to precisely control the light-emitting time of the light-emitting sub-circuit. Since the magnitude of the current flowing through the light-emitting device and the working time of the light-emitting device in one cycle (eg, one frame) affect the effective light-emitting brightness of the light-emitting device in the cycle, the driving current and the time signal provided by the current control circuit 1 The time control voltage provided by the control terminal DataT can control the effective light-emitting brightness of the light-emitting device in this period, so as to achieve the purpose of adjusting the display gray scale.

Preferably, in this embodiment, the current output sub-circuit includes: a first reset transistor T1, a first threshold compensation transistor T2, a current writing transistor T3, a third driving transistor T4, a second light-emitting control transistor T5, and a first light-emitting control transistor T5. Transistor T6 and first capacitor C1. The first pole of the current writing transistor T3 is connected to the driving voltage terminal DataI, the control pole of the current writing transistor T3 is connected to the second scanning terminal GateI, the second pole of the current writing transistor T3, the first pole of the third driving transistor T4 The pole is connected to the first pole of the second light-emitting control transistor T5, the first pole of the third threshold compensation transistor T2 is connected to the second pole of the third driving transistor T4, and the first pole of the first light-emitting control transistor T6; The second pole of the compensation transistor T2 is connected to the control pole of the third driving transistor T4, one end of the first capacitor C1 is connected to the second pole of the first reset transistor T1, and the control pole of the third threshold compensation transistor T2 is connected to the second scanning terminal GateI connected, the second pole of the second light-emitting control transistor T5 is connected to the other end of the first capacitor C1 and the third voltage terminal VDD3, the second pole of the first light-emitting control transistor T6 is connected to the input end of the gating unit, the second light-emitting The control electrode of the control transistor T5 and the control electrode of the first light-emitting control transistor T6 are both connected to the light-emitting control terminal EM, the control electrode of the first reset transistor T1 is connected to the first reset terminal Reset, and the first electrode of the first reset transistor T1 is connected to the light-emitting control terminal EM. The third initial voltage terminal INI3 is connected.

Preferably, the gating unit includes: a gating transistor and at least one stage of inversion module; the input end of the first stage inversion module is connected to one end of the capacitance reading unit, and the output end of the last stage of inversion module is connected to the gate transistor The control pole of the gate is connected to the control pole, the first pole of the gate transistor is connected to the output end of the current output sub-circuit, and the second pole of the gate transistor is connected to the light-emitting sub-circuit; the inversion module is configured to read in response to the connected capacitance The voltage at one end of the cell is taken, and a gate signal or a turn-off signal is provided to the gate transistor.

As shown in FIGS. 2-5 and 7 , in the pixel circuit provided by this embodiment, the gate unit may include one inversion module and one gate transistor, or multiple inversion modules and one gate transistor. When the gating unit includes a plurality of inversion modules, the plurality of inversion modules are cascaded. In this embodiment, the control end of the gating unit is the input end of the first-stage inversion module, which is connected to one end of the capacitance reading unit; the output end of the last-stage inversion module is connected to the control electrode of the gating transistor connected.

Specifically, in this embodiment, one inversion module may include a first driving transistor T9 and a second driving transistor T10. The first pole of the first driving transistor T9 is connected to the first voltage terminal VDD, the first pole of the second driving transistor T10 is connected to the second voltage terminal VSS, and the second pole of the first driving transistor T9 is connected to the second driving transistor T10. The second pole is connected, the control pole of the first driving transistor T9 is connected to the control pole of the second driving transistor T10, one of the first driving transistor T9 and the second driving transistor T10 is an N-type transistor, and the other is a P-type transistor transistor. The gate signal is the voltage signal of the second voltage terminal VSS, and the turn-off signal is the voltage signal of the first voltage terminal VDD.

The effective level signal of the P-type transistor is a low-level voltage signal; the effective-level signal of the N-type transistor is a high-level voltage signal. The voltage provided by the first voltage terminal VDD is a high-level voltage signal, and the voltage provided by the second voltage terminal VSS is a low-level voltage signal. In addition, the first voltage terminals VDD of the inverter modules of different stages can be connected to the same voltage terminal, and the second voltage terminals VSS of the inverter modules of different stages can be connected to the same voltage terminal.

In this embodiment, among multiple cascaded inverter modules, the input terminal of the first-stage inverter module is connected to the control terminal of the gating unit, and the output terminal of the last-stage inverter module is connected to the control terminal of the gating transistor T8 The first pole of the gate transistor T8 is connected to the output end of the current output sub-circuit, and the second pole of the gate transistor T8 is connected to the light-emitting sub-circuit. The plurality of cascaded inversion modules are configured to provide a gate signal to the gate transistor T8 when the control terminal of the gate unit receives the voltage of the first voltage terminal VDD1 in the light-emitting stage. When the control terminal of the strobe unit receives the voltage of the second voltage terminal VSS1, a turn-off signal is provided to the strobe transistor T8.

In the light-emitting stage, since the voltage of the control terminal of the gating unit rises or falls with the ramp voltage signal, and the first driving transistor T9 and the second driving transistor T10 are turned on alternately during the rising or falling process, it will cause An intermediate voltage exists at the output of the first stage inverting unit. Since the intermediate voltage may be smaller than the high-level voltage signal output by the first voltage terminal VDD1, and greater than the low-level voltage signal output by the second voltage terminal VSS1, if the output terminal of the first-stage inverting unit is directly connected to the gate transistor T8 is connected to each other, and the intermediate voltage will cause the magnitude of the light-emitting driving current passing through the gate transistor T8 to change, thereby affecting the light-emitting brightness of the light-emitting device in the light-emitting sub-circuit. In this embodiment, through the setting of the multi-stage inversion module, the first-stage inversion module receives the above-mentioned intermediate state voltage, and after the multi-stage inversion module inverts the phase, the last-stage inversion module will output a The set gate signal or turn-off signal, so that the gate transistor T8 is fully turned on or off, so as to avoid the change in the magnitude of the light-emitting driving current passing through the gate transistor T8.

Preferably, in this embodiment, the light-emitting sub-circuit may include a light-emitting device. The light emitting device may be a light emitting diode (Light Emitting Diode, LED). The input end of the light-emitting device is connected to the output end of the current output sub-circuit through the gating unit. When the gating unit controls the current output sub-circuit and the light-emitting sub-circuit to conduct, the light-emitting driving current output by the current output sub-circuit is transmitted to the light-emitting device, so that the light-emitting device emits light; when the gating unit controls the current output sub-circuit and the light-emitting sub-circuit to disconnect , the light-emitting driving current cannot be transmitted to the light-emitting device, resulting in the light-emitting device being extinguished.

Example 2:

As shown in FIGS. 2 to 6 , this embodiment provides a pixel circuit, which is substantially the same as the pixel circuit provided in Embodiment 1, including: a current output sub-circuit and a time control sub-circuit, and the current output sub-circuit is configured to: generate a driving The current and the drive current are output to the time control sub-circuit; the time control sub-circuit is configured to: control the light-emitting time of the light-emitting sub-circuit according to the time control signal; wherein, the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, A data writing unit, a ramp writing unit and a gating unit; wherein, the control signal writing unit and the data writing unit are respectively connected with both ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with the capacitance Both ends of the reading unit are connected; the current output sub-circuit is connected with the gating unit.

In particular, in this embodiment, the control signal writing unit and the gating unit are connected to the first end of the capacitance reading unit; the data writing unit and the ramp wave writing unit are connected to the second end of the capacitance reading unit The control signal writing unit is configured to: in response to the control of the first scanning terminal GateT, transmit the time control signal to the first end of the capacitance reading unit; the data writing unit is configured to: in response to the first scanning terminal GateT The control of the initial data signal is transmitted to the second end of the capacitance reading unit, so that a fixed voltage difference is generated between the two ends of the capacitance reading unit.

Preferably, as shown in FIGS. 2 to 5 , the capacitance reading unit may include a second capacitor C2, the first terminal of which is connected to the second pole of the control signal writing transistor T7 and the control terminal of the gating unit.

In this embodiment, the data writing unit may include a data writing transistor T11, the control electrode of the data writing transistor T11 is connected to the first scanning terminal GateT, and the first electrode of the data writing transistor T11 is connected to the first reference voltage terminal Commom1 connected, the second pole of the data writing transistor T11 is connected to the second terminal of the second capacitor C2.

Preferably, the ramp wave writing unit may include a light-emitting control transistor T12, the control electrode of the light-emitting control transistor T12 is connected to the light-emitting control terminal EM, the first electrode of the light-emitting control transistor T12 is connected to the second reference voltage terminal Common2, and the light-emitting control transistor T12 is connected to the second reference voltage terminal Common2. The second pole of T12 is connected to the second end of the second capacitor C2.

FIG. 6 is a signal timing diagram of a pixel circuit provided by an embodiment of the present invention. The driving process of the present invention will be explained below with reference to FIGS. 1 to 6 .

In the first reset phase t1 (current reset phase), an active level signal is provided to the first reset terminal Reset. The first reset transistor T1 is turned on to conduct the first initial voltage terminal INI1 and the second terminal of the first capacitor C1. At this stage, the N-node is reset to the corresponding initial voltage.

In the current compensation stage t2, an effective level signal is provided to the second scanning terminal GateI, the current writing transistor T3 is controlled to be turned on, the driving voltage terminal DataI and the first electrode of the third driving transistor T4 are turned on, and the third threshold compensation transistor is turned on. T2 turns on the second terminal of the third driving transistor T4 and the first terminal of the first capacitor C1 to transmit the driving voltage signal VdataI1 output by the driving voltage terminal DataI and the threshold voltage Vth3 of the third driving transistor T4 to the first capacitor C1 the first end.

In the time data reading stage t3, an active level signal is provided to the first scanning terminal GateT, the control signal writing transistor T7 and the data writing transistor T11 are controlled to be turned on, and the time control signal output terminal DataT and the time control signal output terminal DataT are output. The time control signal V of the time control signal output terminal DataT1 and the initial data signal Vcomm1 output by the first reference voltage terminal Commom1 are respectively written into the two ends of the second capacitor C2 (as shown in Figure 2, the M point potential is the V time control signal output Terminal DataT1, the potential of M' point is Vcomm1.) At this stage, because the charge of the second capacitor C2 remains unchanged, the two ends of the second capacitor C2 establish and save the voltage difference ΔV between the two points M and M'.

In the light-emitting stage t4, an effective level signal is provided to the light-emitting control terminal EM, the light-emitting control transistor T12 is turned on, the second reference voltage terminal common2 and the second terminal of the second capacitor C2 are turned on, and the ramp voltage signal Vcom2 is transmitted to At the first end of the second capacitor C2, at this stage, the charge of the second capacitor C2 remains unchanged, and the voltage difference between the potential at point M and the potential at point M' remains unchanged. With the change of the ramp voltage signal, the potential of the M point changes, that is, the potential of the control terminal of the conduction unit is changing, thereby controlling the current output sub-circuit and the light-emitting sub-circuit to be turned on or off.

Theoretically, when the potential of the M point changes to Vth, the conduction unit is turned on, the current output sub-circuit and the light-emitting sub-circuit are turned on, and the light-emitting device lights up and emits light. In order to maintain that the light-emitting time of each row is not affected by the morning or evening of writing data, the ramp voltage signal Vcom2 is set as a periodic ramp signal with a period of 1H. In this way, in each cycle, the light emitting device experiences an off-to-on state. The time ratio of switching depends on the initial potential of the written M point and the variation of the Vcom2 signal. In the case of the timing sequence shown in Figure 4, the ramp voltage signal Vcom2 first decreases and then increases, the higher the initial potential at point M, the later the turn-on time, the earlier the turn-off time, and the lower duty ratio; as the initial potential at point M decreases, the light-emitting Empty ratio increases. When the ramp voltage signal Vcom2 rises first and then falls, vice versa.

It should be noted here that, in this embodiment, a one-stage inversion module is used as an example for description. In order to improve the time control accuracy, a multi-stage inversion module can be set. For the specific control and timing, please refer to the above description. The example is not repeated here.

Example 3:

As shown in FIGS. 7 and 8 , this embodiment provides a pixel circuit, which generally includes the pixel circuit provided in Embodiment 1, and specifically includes: a current output sub-circuit and a time control sub-circuit, and the current output sub-circuit is configured to: generate a driving The current and the drive current are output to the time control sub-circuit; the time control sub-circuit is configured to: control the light-emitting time of the light-emitting sub-circuit according to the time control signal; wherein, the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, A data writing unit, a ramp writing unit and a gating unit; wherein, the control signal writing unit and the data writing unit are respectively connected with both ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with the capacitance Both ends of the reading unit are connected; the current output sub-circuit is connected with the gating unit.

The pixel circuit provided in this embodiment is similar to the pixel circuit provided in Embodiment 2. In particular, in this embodiment, the control signal writing unit and the ramp wave writing unit are connected to the first end of the capacitance reading unit; The input unit and the gating unit are connected to the second end of the capacitance reading unit; the control signal writing unit is configured to: in response to the control of the scanning end, transmit the time control signal to the first end of the capacitance reading unit.

In the scanning stage (specifically, the time scanning stage), an active level signal is provided to the first scanning terminal GateT, and the time control signal writing transistor T7 turns on the time control signal output terminal DataT, thereby transmitting the time control signal V2 to the second scanning terminal GateT. The first end of the capacitor C2 and the first end of the third capacitor C3; at the same time, the data writing unit transmits the initial data signal to the second end of the second capacitor C2 and the second end of the third capacitor C3 under the control of the scanning end terminal, the two terminals of the second capacitor C2 and the two terminals of the third capacitor C3 respectively form a voltage difference. In the light-emitting stage, an effective level signal is provided to the light-emitting control terminal EM, and the ramp-wave writing unit transmits the ramp-wave voltage signal of the reference voltage terminal to the first end of the second capacitor C2 and the first end of the third capacitor C3. , the voltage difference between the two ends of the capacitor reading unit remains unchanged. With the change of the ramp voltage signal, the bootstrap effect of the capacitor, the voltage of the first end of the second capacitor C2 and the second end of the third capacitor C3 also follow the ramp wave The wave voltage signal rises or falls, when the voltage of the node drops to meet the first voltage, the gating unit turns on the current output sub-circuit and the light-emitting sub-circuit; when the voltage of the node continues to drop to meet the second voltage , the gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.

Preferably, in this embodiment, the capacitance reading unit includes: a second capacitor C2 and a third capacitor C3; the first-stage inverting module includes: a first driving transistor T9 and a second driving transistor T10 and a light-emitting control unit; data writing The input unit includes: a first compensation transistor T13 and a second compensation transistor T14.

As shown in FIG. 7 , the control signal writing unit, the ramp writing unit and the first ends of the second capacitor C2 and the third capacitor C3 are connected to the first node M1; the control electrode of the first compensation transistor T13 is connected to the first node M1. The scanning terminal GateT is connected; the first pole of the first compensation transistor T13 is connected to the second pole of the first driving transistor T9; the second pole of the first compensation transistor T13 is connected to the second pole of the first driving transistor T9 The control electrode and the second end of the second capacitor C2 are connected to T14; the control electrode of the second compensation transistor T14 is connected to the first scanning end GateT; the first electrode of the second compensation transistor T14 is connected to the second The first pole of the driving transistor T10 is connected; the second pole of the second compensation transistor T14 and the control pole of the second driving transistor T10 and the second terminal of the third capacitor C3 are connected to the third node M3.

The first pole of the first driving transistor T9 is connected to the first voltage terminal, and the second pole is the output terminal of the first-stage inverter module; the first pole of the second driving transistor T10 is connected to the second voltage terminal, and the second pole emits light through The output end of the control unit and the first-stage inverting module; one of the first driving transistor T9 and the second driving transistor T10 is an N-type transistor, and the other is a P-type transistor.

The first compensation transistor T13 is configured to: in response to the control of the first scanning terminal GateT, write the threshold voltage of the first driving transistor T9 and the voltage of the first voltage terminal into the second capacitor C2; the second compensation transistor T14 is configured to: In response to the control of the first scanning terminal GateT, the threshold voltage of the second driving transistor T10 and the voltage of the second voltage terminal are written into the third capacitor C3. The light-emitting control unit is configured to: in response to the control of the light-emitting control terminal EM, to conduct the second pole of the second driving transistor T10 with the output terminal of the first-stage inverting module.

Preferably, the ramp wave writing unit may include a light-emitting control transistor T12, the control electrode of the light-emitting control transistor T12 is connected to the light-emitting control terminal EM, the first electrode of the light-emitting control transistor T12 is connected to the second reference voltage terminal Common2, and the light-emitting control transistor T12 is connected to the second reference voltage terminal Common2. The second pole of T12 is connected to the first terminals of the second capacitor C2 and the third capacitor C3 (ie, the first node M1).

In the embodiment of the present invention, the threshold voltages of the first drive transistor T9 and the second drive transistor TT10 of the first-stage inverter module can be compensated by the data writing unit, and the threshold voltage drift of the first drive transistor T9 and the first drive transistor T9 and the second drive transistor TT10 can be eliminated by eliminating the threshold voltage drift. The influence of the second driving transistor T10 improves the accuracy of the turn-on (or turn-off) time control of the gate unit by the first driving transistor T9 and the second driving transistor T10.

In the light-emitting stage, since the voltage of the third node M3 and the voltage of the fourth node M4 rise or fall with the ramp voltage signal, and the first driving transistor T9 and the second driving transistor T10 are alternated during the rising or falling process Turning on, therefore, results in an intermediate voltage at the second node M2. Since the intermediate voltage may be smaller than the high-level voltage signal output by the first voltage terminal VDD1 and greater than the low-level voltage signal output by the second voltage terminal VSS1, if the second node N2 is directly connected to the gate transistor T8, the intermediate voltage The state voltage will cause a change in the magnitude of the light-emitting driving current passing through the gate transistor T8, thereby affecting the light-emitting brightness of the light-emitting device in the light-emitting sub-circuit.

Preferably, in this embodiment, the time control sub-circuit element further includes: a time reset unit; the time reset unit is configured to: in response to the control of the second reset terminal RSTT, the control electrode of the first drive transistor T9 and the second drive The gate of transistor T10 provides a reset signal.

Preferably, the time reset unit includes: a second reset transistor T15 and a third reset transistor T16; the first pole of the second reset transistor T15 is connected to the second initial voltage terminal INI2, and the second pole of the second reset transistor T15 is connected to the second node The first pole of the third reset transistor T16 is connected to the third initial voltage terminal INI3, and the second pole of the third reset transistor T16 is connected to the third node; the control pole of the second reset transistor T15 is connected to the third reset transistor T16. The control electrodes are all connected to the second reset terminal RSTT.

FIG. 8 is a signal timing diagram of a pixel circuit provided by an embodiment of the present invention. The driving process of the present invention will be explained below with reference to FIGS. 7 and 8 .

In the first reset phase t1 (current reset phase), an active level signal is provided to the first reset terminal Reset, the first reset transistor T1 is turned on, and the first initial voltage terminal INI1 is connected to the second terminal of the first capacitor C1. At this stage, the N-node is reset to the corresponding initial voltage.

In the current compensation stage t2, an effective level signal is provided to the second scanning terminal GateI, the current writing transistor T3 is controlled to be turned on, the driving voltage terminal DataI and the first electrode of the third driving transistor T4 are turned on, and the third threshold compensation transistor is turned on. T2 turns on the second terminal of the third driving transistor T4 and the first terminal of the first capacitor C1 to transmit the driving voltage signal VdataI1 output by the driving voltage terminal DataI and the threshold voltage Vth3 of the third driving transistor T4 to the first capacitor C1 the first end.

In the second reset phase t3 (time reset phase), an active level signal is provided to the second reset terminal RSTT, the second reset transistor T15 and the third reset transistor T16 are turned on, and the second reset transistor T15 connects the second initial voltage terminal INI2 with the second initial voltage terminal INI2. The second terminal of the second capacitor C2 is turned on, and the third reset transistor T16 turns on the third initial voltage terminal INI3 and the first terminal of the third capacitor C3. At this stage, both the second node M2 and the third node M3 are reset to corresponding initial voltages.

In the data reading stage t4, an active level signal is provided to the first scanning terminal GateT, the control signal writing transistor T7 is turned on, and the time control signal VdataT1 output by the time control signal output terminal DataT is written into the second capacitor C2 and the second capacitor C2 respectively. The first terminals of the three capacitors C3; at the same time, the first scanning terminal GateT controls the first compensation transistor T13 and the second compensation transistor T14 to be turned on.

At this stage, the voltages of the first terminals of the second capacitor C2 and the third capacitor C3 are both VdataT1, the voltage of the M2 node is V1+Vth1, and the voltage of the M3 node is V2+Vth2, where V1 is the output of the first voltage terminal VDD1. The voltage, V2 is the voltage output by the second voltage terminal VSS1, Vth1 is the threshold voltage of the first driving transistor T9, and Vth2 is the threshold voltage of the second driving transistor T10.

In the t5 stage, it is the full-screen data reading and compensation stage.

In the light-emitting stage t6, an effective level signal is provided to the light-emitting control terminal EM. The light-emitting control transistor T12 conducts the reference voltage terminal common with the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3, and the ramp voltage signal Vcom is transmitted to the first terminal of the second capacitor C2 and the third capacitor C3 At the first end, T23 conducts the second pole of the second driving transistor T10 with the node M, thereby conducting the second pole of the gate transistor T8 with the light-emitting device, or through the cascaded multi-level inversion modules to select The second pole of the pass transistor T8 is turned on with the light emitting device.

At this stage, the voltage of the second capacitor C2 and the voltage of the first end of the third capacitor C3 are VdataT1, the voltage of the N1 node is V1+Vth1+ΔV1, and the voltage of the N2 node is V2+Vth2+ΔV1, where ΔV1 is a ramp wave The difference between the voltage signal Vcom and the time control signal VdataT1, that is, ΔV1=Vcom−VdataT1. The gate-source voltage of the first drive transistor T9 is Vgs1=V1+Vth1+ΔV1-V1, the gate-source voltage of the second drive transistor T10 is Vgs2=V2+Vth2+ΔV1-V2, the gate-source voltage of the third drive transistor T4 is Vgs3=VdataI1 +Vth3-V3, the light-emitting driving current I1=k(Vgs3-Vth3)^2=k(Vd ataI1+Vth3-V3-Vth3)^2 output by the third driving transistor T4. Since the first driving transistor T9 is a P-type transistor and the second driving transistor T10 is an N-type transistor, when Vgs1-Vth1<0, Vgs2-Vth2<0, the first driving transistor T9 is turned on, and the second driving transistor T10 is turned off , at this time, ΔV1<0, which corresponds to the time period when the current voltage of the ramp voltage signal Vcom is smaller than the voltage of the time control signal VdataT1 (ie, the time period t6 in FIG. 4 ). The voltage V1 output by the first voltage terminal VDD1 is transmitted to the first-stage inversion module 321, the second driving transistor T10 in the first-stage inversion module 321 is turned on, and the low-level signal output by the second voltage terminal VSS1 is transmitted to the selector. The gate of the transistor T8 is turned on, and the low level signal is used as the gate signal of the gate transistor T8, so that the gate transistor T8 is turned on, and the light-emitting drive current I1 output by the second pole of the first light-emitting control transistor T6 is It is transmitted to the light-emitting device, and the light-emitting device LED emits light according to the magnitude of the light-emitting driving current I1 and the turn-on time of the gating unit. When Vgs1-Vth1>0, Vgs2-Vth2>0, the first driving transistor T9 is turned off, and the second driving transistor T10 is turned on, at this time, ΔV1>0, corresponding to the current voltage of the ramp voltage signal Vcom greater than the time control signal During the period of VdataT1, the voltage V2 output by the second voltage terminal VSS1 is transmitted to the next-stage inversion module 321, the first inversion transistor T10 in the next-stage inversion module is turned on, and the first voltage terminal outputs a high level The signal is transmitted to the control electrode of the gate transistor T8, and the high level signal is used as the turn-off signal of the gate transistor T8, so that the light-emitting driving current I cannot be transmitted to the light-emitting device LED, and the light-emitting device LED is turned off.

That is to say, in this embodiment, through the setting of the data writing unit, the threshold value compensation is performed on the capacitance reading unit, so that the jumping (on and off transition) conditions of the first-stage inversion module of the gating unit are only It is related to ΔV, independent of Vth. The output of the first-stage inversion module is independent of Vth, thereby ensuring that the entire pixel circuit is independent of Vth.

It can be understood that, in this embodiment, the gating unit includes a first-stage inverter module as an example for description. When the strobing unit includes multi-stage inversion modules, the first-stage inversion module can be compensated by the data writing unit, because the output of the first-stage inversion module has nothing to do with Vth, and the output Vth of the subsequent stages of inversion modules The effect is small, thus ensuring that the overall pixel circuit is independent of Vth. It can be understood that those skilled in the art can select the number of stages of the inversion modules of the gating unit according to the control accuracy of the time, and the number of stages of the inversion modules included in the gating unit is not specifically limited in this embodiment.

Example 4:

This embodiment provides a display device, and an embodiment of the present invention also provides a display device, which includes the pixel circuit in the above-mentioned embodiment of the present invention.

The display device can be any product or component with display function, such as electronic paper, OLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, and navigator.

The display device adopts the above-mentioned pixel circuit, so the light-emitting time of a plurality of light-emitting devices can be controlled by one light-emitting time control sub-circuit, which greatly reduces the space occupied by the light-emitting time control sub-circuit, thereby increasing the pixel density of the display device.

Example 5:

An embodiment of the present invention further provides a driving method applied to the pixel circuit in the above-mentioned embodiment, wherein the driving method includes:

In the scanning stage, an active level signal is provided to the scanning terminal, so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; at the same time, the control signal writing unit transmits the time control signal to the other end of the capacitance reading unit one end;

In the light-emitting stage, an effective level signal is provided to the light-emitting control terminal EM, so that the ramp-wave writing unit transmits the ramp-wave signal to one end of the capacitance reading unit, so that the voltage at the other end of the capacitance reading unit changes accordingly.

Optionally, the active level signal is a low level signal. Taking a light-emitting period as an example, in the scanning stage (specifically, the time scanning stage), an active level signal is provided to the scanning terminal GateT, and the time control signal writing transistor control signal writing transistor T7 connects the time control signal output terminal DataT with the conduction. , thereby transmitting the time control signal V2 to one end of the capacitance reading unit; at the same time, the data writing unit transmits the initial data signal to one end of the capacitance reading unit connected to it under the control of the scanning terminal GateT, and the capacitance A certain voltage difference is formed between the two ends of the short reading unit. In the light-emitting stage, an effective level signal is provided to the light-emitting control terminal EM, and the ramp-wave writing unit transmits the ramp-wave voltage signal of the reference voltage terminal to one end of the capacitance reading unit. At this time, the voltage difference between the two ends of the capacitance reading unit remains unchanged. As the ramp voltage signal changes, based on the bootstrap effect of the capacitor, the voltage at the other end of the capacitor reading unit (that is, the node connected to the gating unit; the control end of the gating unit) also follows the ramp wave. The voltage signal rises or falls, when the voltage of the node drops to meet the first voltage, the gating unit turns on the current output sub-circuit and the light-emitting sub-circuit; when the voltage of the node continues to drop to meet the second voltage, The gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.

In the embodiment of the present invention, in the light-emitting phase, the voltage across the capacitor reading unit may be driven to increase or decrease by the ramp voltage signal, and the first time control signal to be written into the capacitor reading unit in the data writing phase may be used to control the first The turn-on time of the first drive transistor T9 and the turn-on time of the second drive transistor T10 control the length of the turn-on time of the current output sub-circuit and the light-emitting sub-circuit of the gating unit.

Preferably, the pixel circuit includes a reset unit, and the driving method further includes: in the reset stage, providing an active level signal to the second reset terminal RSTT, so that the time reset unit provides a reset signal for the first driving transistor T9 and the second driving transistor T10 .

It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present invention, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (10)

1. A pixel circuit, comprising: a current output subcircuit and a time control subcircuit, the current output subcircuit is configured to: generate a drive current and output the drive current to the time control subcircuit; the time control subcircuit The circuit is configured to: control the light-emitting time of the light-emitting sub-circuit according to the time control signal; it is characterized in that, the time control sub-circuit includes: a control signal writing unit, a capacitance reading unit, a data writing unit, and a ramp writing unit and a gating unit; wherein, the control signal writing unit and the data writing unit are respectively connected with both ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with the capacitance The two ends of the reading unit are connected; the current output sub-circuit is connected with the gating unit; The control signal writing unit is configured to: in response to the control of the scanning end, transmit a time control signal to one end of the capacitance reading unit to which it is connected; The data writing unit is configured to: in response to the control of the scanning end, transmit an initial data signal to one end of the capacitance reading unit to which it is connected; The ramp-wave writing unit is configured to: in response to the control of the light-emitting control terminal, transmit a ramp-wave signal to one end of the capacitance reading unit to which it is connected, so as to make the voltage at the other end of the capacitance reading unit change accordingly; The gating unit is configured to control the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit to which it is connected. 2. The pixel circuit according to claim 1, wherein the control signal writing unit and the gating unit are connected to the first end of the capacitance reading unit; the data writing unit and the ramp writing unit are connected to the second end of the capacitance reading unit; The control signal writing unit is configured to: in response to the control of the scanning end, transmit a time control signal to the first end of the capacitance reading unit; The data writing unit is configured to: in response to the control of the scanning terminal, transmit an initial data signal to the second terminal of the capacitive reading unit, so as to generate a fixed voltage difference between two ends of the capacitive reading unit. 3. The pixel circuit according to claim 1, wherein the gating unit comprises: a gating transistor and at least one stage of an inverting module; The input end of the first-stage inversion module is connected to one end of the capacitance reading unit, and the output end of the last-stage inversion module is connected to the gate of the gate transistor, and the first pole of the gate transistor is connected to the gate of the gate transistor. The output end of the current output sub-circuit is connected, and the second pole of the gate transistor is connected with the light-emitting sub-circuit; The inverting module is configured to provide a gate signal or a turn-off signal to the gate transistor in response to a voltage at one end of the capacitance reading unit to which it is connected. 4. The pixel circuit according to claim 3, wherein the control signal writing unit and the ramp wave writing unit are connected to the first end of the capacitance reading unit; the data writing unit and the gating unit are connected to the second end of the capacitance reading unit; The control signal writing unit is configured to transmit a time control signal to the first end of the capacitance reading unit in response to the control of the scanning end. 5. The pixel circuit according to claim 4, wherein the capacitance reading unit comprises: a second capacitance and a third capacitance; the first-stage inverting module comprises: a first driving transistor and a second driving a transistor and a light-emitting control unit; the data writing unit includes: a first compensation transistor and a second compensation transistor; the control signal writing unit, the ramp writing unit, the second capacitor and the first end of the third capacitor are connected to the first node; The control electrode of the first compensation transistor is connected to the scan terminal; the first electrode of the first compensation transistor is connected to the second electrode of the first driving transistor; the second electrode of the first compensation transistor is connected to the The control electrode of the first driving transistor and the second end of the second capacitor are connected to the second node; The control electrode of the second compensation transistor is connected to the scan terminal; the first electrode of the second compensation transistor is connected to the first electrode of the second driving transistor; the second electrode of the second compensation transistor is connected to the first electrode of the second driving transistor; The control electrodes of the two driving transistors and the second end of the third capacitor are connected to the third node; The first pole of the first driving transistor is connected to the first voltage terminal, the second pole is the output terminal of the first-stage inverting module; the first pole of the second driving transistor is connected to the second voltage terminal, and the first pole is connected to the second voltage terminal. The diode passes through the output terminal of the light-emitting control unit and the first-stage inverter module; one of the first driving transistor and the second driving transistor is an N-type transistor, and the other is a P-type transistor ; The first compensation transistor is configured to: in response to the control of the scan terminal, write the threshold voltage of the first drive transistor and the voltage of the first voltage terminal into the second capacitor; The second compensation transistor is configured to write the threshold voltage of the second driving transistor and the voltage of the second voltage terminal into the third capacitor in response to the control of the scan terminal. The light-emitting control unit is configured to: in response to the control of the light-emitting control terminal, turn on the second pole of the second driving transistor and the output terminal of the first-stage inverting module. 6. The pixel circuit according to claim 5, wherein the time control sub-circuit element further comprises: a time reset unit; The time reset unit is configured to provide a reset signal to the control electrode of the first driving transistor and the control electrode of the second driving transistor in response to the control of the second reset terminal. 7. The pixel circuit according to claim 6, wherein the time reset unit comprises: a second reset transistor and a third reset transistor; The first pole of the second reset transistor is connected to the first initial voltage terminal, and the second pole of the second reset transistor is connected to the second node; The first pole of the third reset transistor is connected to the second initial voltage terminal, and the second pole of the third reset transistor is connected to the third node; Both the control electrode of the second reset transistor and the control electrode of the third reset transistor are connected to the second reset terminal. 8. A display device, comprising the pixel circuit according to any one of claims 1 to 7. 9. A driving method applied to the pixel circuit according to any one of claims 1 to 7, wherein the driving method comprises: In the scanning stage, an active level signal is provided to the scanning terminal, so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; at the same time, the control signal writing unit causes the time the control signal is transmitted to the other end of the capacitance reading unit; In the light-emitting stage, an active level signal is provided to the light-emitting control terminal, so that the ramp-wave writing unit transmits the ramp-wave signal to one end of the capacitance reading unit, so that the other end of the capacitance reading unit is The voltage at one end changes accordingly. 10 . The driving method of a pixel circuit according to claim 9 , wherein the pixel circuit is the pixel circuit according to claim 6 , and the driving method further comprises: 10 . In the reset phase, an active level signal is provided to the second reset terminal, so that the time reset unit provides a reset signal for the first driving transistor and the second driving transistor.

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